arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x500>;
  45                 };
  46                 cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x501>;
  50                 };
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <0x502>;
  55                 };
  56                 cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x503>;
  60                 };
  61         };
  62
  63         gic: interrupt-controller@ffc01000 {
  64                 compatible = "arm,cortex-a15-gic";
  65                 interrupt-controller;
  66                 #interrupt-cells = <3>;
  67                 #address-cells = <0>;
  68                 reg = <0xffc01000 0x1000>,
  69                       <0xffc02000 0x1000>;
  70         };
  71
  72         cpu_axi_bus: cpu_axi_bus {
  73                 compatible = "rockchip,cpu_axi_bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77                 qos {
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges;
  81                         /* service core */
  82                         cpup {
  83                                 reg = <0xffa80000 0x20>;
  84                         };
  85                         cpum_r {
  86                                 reg = <0xffa80080 0x20>;
  87                         };
  88                         cpum_w {
  89                                 reg = <0xffa80100 0x20>;
  90                         };
  91                         /* service dmac */
  92                         bus_dmac {
  93                                 reg = <0xffa90000 0x20>;
  94                         };
  95                         host {
  96                                 reg = <0xffa90080 0x20>;
  97                         };
  98                         crypto {
  99                                 reg = <0xffa90100 0x20>;
 100                         };
 101                         ccp {
 102                                 reg = <0xffa90180 0x20>;
 103                         };
 104                         ccs {
 105                                 reg = <0xffa90200 0x20>;
 106                         };
 107                         /* service gpu */
 108                         gpu_r {
 109                                 reg = <0xffaa0000 0x20>;
 110                         };
 111                         gpu_w {
 112                                 reg = <0xffaa0080 0x20>;
 113                         };
 114                         /* service peri */
 115                         peri {
 116                                 reg = <0xffab0000 0x20>;
 117                         };
 118                         /* service vio */
 119                         vio1_vop {
 120                                 reg = <0xffad0000 0x20>;
 121                                 rockchip,priority = <2 2>;
 122                         };
 123                         vio1_isp_w0 {
 124                                 reg = <0xffad0100 0x20>;
 125                         };
 126                         vio1_isp_w1 {
 127                                 reg = <0xffad0180 0x20>;
 128                         };
 129                         vio0_vop {
 130                                 reg = <0xffad0400 0x20>;
 131                                 rockchip,priority = <2 2>;
 132                         };
 133                         vio0_vip {
 134                                 reg = <0xffad0480 0x20>;
 135                         };
 136                         vio0_iep {
 137                                 reg = <0xffad0500 0x20>;
 138                         };
 139                         vio2_rga_r {
 140                                 reg = <0xffad0800 0x20>;
 141                         };
 142                         vio2_rga_w {
 143                                 reg = <0xffad0880 0x20>;
 144                         };
 145                         vio1_isp_r {
 146                                 reg = <0xffad0900 0x20>;
 147                         };
 148                         /* service video */
 149                         video {
 150                                 reg = <0xffae0000 0x20>;
 151                         };
 152                         /* service hevc */
 153                         hevc_r {
 154                                 reg = <0xffaf0000 0x20>;
 155                         };
 156                         hevc_w {
 157                                 reg = <0xffaf0080 0x20>;
 158                         };
 159                 };
 160                 msch {
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges;
 164                         msch@0 {
 165                                 reg = <0xffac0000 0x40>;
 166                                 rockchip,read-latency = <0xff>;
 167                         };
 168                         msch@1 {
 169                                 reg = <0xffac0080 0x40>;
 170                                 rockchip,read-latency = <0xff>;
 171                         };
 172                 };
 173         };
 174
 175         sram: sram@ff710000 {
 176                 compatible = "mmio-sram";
 177                 reg = <0xff710000 0x8000>; /* 32k */
 178                 map-exec;
 179         };
 180
 181         timer {
 182                 compatible = "arm,armv7-timer";
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 185                 clock-frequency = <24000000>;
 186         };
 187
 188         timer@ff810000 {
 189                 compatible = "rockchip,timer";
 190                 reg = <0xff810000 0x20>;
 191                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 192                 rockchip,broadcast = <1>;
 193         };
 194
 195         watchdog:wdt@2004c000 {
 196                 compatible = "rockchip,watch dog";
 197                 reg = <0xff800000 0x100>;
 198                 clocks = <&pclk_pd_alive>;
 199                 clock-names = "pclk_wdt";
 200                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,irq = <0>;
 202                 rockchip,timeout = <60>;
 203                 rockchip,atboot = <1>;
 204                 rockchip,debug = <0>;
 205                 status = "disable";
 206         };
 207
 208     amba {
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 compatible = "arm,amba-bus";
 212                 interrupt-parent = <&gic>;
 213                 ranges;
 214
 215                 pdma0: pdma@ffb20000 {
 216                         compatible = "arm,pl330", "arm,primecell";
 217                         reg = <0xffb20000 0x4000>;
 218                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 220                         #dma-cells = <1>;
 221                 };
 222
 223                 pdma1: pdma@ff250000 {
 224                         compatible = "arm,pl330", "arm,primecell";
 225                         reg = <0xff250000 0x4000>;
 226                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 228                         #dma-cells = <1>;
 229                 };
 230         };
 231
 232
 233         emmc: rksdmmc@ff0f0000 {
 234                 compatible = "rockchip,rk_mmc";
 235                 device_type = "emmc";
 236                 reg = <0xff0f0000 0x4000>;
 237                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 //pinctrl-names = "default",,"suspend";
 241                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 242                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 243                 clock-names = "clk_mmc", "hclk_mmc";
 244                 num-slots = <1>;
 245                 fifo-depth = <0x100>;
 246                 bus-width = <8>;
 247         };
 248
 249         sdmmc: rksdmmc@ff0c0000 {
 250                 compatible = "rockchip,rk_mmc";
 251                 device_type = "sdmmc";
 252                 reg = <0xff0c0000 0x4000>;
 253                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 pinctrl-names = "default","idle";
 257                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 258                 pinctrl-1 = <&sdmmc0_gpio>;
 259                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 260                 clock-names = "clk_mmc", "hclk_mmc";
 261                 num-slots = <1>;
 262                 fifo-depth = <0x100>;
 263                 bus-width = <4>;
 264
 265         };
 266
 267         sdio: rksdmmc@ff0d0000 {
 268                 compatible = "rockchip,rk_mmc";
 269                 device_type = "sdio";
 270                 reg = <0xff0d0000 0x4000>;
 271                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274                 pinctrl-names = "default","idle";
 275                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_dectn  &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 276                                          &sdio0_intn &sdio0_bus4>;
 277                 pinctrl-1 = <&sdio0_gpio>;
 278                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 279                 clock-names = "clk_mmc", "hclk_mmc";
 280                 num-slots = <1>;
 281                 fifo-depth = <0x100>;
 282                 bus-width = <4>;
 283         };
 284
 285     sdio1: rksdmmc@ff0e0000 {
 286                 compatible = "rockchip,rk_mmc";
 287         device_type = "sdio";
 288                 reg = <0xff0e0000 0x4000>;
 289         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 290         #address-cells = <1>;
 291         #size-cells = <0>;
 292         //pinctrl-names = "default","suspend";
 293         //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 294         /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 295         clocks = <&clk_sdio1>, <&clk_gates8 5>;
 296         clock-names = "clk_mmc", "hclk_mmc";
 297         num-slots = <1>;
 298         fifo-depth = <0x100>;
 299         bus-width = <4>;
 300                 status = "disabled";
 301         };
 302
 303         spi0: spi@ff110000 {
 304                 compatible = "rockchip,rockchip-spi";
 305                 reg = <0xff110000 0x1000>;
 306                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 311                 rockchip,spi-src-clk = <0>;
 312                 num-cs = <2>;
 313                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 314                 clock-names = "spi","pclk_spi0";
 315                 //dmas = <&pdma1 11>, <&pdma1 12>;
 316                 //#dma-cells = <2>;
 317                 //dma-names = "tx", "rx";
 318                 status = "disabled";
 319         };
 320
 321         spi1: spi@ff120000 {
 322                 compatible = "rockchip,rockchip-spi";
 323                 reg = <0xff120000 0x1000>;
 324                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 329                 rockchip,spi-src-clk = <1>;
 330                 num-cs = <1>;
 331                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 332                 clock-names = "spi","pclk_spi1";
 333                 //dmas = <&pdma1 13>, <&pdma1 14>;
 334                 //#dma-cells = <2>;
 335                 //dma-names = "tx", "rx";
 336                 status = "disabled";
 337         };
 338
 339         spi2: spi@ff130000 {
 340                 compatible = "rockchip,rockchip-spi";
 341                 reg = <0xff130000 0x1000>;
 342                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 347                 rockchip,spi-src-clk = <2>;
 348                 num-cs = <2>;
 349                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 350                 clock-names = "spi","pclk_spi2";
 351                 //dmas = <&pdma1 15>, <&pdma1 16>;
 352                 //#dma-cells = <2>;
 353                 //dma-names = "tx", "rx";
 354                 status = "disabled";
 355         };
 356
 357         uart_bt: serial@ff180000 {
 358                 compatible = "rockchip,serial";
 359                 reg = <0xff180000 0x100>;
 360                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 361                 clock-frequency = <24000000>;
 362                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 363                 clock-names = "sclk_uart", "pclk_uart";
 364                 reg-shift = <2>;
 365                 reg-io-width = <4>;
 366                 dmas = <&pdma1 1>, <&pdma1 2>;
 367                 #dma-cells = <2>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 370                 status = "disabled";
 371         };
 372
 373         uart_bb: serial@ff190000 {
 374                 compatible = "rockchip,serial";
 375                 reg = <0xff190000 0x100>;
 376                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 377                 clock-frequency = <24000000>;
 378                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 379                 clock-names = "sclk_uart", "pclk_uart";
 380                 reg-shift = <2>;
 381                 reg-io-width = <4>;
 382                 dmas = <&pdma1 3>, <&pdma1 4>;
 383                 #dma-cells = <2>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 386                 status = "disabled";
 387         };
 388
 389         uart_dbg: serial@ff690000 {
 390                 compatible = "rockchip,serial";
 391                 reg = <0xff690000 0x100>;
 392                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 393                 clock-frequency = <24000000>;
 394                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 395                 clock-names = "sclk_uart", "pclk_uart";
 396                 reg-shift = <2>;
 397                 reg-io-width = <4>;
 398                 dmas = <&pdma0 4>, <&pdma0 5>;
 399                 #dma-cells = <2>;
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&uart2_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         uart_gps: serial@ff1b0000 {
 406                 compatible = "rockchip,serial";
 407                 reg = <0xff1b0000 0x100>;
 408                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 409                 clock-frequency = <24000000>;
 410                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 411                 clock-names = "sclk_uart", "pclk_uart";
 412                 current-speed = <115200>;
 413                 reg-shift = <2>;
 414                 reg-io-width = <4>;
 415                 dmas = <&pdma1 7>, <&pdma1 8>;
 416                 #dma-cells = <2>;
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 419                 status = "disabled";
 420         };
 421
 422         uart_exp: serial@ff1c0000 {
 423                 compatible = "rockchip,serial";
 424                 reg = <0xff1c0000 0x100>;
 425                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 426                 clock-frequency = <24000000>;
 427                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 428                 clock-names = "sclk_uart", "pclk_uart";
 429                 reg-shift = <2>;
 430                 reg-io-width = <4>;
 431                 dmas = <&pdma1 9>, <&pdma1 10>;
 432                 #dma-cells = <2>;
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 435                 status = "disabled";
 436         };
 437
 438         fiq-debugger {
 439                 compatible = "rockchip,fiq-debugger";
 440                 rockchip,serial-id = <2>;
 441                 rockchip,signal-irq = <106>;
 442                 rockchip,wake-irq = <0>;
 443                 status = "disabled";
 444         };
 445
 446         clocks-init{
 447                 compatible = "rockchip,clocks-init";
 448                 rockchip,clocks-init-parent =
 449                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 450                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 451                         <&clk_i2s_pll &clk_cpll>;
 452                 rockchip,clocks-init-rate =
 453                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 454                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 455                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 456                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 457                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 458                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 459                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 460                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 461                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 462                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 463                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 464                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 465                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 466                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 467                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 468                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 469         };
 470
 471         clocks-enable {
 472                 compatible = "rockchip,clocks-enable";
 473                 clocks =
 474                                 /*PD_CORE*/
 475                                 <&clk_gates0 2>, <&clk_core0>,
 476                                 <&clk_core1>, <&clk_core2>,
 477                                 <&clk_core3>, <&clk_l2ram>,
 478                                 <&aclk_core_m0>, <&aclk_core_mp>,
 479                                 <&atclk_core>, <&pclk_dbg_src>,
 480
 481                                 /*PD_BUS*/
 482                                 <&aclk_bus>, <&clk_gates0 3>,
 483                                 <&hclk_bus>, <&pclk_bus>,
 484                                 <&clk_gates13 8>, <&clk_crypto>,
 485                                 <&clk_gates0 7>,
 486
 487                                 /*TIMER*/
 488                                 <&clk_gates1 0>, <&clk_gates1 1>,
 489                                 <&clk_gates1 2>, <&clk_gates1 3>,
 490                                 <&clk_gates1 4>, <&clk_gates1 5>,
 491
 492                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 493
 494                                 /*PD_PERI*/
 495                                 <&aclk_peri>, <&hclk_peri>,
 496                                 <&pclk_peri>,
 497
 498                                 /*JTAG*/
 499                                 /*<&clk_gates4 14>,*/
 500
 501                                 /*aclk_bus*/
 502                                 <&clk_gates10 5>,/*aclk_intmem0*/
 503                                 <&clk_gates10 6>,/*aclk_intmem1*/
 504                                 <&clk_gates10 7>,/*aclk_intmem2*/
 505                                 <&clk_gates10 12>,/*aclk_dma1*/
 506                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 507                                 <&clk_gates10 4>,/*aclk_intmem*/
 508                                 <&clk_gates11 6>,/*aclk_crypto*/
 509                                 <&clk_gates11 8>,/*aclk_ccp*/
 510
 511                                 /*hclk_bus*/
 512                                 <&clk_gates11 7>,/*hclk_crypto*/
 513                                 <&clk_gates10 9>,/*hclk_rom*/
 514
 515                                 /*pclk_bus*/
 516                                 <&clk_gates10 1>,/*pclk_timer*/
 517
 518                                 /*aclk_peri*/
 519                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 520                                 <&clk_gates6 3>,/*aclk_dmac2*/
 521                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 522                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 523
 524                                 /*hclk_peri*/
 525                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 526                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 527                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 528                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 529
 530                                 /*pclk_peri*/
 531                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 532
 533                                 /*pclk_pd_alive*/
 534                                 <&clk_gates14 11>,/*pclk_grf*/
 535                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 536
 537                                 /*pclk_pd_pmu*/
 538                                 <&clk_gates17 0>,/*pclk_pmu*/
 539                                 <&clk_gates17 1>,/*pclk_intmem1*/
 540                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 541                                 <&clk_gates17 3>,/*pclk_sgrf*/
 542
 543                                 /*hclk_vio*/
 544                                 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
 545                                 <&clk_gates15 10>,/*hclk_vio_niu*/
 546                                 <&clk_gates16 10>,/*hclk_vio2_h2p*/
 547                                 <&clk_gates16 11>,/*pclk_vio2_h2p*/
 548
 549                                 /*aclk_vio0*/
 550                                 <&clk_gates15 11>,/*aclk_vio0_niu*/
 551
 552                                 /*aclk_vio1*/
 553                                 <&clk_gates15 12>,/*aclk_vio1_niu*/
 554
 555                                 /*HDMI*/
 556                                 <&clk_gates5 12>,/*hdmi_hdcp_clk*/
 557
 558                                 /*UART*/
 559                                 <&clk_gates11 9>;/*pclk_uart2*/
 560         };
 561
 562         i2c0: i2c@ff650000 {
 563                 compatible = "rockchip,rk30-i2c";
 564                 reg = <0xff650000 0x1000>;
 565                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 pinctrl-names = "default", "gpio";
 569                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 570                 pinctrl-1 = <&i2c0_gpio>;
 571                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 572                 clocks = <&clk_gates10 2>;
 573                 rockchip,check-idle = <1>;
 574                 status = "disabled";
 575         };
 576
 577         i2c1: i2c@ff140000 {
 578                 compatible = "rockchip,rk30-i2c";
 579                 reg = <0xff140000 0x1000>;
 580                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 pinctrl-names = "default", "gpio";
 584                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 585                 pinctrl-1 = <&i2c1_gpio>;
 586                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 587                 clocks = <&clk_gates10 3>;
 588                 rockchip,check-idle = <1>;
 589                 status = "disabled";
 590         };
 591
 592         i2c2: i2c@ff660000 {
 593                 compatible = "rockchip,rk30-i2c";
 594                 reg = <0xff660000 0x1000>;
 595                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 pinctrl-names = "default", "gpio";
 599                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 600                 pinctrl-1 = <&i2c2_gpio>;
 601                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 602                 clocks = <&clk_gates6 13>;
 603                 rockchip,check-idle = <1>;
 604                 status = "disabled";
 605         };
 606
 607         i2c3: i2c@ff150000 {
 608                 compatible = "rockchip,rk30-i2c";
 609                 reg = <0xff150000 0x1000>;
 610                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 pinctrl-names = "default", "gpio";
 614                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 615                 pinctrl-1 = <&i2c3_gpio>;
 616                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 617                 clocks = <&clk_gates6 14>;
 618                 rockchip,check-idle = <1>;
 619                 status = "disabled";
 620         };
 621
 622         i2c4: i2c@ff160000 {
 623                 compatible = "rockchip,rk30-i2c";
 624                 reg = <0xff160000 0x1000>;
 625                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 pinctrl-names = "default", "gpio";
 629                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 630                 pinctrl-1 = <&i2c4_gpio>;
 631                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 632                 clocks = <&clk_gates6 15>;
 633                 rockchip,check-idle = <1>;
 634                 status = "disabled";
 635         };
 636
 637         i2c5: i2c@ff170000 {
 638                 compatible = "rockchip,rk30-i2c";
 639                 reg = <0xff170000 0x1000>;
 640                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 641                 #address-cells = <1>;
 642                 #size-cells = <0>;
 643                 pinctrl-names = "default", "gpio";
 644                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 645                 pinctrl-1 = <&i2c5_gpio>;
 646                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 647                 clocks = <&clk_gates7 0>;
 648                 rockchip,check-idle = <1>;
 649                 status = "disabled";
 650         };
 651
 652
 653         fb: fb{
 654                 compatible = "rockchip,rk-fb";
 655                 rockchip,disp-mode = <DUAL>;
 656         };
 657
 658         rk_screen: rk_screen{
 659                         compatible = "rockchip,screen";
 660         };
 661
 662         dsihost0: mipi@ff960000{
 663                 compatible = "rockchip,rk32-dsi";
 664                 rockchip,prop = <0>;
 665                 reg = <0xff960000 0x4000>;
 666                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 667                 status = "okay";
 668         };
 669
 670         dsihost1: mipi@ff964000{
 671                 compatible = "rockchip,rk32-dsi";
 672                 rockchip,prop = <1>;
 673                 reg = <0xff964000 0x4000>;
 674                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 675                 status = "disabled";
 676         };
 677
 678         lvds: lvds@ff96c000 {
 679                 compatible = "rockchip,rk32-lvds";
 680                 reg = <0xff96c000 0x4000>;
 681                 clocks = <&clk_gates16 7>;
 682                 clock-names = "pclk_lvds";
 683         };
 684
 685         edp: edp@ff970000 {
 686                 compatible = "rockchip,rk32-edp";
 687                 reg = <0xff970000 0x4000>;
 688                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 690                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 691         };
 692
 693         hdmi: hdmi@ff980000 {
 694                 compatible = "rockchip,rk3288-hdmi";
 695                 reg = <0xff980000 0x20000>;
 696                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 697                 pinctrl-names = "default", "gpio";
 698                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 699                 pinctrl-1 = <&i2c5_gpio>;
 700                 clocks = <&clk_gates16 9>;
 701                 clock-names = "pclk_hdmi";
 702                 status = "disabled";
 703         };
 704
 705         lcdc1: lcdc@ff940000 {
 706                 compatible = "rockchip,rk3288-lcdc";
 707                 rockchip,prop = <PRMRY>;
 708                 rochchip,pwr18 = <0>;
 709                 reg = <0xff940000 0x10000>;
 710                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 711                 pinctrl-names = "default", "gpio";
 712                 pinctrl-0 = <&lcdc0_lcdc>;
 713                 pinctrl-1 = <&lcdc0_gpio>;
 714                 status = "disabled";
 715                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>;
 716                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 717         };
 718
 719         lcdc0: lcdc@ff930000 {
 720                 compatible = "rockchip,rk3288-lcdc";
 721                 rockchip,prop = <EXTEND>;
 722                 rockchip,pwr18 = <0>;
 723                 reg = <0xff930000 0x10000>;
 724                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 725                 //pinctrl-names = "default", "gpio";
 726                 //pinctrl-0 = <&lcdc0_lcdc>;
 727                 //pinctrl-1 = <&lcdc0_gpio>;
 728                 status = "disabled";
 729                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>;
 730                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 731         };
 732
 733         adc: adc@ff100000 {
 734                 compatible = "rockchip,saradc";
 735                 reg = <0xff100000 0x100>;
 736                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 737                 #io-channel-cells = <1>;
 738                 io-channel-ranges;
 739                 rockchip,adc-vref = <1800>;
 740                 clock-frequency = <1000000>;
 741                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 742                 clock-names = "saradc", "pclk_saradc";
 743                 status = "disabled";
 744         };
 745
 746         rga@ff920000 {
 747                 compatible = "rockchip,rga";
 748                 reg = <0xff920000 0x1000>;
 749                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 750                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 751                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 752         };
 753
 754         i2s: rockchip-i2s@0xff890000 {
 755                 compatible = "rockchip-i2s";
 756                 reg = <0xff890000 0x10000>;
 757                 i2s-id = <0>;
 758                 clocks = <&clk_i2s>, <&clk_i2s_out>;
 759                 clock-names = "i2s_clk","i2s_mclk";
 760                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 761                 dmas = <&pdma0 0>,
 762                         <&pdma0 1>;
 763                 //#dma-cells = <2>;
 764                 dma-names = "tx", "rx";
 765                 pinctrl-names = "default", "sleep";
 766                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 767                 pinctrl-1 = <&i2s_gpio>;
 768         };
 769
 770         spdif: rockchip-spdif@0xff8b0000 {
 771                 compatible = "rockchip-spdif";
 772                 reg = <0xff8b0000 0x10000>;     //8channel
 773                 //reg = <ff880000 0x10000>;//2channel
 774                 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
 775                 clock-names = "spdif_mclk","spdif_8ch_mclk";
 776                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 777                 dmas = <&pdma0 3>;
 778                 //dmas = <&pdma0 2>; //2channel
 779                 //#dma-cells = <1>;
 780                 dma-names = "tx";
 781                 pinctrl-names = "default";
 782                 pinctrl-0 = <&spdif_tx>;
 783         };
 784
 785         pwm0: pwm@ff680000 {
 786                 compatible = "rockchip,rk-pwm";
 787                 reg = <0xff680000 0x10>;
 788                 #pwm-cells = <2>;
 789                 pinctrl-names = "default";
 790                 pinctrl-0 = <&pwm0_pin>;
 791                 clocks = <&clk_gates11 11>;
 792                 clock-names = "pclk_pwm";
 793                 status = "okay";
 794         };
 795
 796         pwm1: pwm@ff680010 {
 797                 compatible = "rockchip,rk-pwm";
 798                 reg = <0xff680010 0x10>;
 799                 #pwm-cells = <2>;
 800                 pinctrl-names = "default";
 801                 pinctrl-0 = <&pwm1_pin>;
 802                 clocks = <&clk_gates11 11>;
 803                 clock-names = "pclk_pwm";
 804                 status = "disabled";
 805         };
 806
 807         pwm2: pwm@ff680020 {
 808                 compatible = "rockchip,rk-pwm";
 809                 reg = <0xff680020 0x10>;
 810                 #pwm-cells = <2>;
 811                 pinctrl-names = "default";
 812                 pinctrl-0 = <&pwm2_pin>;
 813                 clocks = <&clk_gates11 11>;
 814                 clock-names = "pclk_pwm";
 815                 status = "disabled";
 816         };
 817
 818         pwm3: pwm@ff680030 {
 819                 compatible = "rockchip,rk-pwm";
 820                 reg = <0xff680030 0x10>;
 821                 #pwm-cells = <2>;
 822                 pinctrl-names = "default";
 823                 pinctrl-0 = <&pwm3_pin>;
 824                 clocks = <&clk_gates11 11>;
 825                 clock-names = "pclk_pwm";
 826                 status = "disabled";
 827         };
 828         dvfs {
 829                 vd_arm:
 830                 vd_arm {
 831                         regulator_name="vdd_arm";
 832                         suspend_volt=<1000>; //mV
 833                         pd_core {
 834                                 clk_core_dvfs_table:
 835                                 clk_core {
 836                                         operating-points = <
 837                                                 /* KHz    uV */
 838                                                 312000 1100000
 839                                                 504000 1100000
 840                                                 816000 1100000
 841                                                 1008000 1100000
 842                                                 >;
 843                                         temp-channel=<1>;
 844                                         temp-limit = <
 845                                                 /*temp    freq*/
 846                                                 50      1608000
 847                                                 70      1416000
 848                                                 80      1200000
 849                                                 100     1008000
 850                                                 >;
 851                                         status = "okay";
 852                                 };
 853                         };
 854                 };
 855
 856                 vd_logic:
 857                 vd_logic {
 858                         regulator_name="vdd_logic";
 859                         suspend_volt=<1000>; //mV
 860                         pd_ddr {
 861                                 clk_ddr_dvfs_table:
 862                                 clk_ddr {
 863                                         operating-points = <
 864                                                 /* KHz    uV */
 865                                                 200000 1200000
 866                                                 300000 1200000
 867                                                 400000 1200000
 868                                                 >;
 869                                         status = "disable";
 870                                 };
 871                         };
 872
 873                         pd_vpu {
 874                                 clk_ddr_vepu_table:
 875                                 clk_vepu {
 876                                         operating-points = <
 877                                                 /* KHz    uV */
 878                                                 200000 1300000
 879                                                 300000 1300000
 880                                                 400000 1300000
 881                                                 >;
 882                                         status = "okay";
 883                                 };
 884                         };
 885                 };
 886
 887                 vd_gpu:
 888                 vd_gpu {
 889                         regulator_name="vdd_gpu";
 890                         suspend_volt=<1000>; //mV
 891                         pd_gpu {
 892                                 clk_gpu_dvfs_table:
 893                                 clk_gpu {
 894                                         operating-points = <
 895                                                 /* KHz    uV */
 896                                                 200000 1200000
 897                                                 300000 1200000
 898                                                 400000 1200000
 899                                                 >;
 900                                         temp-channel=<2>;
 901                                         temp-limit = <
 902                                                 /*temp    freq*/
 903                                                 50      600000
 904                                                 70      500000
 905                                                 80      400000
 906                                                 100     300000
 907                                                 >;
 908                                         status = "okay";
 909                                 };
 910                         };
 911                 };
 912         };
 913
 914         ion {
 915                 compatible = "rockchip,ion";
 916                 #address-cells = <1>;
 917                 #size-cells = <0>;
 918                 rockchip,ion-heap@1 { /* CMA HEAP */
 919                         compatible = "rockchip,ion-reserve";
 920                         reg = <1>;
 921                         memory-reservation = <0x00000000 0x18000000>; /* 384MB */
 922                 };
 923                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 924                         reg = <3>;
 925                 };
 926         };
 927
 928
 929         vpu: vpu_service@ff9a0000 {
 930                 compatible = "vpu_service";
 931                 reg = <0xff9a0000 0x800>;
 932                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 933                 interrupt-names = "irq_enc", "irq_dec";
 934                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 935                 clock-names = "aclk_vcodec", "hclk_vcodec";
 936                 name = "vpu_service";
 937                 //status = "disabled";
 938         };
 939
 940         hevc: hevc_service@ff9c0000 {
 941                 compatible = "rockchip,hevc_service";
 942                 reg = <0xff9c0000 0x800>;
 943                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 944                 interrupt-names = "irq_dec";
 945                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 946                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 947                 name = "hevc_service";
 948                 //status = "disabled";
 949         };
 950
 951         iep: iep@ff900000 {
 952                 compatible = "rockchip,iep";
 953                 reg = <0xff900000 0x800>;
 954                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 955                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 956                 clock_names = "aclk_iep", "hclk_iep";
 957                 status = "okay";
 958         };
 959
 960         dwc_control_usb: dwc-control-usb@ff770284 {
 961                 compatible = "rockchip,rk3288-dwc-control-usb";
 962                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 963                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 964                       <0xff770320 0x14>, <0xff770334 0x14>,
 965                       <0xff770348 0x10>, <0xff770358 0x08>,
 966                       <0xff770360 0x08>;
 967                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 968                     "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 969                     "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 970                     "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 971                     "GRF_UOC4_BASE";
 972                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 973                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 974                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 975                 interrupt-names = "otg_id", "otg_bvalid",
 976                           "otg_linestate", "host0_linestate",
 977                           "host1_linestate";
 978                 gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,/*HOST_VBUS_DRV*/
 979                         <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;/*OTG_VBUS_DRV*/
 980                 clocks = <&clk_gates7 9>;
 981                 clock-names = "hclk_usb_peri";
 982                 rockchip,remote_wakeup;
 983                 rockchip,usb_irq_wakeup;
 984
 985                 usb_bc{
 986                         compatible = "synopsys,phy";
 987                                         /* offset bit mask */
 988                         rk_usb,bvalid     = <0x288 14 1>;
 989                         rk_usb,dcdenb     = <0x328 14 1>;
 990                         rk_usb,vdatsrcenb = <0x328  7 1>;
 991                         rk_usb,vdatdetenb = <0x328  6 1>;
 992                         rk_usb,chrgsel    = <0x328  5 1>;
 993                         rk_usb,chgdet     = <0x2cc 23 1>;
 994                         rk_usb,fsvminus   = <0x2cc 25 1>;
 995                         rk_usb,fsvplus    = <0x2cc 24 1>;
 996                 };
 997         };
 998
 999         usb0: usb@ff580000 {
1000                 compatible = "rockchip,rk3288_usb20_otg";
1001                 reg = <0xff580000 0x40000>;
1002                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1003                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1004                 clock-names = "clk_usbphy0", "hclk_usb0";
1005                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1006                 rockchip,usb-mode = <0>;
1007         };
1008
1009         usb1: usb@ff540000 {
1010                 compatible = "rockchip,rk3288_usb20_host";
1011                 reg = <0xff540000 0x40000>;
1012                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1013                 clocks = <&clk_gates13 6>, <&clk_gates7 7>;
1014                 clock-names = "clk_usbphy1", "hclk_usb1";
1015         };
1016
1017         usb2: usb@ff500000 {
1018                 compatible = "rockchip,rk3288_rk_ehci_host";
1019                 reg = <0xff500000 0x20000>;
1020                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1021                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1022                 clock-names = "clk_usbphy2", "hclk_usb2";
1023         };
1024
1025         usb3: usb@ff520000 {
1026                 compatible = "rockchip,rk3288_rk_ohci_host";
1027                 reg = <0xff520000 0x20000>;
1028                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1029                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1030                 clock-names = "clk_usbphy3", "hclk_usb3";
1031         };
1032
1033         hsic: hsic@ff5c0000 {
1034                 compatible = "rockchip,rk3288_rk_hsic_host";
1035                 reg = <0xff5c0000 0x40000>;
1036                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1037                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1038                          <&hsicphy_12m>, <&usbphy_480m>,
1039                          <&otgphy1_480m>, <&otgphy2_480m>;
1040                 clock-names = "hsicphy_480m", "hclk_hsic",
1041                               "hsicphy_12m", "usbphy_480m",
1042                               "hsic_usbphy1", "hsic_usbphy2";
1043         };
1044
1045         gmac: eth@ff290000 {
1046                 compatible = "rockchip,gmac";
1047                 reg = <0xff290000 0x10000>;
1048                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1049                 interrupt-names = "macirq";
1050                 //phy-mode = "rmii";
1051                 phy-mode = "rgmii";
1052                 pinctrl-names = "default";
1053                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1054         };
1055     gpu{
1056         compatible = "arm,malit764",
1057                      "arm,malit76x",
1058                      "arm,malit7xx",
1059                      "arm,mali-midgard";
1060         reg = <0xffa30000 0x10000>;
1061         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1062                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1063                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1064         interrupt-names = "JOB",
1065                           "MMU",
1066                           "GPU";
1067     };
1068
1069     iep_mmu{
1070         dbgname = "iep";
1071         compatible = "iommu,iep_mmu";
1072         reg = <0xff900800 0x100>;
1073         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1074         interrupt-names = "iep_mmu";
1075     };
1076
1077     vip_mmu{
1078         dbgname = "vip";
1079         compatible = "iommu,vip_mmu";
1080         reg = <0xff950800 0x100>;
1081         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1082         interrupt-names = "vip_mmu";
1083     };
1084
1085     isp_mmu0{
1086         dbgname = "isp_mmu0";
1087         compatible = "iommu,isp_mmu0";
1088         reg = <0xff914000 0x100>;
1089         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1090         interrupt-names = "isp_mmu0";
1091     };
1092
1093     isp_mmu1{
1094         dbgname = "isp_mmu1";
1095         compatible = "iommu,isp_mmu1";
1096         reg = <0xff915000 0x100>;
1097         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1098         interrupt-names = "isp_mmu1";
1099     };
1100
1101     vopb_mmu{
1102         dbgname = "vopb";
1103         compatible = "iommu,vopb_mmu";
1104         reg = <0xff930300 0x100>;
1105         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1106         interrupt-names = "vopb_mmu";
1107     };
1108
1109     vopl_mmu{
1110         dbgname = "vopl";
1111         compatible = "iommu,vopl_mmu";
1112         reg = <0xff940300 0x100>;
1113         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1114         interrupt-names = "vopl_mmu";
1115     };
1116
1117     hevc_mmu{
1118         dbgname = "hevc";
1119         compatible = "iommu,hevc_mmu";
1120         reg = <0xff9c0800 0x100>;
1121         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1122         interrupt-names = "hevc_mmu";
1123     };
1124
1125                 vpu_mmu{
1126         dbgname = "vpu";
1127         compatible = "iommu,vpu_mmu";
1128         reg = <0xff9a0800 0x100>;
1129         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1130         interrupt-names = "vpu_mmu";
1131     };
1132
1133     rockchip_suspend {
1134                   rockchip,ctrbits = <
1135                                             (0
1136                                             |RKPM_CTR_PWR_DMNS
1137                                             |RKPM_CTR_GTCLKS
1138                                             |RKPM_CTR_PLLS
1139                                             //|RKPM_CTR_SYSCLK_DIV
1140                                             //|RKPM_CTR_IDLEAUTO_MD
1141                                             //|RKPM_CTR_ARMDP_LPMD
1142                                             |RKPM_CTR_ARMOFF_LPMD
1143                                             )
1144                                         >;
1145                   rockchip,pmic-gpios=<
1146                                                     RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1147                                                     RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1148                                                     >;
1149             };
1150
1151            isp:isp@ff910000{
1152                 compatible = "rockchip,isp";
1153                 reg = <0xff910000 0x10000>;
1154                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1155                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&dummy>, <&clk_cif_out>;
1156                         clock_names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout";
1157                         pinctrl-names = "default", "isp_dvp8bit","isp_dvp10bit","isp_dvp12bit";
1158                         pinctrl-0 = <&isp_mipi>;
1159                         pinctrl-1 = <&isp_mipi &isp_dvp_sync_d2d9>;
1160                         pinctrl-2 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1>;
1161                         pinctrl-3 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1 &isp_dvpd10d11>;
1162
1163                         status = "okay";
1164         };
1165
1166         tsadc: tsadc@ff280000{
1167                         compatible = "rockchip,tsadc";
1168                         reg = <0xff280000 0x100>;
1169                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1170                         #io-channel-cells = <1>;
1171                         io-channel-ranges;
1172                         clock-frequency = <50000>;
1173                         clocks = <&clk_tsadc>, <&clk_gates7 2>;
1174                         clock-names = "tsadc", "pclk_tsadc";
1175                         status = "okay";
1176         };
1177
1178         lcdc_vdd_domain: lcdc-vdd-domain{
1179                         compatible = "rockchip,io_vol_domain";
1180                         pinctrl-names = "default", "1.8V", "3.3V";
1181                         pinctrl-0 = <&lcdc_vcc>;
1182                         pinctrl-1 = <&lcdc_vcc_18>;
1183                         pinctrl-2 = <&lcdc_vcc_33>;
1184         };
1185         dpio_vdd_domain: dpio-vdd-domain{
1186                         compatible = "rockchip,io_vol_domain";
1187                         pinctrl-names = "default", "1.8V", "3.3V";
1188                         pinctrl-0 = <&dvp_vcc>;
1189                         pinctrl-1 = <&dvp_vcc_18>;
1190                         pinctrl-2 = <&dvp_vcc_33>;
1191         };
1192         flash0_vdd_domain: flash0-vdd-domain{
1193                         compatible = "rockchip,io_vol_domain";
1194                         pinctrl-names = "default", "1.8V", "3.3V";
1195                         pinctrl-0 = <&flash0_vcc>;
1196                         pinctrl-1 = <&flash0_vcc_18>;
1197                         pinctrl-2 = <&flash0_vcc_33>;
1198         };
1199         flash1_vdd_domain: flash1-vdd-domain{
1200                         compatible = "rockchip,io_vol_domain";
1201                         pinctrl-names = "default", "1.8V", "3.3V";
1202                         pinctrl-0 = <&flash1_vcc>;
1203                         pinctrl-1 = <&flash1_vcc_18>;
1204                         pinctrl-2 = <&flash1_vcc_33>;
1205         };
1206         apio3_vdd_domain: apio3-vdd-domain{
1207                         compatible = "rockchip,io_vol_domain";
1208                         pinctrl-names = "default", "1.8V", "3.3V";
1209                         pinctrl-0 = <&wifi_vcc>;
1210                         pinctrl-1 = <&wifi_vcc_18>;
1211                         pinctrl-2 = <&wifi_vcc_33>;
1212         };
1213         apio5_vdd_domain: apio5-vdd-domain{
1214                         compatible = "rockchip,io_vol_domain";
1215                         pinctrl-names = "default", "1.8V", "3.3V";
1216                         pinctrl-0 = <&bb_vcc>;
1217                         pinctrl-1 = <&bb_vcc_18>;
1218                         pinctrl-2 = <&bb_vcc_33>;
1219         };
1220         apio4_vdd_domain: apio4-vdd-domain{
1221                         compatible = "rockchip,io_vol_domain";
1222                         pinctrl-names = "default", "1.8V", "3.3V";
1223                         pinctrl-0 = <&audio_vcc>;
1224                         pinctrl-1 = <&audio_vcc_18>;
1225                         pinctrl-2 = <&audio_vcc_33>;
1226         };
1227         apio1_vdd_domain: apio0-vdd-domain{
1228                         compatible = "rockchip,io_vol_domain";
1229                         pinctrl-names = "default", "1.8V", "3.3V";
1230                         pinctrl-0 = <&gpio30_vcc>;
1231                         pinctrl-1 = <&gpio30_vcc_18>;
1232                         pinctrl-2 = <&gpio30_vcc_33>;
1233         };
1234         apio2_vdd_domain: apio2-vdd-domain{
1235                         compatible = "rockchip,io_vol_domain";
1236                         pinctrl-names = "default", "1.8V", "3.3V";
1237                         pinctrl-0 = <&gpio1830_vcc>;
1238                         pinctrl-1 = <&gpio1830_vcc_18>;
1239                         pinctrl-2 = <&gpio1830_vcc_33>;
1240         };
1241         sdmmc0_vdd_domain: sdmmc0-vdd-domain{
1242                         compatible = "rockchip,io_vol_domain";
1243                         pinctrl-names = "default", "1.8V", "3.3V";
1244                         pinctrl-0 = <&sdcard_vcc>;
1245                         pinctrl-1 = <&sdcard_vcc_18>;
1246                         pinctrl-2 = <&sdcard_vcc_33>;
1247         };
1248
1249 };