arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 mshc0 = &emmc;
  63                 mshc1 = &sdmmc;
  64                 mshc2 = &sdio0;
  65                 mshc3 = &sdio1;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         arm-pmu {
  77                 compatible = "arm,cortex-a12-pmu";
  78                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88                 enable-method = "rockchip,rk3066-smp";
  89                 rockchip,pmu = <&pmu>;
  90
  91                 cpu0: cpu@500 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x500>;
  95                         resets = <&cru SRST_CORE0>;
  96                         operating-points = <
  97                                 /* KHz    uV */
  98                                 1608000 1350000
  99                                 1512000 1300000
 100                                 1416000 1200000
 101                                 1200000 1100000
 102                                 1008000 1050000
 103                                  816000 1000000
 104                                  696000  950000
 105                                  600000  900000
 106                                  408000  900000
 107                                  312000  900000
 108                                  216000  900000
 109                                  126000  900000
 110                         >;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clock-latency = <40000>;
 113                         clocks = <&cru ARMCLK>;
 114                 };
 115                 cpu1: cpu@501 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a12";
 118                         reg = <0x501>;
 119                         resets = <&cru SRST_CORE1>;
 120                 };
 121                 cpu2: cpu@502 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x502>;
 125                         resets = <&cru SRST_CORE2>;
 126                 };
 127                 cpu3: cpu@503 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a12";
 130                         reg = <0x503>;
 131                         resets = <&cru SRST_CORE3>;
 132                 };
 133         };
 134
 135         amba {
 136                 compatible = "arm,amba-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 dmac_peri: dma-controller@ff250000 {
 142                         compatible = "arm,pl330", "arm,primecell";
 143                         reg = <0xff250000 0x4000>;
 144                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 146                         #dma-cells = <1>;
 147                         arm,pl330-broken-no-flushp;
 148                         clocks = <&cru ACLK_DMAC2>;
 149                         clock-names = "apb_pclk";
 150                 };
 151
 152                 dmac_bus_ns: dma-controller@ff600000 {
 153                         compatible = "arm,pl330", "arm,primecell";
 154                         reg = <0xff600000 0x4000>;
 155                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 156                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 157                         #dma-cells = <1>;
 158                         arm,pl330-broken-no-flushp;
 159                         clocks = <&cru ACLK_DMAC1>;
 160                         clock-names = "apb_pclk";
 161                         status = "disabled";
 162                 };
 163
 164                 dmac_bus_s: dma-controller@ffb20000 {
 165                         compatible = "arm,pl330", "arm,primecell";
 166                         reg = <0xffb20000 0x4000>;
 167                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 169                         #dma-cells = <1>;
 170                         arm,pl330-broken-no-flushp;
 171                         clocks = <&cru ACLK_DMAC1>;
 172                         clock-names = "apb_pclk";
 173                 };
 174         };
 175
 176         reserved-memory {
 177                 #address-cells = <1>;
 178                 #size-cells = <1>;
 179                 ranges;
 180
 181                 /*
 182                  * The rk3288 cannot use the memory area above 0xfe000000
 183                  * for dma operations for some reason. While there is
 184                  * probably a better solution available somewhere, we
 185                  * haven't found it yet and while devices with 2GB of ram
 186                  * are not affected, this issue prevents 4GB from booting.
 187                  * So to make these devices at least bootable, block
 188                  * this area for the time being until the real solution
 189                  * is found.
 190                  */
 191                 dma-unusable@fe000000 {
 192                         reg = <0xfe000000 0x1000000>;
 193                 };
 194         };
 195
 196         xin24m: oscillator {
 197                 compatible = "fixed-clock";
 198                 clock-frequency = <24000000>;
 199                 clock-output-names = "xin24m";
 200                 #clock-cells = <0>;
 201         };
 202
 203         timer {
 204                 compatible = "arm,armv7-timer";
 205                 arm,cpu-registers-not-fw-configured;
 206                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 207                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 208                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 209                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 210                 clock-frequency = <24000000>;
 211         };
 212
 213         timer: timer@ff810000 {
 214                 compatible = "rockchip,rk3288-timer";
 215                 reg = <0xff810000 0x20>;
 216                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 218                 clock-names = "timer", "pclk";
 219         };
 220
 221         display-subsystem {
 222                 compatible = "rockchip,display-subsystem";
 223                 ports = <&vopl_out>, <&vopb_out>;
 224         };
 225
 226         sdmmc: dwmmc@ff0c0000 {
 227                 compatible = "rockchip,rk3288-dw-mshc";
 228                 clock-freq-min-max = <400000 150000000>;
 229                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 230                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 231                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 232                 fifo-depth = <0x100>;
 233                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 234                 reg = <0xff0c0000 0x4000>;
 235                 status = "disabled";
 236         };
 237
 238         sdio0: dwmmc@ff0d0000 {
 239                 compatible = "rockchip,rk3288-dw-mshc";
 240                 clock-freq-min-max = <400000 150000000>;
 241                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 242                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 243                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 244                 fifo-depth = <0x100>;
 245                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 246                 reg = <0xff0d0000 0x4000>;
 247                 status = "disabled";
 248         };
 249
 250         sdio1: dwmmc@ff0e0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 clock-freq-min-max = <400000 150000000>;
 253                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 254                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0xff0e0000 0x4000>;
 259                 status = "disabled";
 260         };
 261
 262         emmc: dwmmc@ff0f0000 {
 263                 compatible = "rockchip,rk3288-dw-mshc";
 264                 clock-freq-min-max = <400000 150000000>;
 265                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 266                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 267                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 268                 fifo-depth = <0x100>;
 269                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 270                 reg = <0xff0f0000 0x4000>;
 271                 status = "disabled";
 272         };
 273
 274         saradc: saradc@ff100000 {
 275                 compatible = "rockchip,saradc";
 276                 reg = <0xff100000 0x100>;
 277                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 278                 #io-channel-cells = <1>;
 279                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 280                 clock-names = "saradc", "apb_pclk";
 281                 status = "disabled";
 282         };
 283
 284         spi0: spi@ff110000 {
 285                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 286                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 287                 clock-names = "spiclk", "apb_pclk";
 288                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 289                 dma-names = "tx", "rx";
 290                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 293                 reg = <0xff110000 0x1000>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 status = "disabled";
 297         };
 298
 299         spi1: spi@ff120000 {
 300                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 301                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 302                 clock-names = "spiclk", "apb_pclk";
 303                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 304                 dma-names = "tx", "rx";
 305                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 308                 reg = <0xff120000 0x1000>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 status = "disabled";
 312         };
 313
 314         spi2: spi@ff130000 {
 315                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 316                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 317                 clock-names = "spiclk", "apb_pclk";
 318                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 319                 dma-names = "tx", "rx";
 320                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 321                 pinctrl-names = "default";
 322                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 323                 reg = <0xff130000 0x1000>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 status = "disabled";
 327         };
 328
 329         i2c1: i2c@ff140000 {
 330                 compatible = "rockchip,rk3288-i2c";
 331                 reg = <0xff140000 0x1000>;
 332                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 clock-names = "i2c";
 336                 clocks = <&cru PCLK_I2C1>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&i2c1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         i2c3: i2c@ff150000 {
 343                 compatible = "rockchip,rk3288-i2c";
 344                 reg = <0xff150000 0x1000>;
 345                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clock-names = "i2c";
 349                 clocks = <&cru PCLK_I2C3>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c3_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c4: i2c@ff160000 {
 356                 compatible = "rockchip,rk3288-i2c";
 357                 reg = <0xff160000 0x1000>;
 358                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clock-names = "i2c";
 362                 clocks = <&cru PCLK_I2C4>;
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c4_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         i2c5: i2c@ff170000 {
 369                 compatible = "rockchip,rk3288-i2c";
 370                 reg = <0xff170000 0x1000>;
 371                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clock-names = "i2c";
 375                 clocks = <&cru PCLK_I2C5>;
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&i2c5_xfer>;
 378                 status = "disabled";
 379         };
 380
 381         uart0: serial@ff180000 {
 382                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 383                 reg = <0xff180000 0x100>;
 384                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 385                 reg-shift = <2>;
 386                 reg-io-width = <4>;
 387                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 388                 clock-names = "baudclk", "apb_pclk";
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&uart0_xfer>;
 391                 status = "disabled";
 392         };
 393
 394         uart1: serial@ff190000 {
 395                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 396                 reg = <0xff190000 0x100>;
 397                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 398                 reg-shift = <2>;
 399                 reg-io-width = <4>;
 400                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 401                 clock-names = "baudclk", "apb_pclk";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&uart1_xfer>;
 404                 status = "disabled";
 405         };
 406
 407         uart2: serial@ff690000 {
 408                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 409                 reg = <0xff690000 0x100>;
 410                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 411                 reg-shift = <2>;
 412                 reg-io-width = <4>;
 413                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 414                 clock-names = "baudclk", "apb_pclk";
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&uart2_xfer>;
 417                 status = "disabled";
 418         };
 419
 420         uart3: serial@ff1b0000 {
 421                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 422                 reg = <0xff1b0000 0x100>;
 423                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 424                 reg-shift = <2>;
 425                 reg-io-width = <4>;
 426                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 427                 clock-names = "baudclk", "apb_pclk";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&uart3_xfer>;
 430                 status = "disabled";
 431         };
 432
 433         uart4: serial@ff1c0000 {
 434                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 435                 reg = <0xff1c0000 0x100>;
 436                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 437                 reg-shift = <2>;
 438                 reg-io-width = <4>;
 439                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 440                 clock-names = "baudclk", "apb_pclk";
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&uart4_xfer>;
 443                 status = "disabled";
 444         };
 445
 446         thermal-zones {
 447                 #include "rk3288-thermal.dtsi"
 448         };
 449
 450         tsadc: tsadc@ff280000 {
 451                 compatible = "rockchip,rk3288-tsadc";
 452                 reg = <0xff280000 0x100>;
 453                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 455                 clock-names = "tsadc", "apb_pclk";
 456                 resets = <&cru SRST_TSADC>;
 457                 reset-names = "tsadc-apb";
 458                 pinctrl-names = "init", "default", "sleep";
 459                 pinctrl-0 = <&otp_gpio>;
 460                 pinctrl-1 = <&otp_out>;
 461                 pinctrl-2 = <&otp_gpio>;
 462                 #thermal-sensor-cells = <1>;
 463                 rockchip,hw-tshut-temp = <95000>;
 464                 status = "disabled";
 465         };
 466
 467         gmac: ethernet@ff290000 {
 468                 compatible = "rockchip,rk3288-gmac";
 469                 reg = <0xff290000 0x10000>;
 470                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 471                 interrupt-names = "macirq";
 472                 rockchip,grf = <&grf>;
 473                 clocks = <&cru SCLK_MAC>,
 474                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 475                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 476                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 477                 clock-names = "stmmaceth",
 478                         "mac_clk_rx", "mac_clk_tx",
 479                         "clk_mac_ref", "clk_mac_refout",
 480                         "aclk_mac", "pclk_mac";
 481                 resets = <&cru SRST_MAC>;
 482                 reset-names = "stmmaceth";
 483                 status = "disabled";
 484         };
 485
 486         usb_host0_ehci: usb@ff500000 {
 487                 compatible = "generic-ehci";
 488                 reg = <0xff500000 0x100>;
 489                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&cru HCLK_USBHOST0>;
 491                 clock-names = "usbhost";
 492                 phys = <&usbphy1>;
 493                 phy-names = "usb";
 494                 status = "disabled";
 495         };
 496
 497         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 498
 499         usb_host1: usb@ff540000 {
 500                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 501                                 "snps,dwc2";
 502                 reg = <0xff540000 0x40000>;
 503                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&cru HCLK_USBHOST1>;
 505                 clock-names = "otg";
 506                 dr_mode = "host";
 507                 phys = <&usbphy2>;
 508                 phy-names = "usb2-phy";
 509                 status = "disabled";
 510         };
 511
 512         usb_otg: usb@ff580000 {
 513                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 514                                 "snps,dwc2";
 515                 reg = <0xff580000 0x40000>;
 516                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&cru HCLK_OTG0>;
 518                 clock-names = "otg";
 519                 dr_mode = "otg";
 520                 g-np-tx-fifo-size = <16>;
 521                 g-rx-fifo-size = <275>;
 522                 g-tx-fifo-size = <256 128 128 64 64 32>;
 523                 g-use-dma;
 524                 phys = <&usbphy0>;
 525                 phy-names = "usb2-phy";
 526                 status = "disabled";
 527         };
 528
 529         usb_hsic: usb@ff5c0000 {
 530                 compatible = "generic-ehci";
 531                 reg = <0xff5c0000 0x100>;
 532                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&cru HCLK_HSIC>;
 534                 clock-names = "usbhost";
 535                 status = "disabled";
 536         };
 537
 538         i2c0: i2c@ff650000 {
 539                 compatible = "rockchip,rk3288-i2c";
 540                 reg = <0xff650000 0x1000>;
 541                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 clock-names = "i2c";
 545                 clocks = <&cru PCLK_I2C0>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c0_xfer>;
 548                 status = "disabled";
 549         };
 550
 551         i2c2: i2c@ff660000 {
 552                 compatible = "rockchip,rk3288-i2c";
 553                 reg = <0xff660000 0x1000>;
 554                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 clock-names = "i2c";
 558                 clocks = <&cru PCLK_I2C2>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c2_xfer>;
 561                 status = "disabled";
 562         };
 563
 564         pwm0: pwm@ff680000 {
 565                 compatible = "rockchip,rk3288-pwm";
 566                 reg = <0xff680000 0x10>;
 567                 #pwm-cells = <3>;
 568                 pinctrl-names = "default";
 569                 pinctrl-0 = <&pwm0_pin>;
 570                 clocks = <&cru PCLK_PWM>;
 571                 clock-names = "pwm";
 572                 status = "disabled";
 573         };
 574
 575         pwm1: pwm@ff680010 {
 576                 compatible = "rockchip,rk3288-pwm";
 577                 reg = <0xff680010 0x10>;
 578                 #pwm-cells = <3>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&pwm1_pin>;
 581                 clocks = <&cru PCLK_PWM>;
 582                 clock-names = "pwm";
 583                 status = "disabled";
 584         };
 585
 586         pwm2: pwm@ff680020 {
 587                 compatible = "rockchip,rk3288-pwm";
 588                 reg = <0xff680020 0x10>;
 589                 #pwm-cells = <3>;
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&pwm2_pin>;
 592                 clocks = <&cru PCLK_PWM>;
 593                 clock-names = "pwm";
 594                 status = "disabled";
 595         };
 596
 597         pwm3: pwm@ff680030 {
 598                 compatible = "rockchip,rk3288-pwm";
 599                 reg = <0xff680030 0x10>;
 600                 #pwm-cells = <2>;
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&pwm3_pin>;
 603                 clocks = <&cru PCLK_PWM>;
 604                 clock-names = "pwm";
 605                 status = "disabled";
 606         };
 607
 608         bus_intmem@ff700000 {
 609                 compatible = "mmio-sram";
 610                 reg = <0xff700000 0x18000>;
 611                 #address-cells = <1>;
 612                 #size-cells = <1>;
 613                 ranges = <0 0xff700000 0x18000>;
 614                 smp-sram@0 {
 615                         compatible = "rockchip,rk3066-smp-sram";
 616                         reg = <0x00 0x10>;
 617                 };
 618         };
 619
 620         sram@ff720000 {
 621                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 622                 reg = <0xff720000 0x1000>;
 623         };
 624
 625         pmu: power-management@ff730000 {
 626                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 627                 reg = <0xff730000 0x100>;
 628
 629                 power: power-controller {
 630                         compatible = "rockchip,rk3288-power-controller";
 631                         #power-domain-cells = <1>;
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634
 635                         /*
 636                          * Note: Although SCLK_* are the working clocks
 637                          * of device without including on the NOC, needed for
 638                          * synchronous reset.
 639                          *
 640                          * The clocks on the which NOC:
 641                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 642                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 643                          * ACLK_RGA is on ACLK_RGA_NIU.
 644                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 645                          *
 646                          * Which clock are device clocks:
 647                          *      clocks          devices
 648                          *      *_IEP           IEP:Image Enhancement Processor
 649                          *      *_ISP           ISP:Image Signal Processing
 650                          *      *_VIP           VIP:Video Input Processor
 651                          *      *_VOP*          VOP:Visual Output Processor
 652                          *      *_RGA           RGA
 653                          *      *_EDP*          EDP
 654                          *      *_LVDS_*        LVDS
 655                          *      *_HDMI          HDMI
 656                          *      *_MIPI_*        MIPI
 657                          */
 658                         pd_vio {
 659                                 reg = <RK3288_PD_VIO>;
 660                                 clocks = <&cru ACLK_IEP>,
 661                                          <&cru ACLK_ISP>,
 662                                          <&cru ACLK_RGA>,
 663                                          <&cru ACLK_VIP>,
 664                                          <&cru ACLK_VOP0>,
 665                                          <&cru ACLK_VOP1>,
 666                                          <&cru DCLK_VOP0>,
 667                                          <&cru DCLK_VOP1>,
 668                                          <&cru HCLK_IEP>,
 669                                          <&cru HCLK_ISP>,
 670                                          <&cru HCLK_RGA>,
 671                                          <&cru HCLK_VIP>,
 672                                          <&cru HCLK_VOP0>,
 673                                          <&cru HCLK_VOP1>,
 674                                          <&cru PCLK_EDP_CTRL>,
 675                                          <&cru PCLK_HDMI_CTRL>,
 676                                          <&cru PCLK_LVDS_PHY>,
 677                                          <&cru PCLK_MIPI_CSI>,
 678                                          <&cru PCLK_MIPI_DSI0>,
 679                                          <&cru PCLK_MIPI_DSI1>,
 680                                          <&cru SCLK_EDP_24M>,
 681                                          <&cru SCLK_EDP>,
 682                                          <&cru SCLK_ISP_JPE>,
 683                                          <&cru SCLK_ISP>,
 684                                          <&cru SCLK_RGA>;
 685                         };
 686
 687                         /*
 688                          * Note: The following 3 are HEVC(H.265) clocks,
 689                          * and on the ACLK_HEVC_NIU (NOC).
 690                          */
 691                         pd_hevc {
 692                                 reg = <RK3288_PD_HEVC>;
 693                                 clocks = <&cru ACLK_HEVC>,
 694                                          <&cru SCLK_HEVC_CABAC>,
 695                                          <&cru SCLK_HEVC_CORE>;
 696                         };
 697
 698                         /*
 699                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 700                          * (video endecoder & decoder) clocks that on the
 701                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 702                          */
 703                         pd_video {
 704                                 reg = <RK3288_PD_VIDEO>;
 705                                 clocks = <&cru ACLK_VCODEC>,
 706                                          <&cru HCLK_VCODEC>;
 707                         };
 708
 709                         /*
 710                          * Note: ACLK_GPU is the GPU clock,
 711                          * and on the ACLK_GPU_NIU (NOC).
 712                          */
 713                         pd_gpu {
 714                                 reg = <RK3288_PD_GPU>;
 715                                 clocks = <&cru ACLK_GPU>;
 716                         };
 717                 };
 718         };
 719
 720         sgrf: syscon@ff740000 {
 721                 compatible = "rockchip,rk3288-sgrf", "syscon";
 722                 reg = <0xff740000 0x1000>;
 723         };
 724
 725         cru: clock-controller@ff760000 {
 726                 compatible = "rockchip,rk3288-cru";
 727                 reg = <0xff760000 0x1000>;
 728                 rockchip,grf = <&grf>;
 729                 #clock-cells = <1>;
 730                 #reset-cells = <1>;
 731                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 732                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 733                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 734                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 735                                   <&cru PCLK_PERI>;
 736                 assigned-clock-rates = <594000000>, <400000000>,
 737                                        <500000000>, <300000000>,
 738                                        <150000000>, <75000000>,
 739                                        <300000000>, <150000000>,
 740                                        <75000000>;
 741         };
 742
 743         grf: syscon@ff770000 {
 744                 compatible = "rockchip,rk3288-grf", "syscon";
 745                 reg = <0xff770000 0x1000>;
 746         };
 747
 748         wdt: watchdog@ff800000 {
 749                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 750                 reg = <0xff800000 0x100>;
 751                 clocks = <&cru PCLK_WDT>;
 752                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 753                 status = "disabled";
 754         };
 755
 756         spdif: sound@ff88b0000 {
 757                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 758                 reg = <0xff8b0000 0x10000>;
 759                 #sound-dai-cells = <0>;
 760                 clock-names = "hclk", "mclk";
 761                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 762                 dmas = <&dmac_bus_s 3>;
 763                 dma-names = "tx";
 764                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 765                 pinctrl-names = "default";
 766                 pinctrl-0 = <&spdif_tx>;
 767                 rockchip,grf = <&grf>;
 768                 status = "disabled";
 769         };
 770
 771         i2s: i2s@ff890000 {
 772                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 773                 reg = <0xff890000 0x10000>;
 774                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 775                 #address-cells = <1>;
 776                 #size-cells = <0>;
 777                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 778                 dma-names = "tx", "rx";
 779                 clock-names = "i2s_hclk", "i2s_clk";
 780                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 781                 pinctrl-names = "default";
 782                 pinctrl-0 = <&i2s0_bus>;
 783                 status = "disabled";
 784         };
 785
 786         vopb: vop@ff930000 {
 787                 compatible = "rockchip,rk3288-vop";
 788                 reg = <0xff930000 0x19c>;
 789                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 790                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 791                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 792                 power-domains = <&power RK3288_PD_VIO>;
 793                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 794                 reset-names = "axi", "ahb", "dclk";
 795                 iommus = <&vopb_mmu>;
 796                 status = "disabled";
 797
 798                 vopb_out: port {
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801
 802                         vopb_out_hdmi: endpoint@0 {
 803                                 reg = <0>;
 804                                 remote-endpoint = <&hdmi_in_vopb>;
 805                         };
 806                         vopb_out_mipi: endpoint@2 {
 807                                 reg = <2>;
 808                                 remote-endpoint = <&mipi_in_vopb>;
 809                         };
 810                 };
 811         };
 812
 813         vopb_mmu: iommu@ff930300 {
 814                 compatible = "rockchip,iommu";
 815                 reg = <0xff930300 0x100>;
 816                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 817                 interrupt-names = "vopb_mmu";
 818                 power-domains = <&power RK3288_PD_VIO>;
 819                 #iommu-cells = <0>;
 820                 status = "disabled";
 821         };
 822
 823         vopl: vop@ff940000 {
 824                 compatible = "rockchip,rk3288-vop";
 825                 reg = <0xff940000 0x19c>;
 826                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 827                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 828                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 829                 power-domains = <&power RK3288_PD_VIO>;
 830                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 831                 reset-names = "axi", "ahb", "dclk";
 832                 iommus = <&vopl_mmu>;
 833                 status = "disabled";
 834
 835                 vopl_out: port {
 836                         #address-cells = <1>;
 837                         #size-cells = <0>;
 838
 839                         vopl_out_hdmi: endpoint@0 {
 840                                 reg = <0>;
 841                                 remote-endpoint = <&hdmi_in_vopl>;
 842                         };
 843                         vopl_out_mipi: endpoint@2 {
 844                                 reg = <2>;
 845                                 remote-endpoint = <&mipi_in_vopl>;
 846                         };
 847                 };
 848         };
 849
 850         vopl_mmu: iommu@ff940300 {
 851                 compatible = "rockchip,iommu";
 852                 reg = <0xff940300 0x100>;
 853                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 854                 interrupt-names = "vopl_mmu";
 855                 power-domains = <&power RK3288_PD_VIO>;
 856                 #iommu-cells = <0>;
 857                 status = "disabled";
 858         };
 859
 860         mipi_dsi: mipi@ff960000 {
 861                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 862                 reg = <0xff960000 0x4000>;
 863                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 864                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 865                 clock-names = "ref", "pclk";
 866                 rockchip,grf = <&grf>;
 867                 #address-cells = <1>;
 868                 #size-cells = <0>;
 869                 status = "disabled";
 870
 871                 ports {
 872                         #address-cells = <1>;
 873                         #size-cells = <0>;
 874                         reg = <1>;
 875
 876                         mipi_in: port {
 877                                 #address-cells = <1>;
 878                                 #size-cells = <0>;
 879                                 mipi_in_vopb: endpoint@0 {
 880                                         reg = <0>;
 881                                         remote-endpoint = <&vopb_out_mipi>;
 882                                 };
 883                                 mipi_in_vopl: endpoint@1 {
 884                                         reg = <1>;
 885                                         remote-endpoint = <&vopl_out_mipi>;
 886                                 };
 887                         };
 888                 };
 889         };
 890
 891         hdmi: hdmi@ff980000 {
 892                 compatible = "rockchip,rk3288-dw-hdmi";
 893                 reg = <0xff980000 0x20000>;
 894                 reg-io-width = <4>;
 895                 rockchip,grf = <&grf>;
 896                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 897                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 898                 clock-names = "iahb", "isfr";
 899                 power-domains = <&power RK3288_PD_VIO>;
 900                 status = "disabled";
 901
 902                 ports {
 903                         hdmi_in: port {
 904                                 #address-cells = <1>;
 905                                 #size-cells = <0>;
 906                                 hdmi_in_vopb: endpoint@0 {
 907                                         reg = <0>;
 908                                         remote-endpoint = <&vopb_out_hdmi>;
 909                                 };
 910                                 hdmi_in_vopl: endpoint@1 {
 911                                         reg = <1>;
 912                                         remote-endpoint = <&vopl_out_hdmi>;
 913                                 };
 914                         };
 915                 };
 916         };
 917
 918         gic: interrupt-controller@ffc01000 {
 919                 compatible = "arm,gic-400";
 920                 interrupt-controller;
 921                 #interrupt-cells = <3>;
 922                 #address-cells = <0>;
 923
 924                 reg = <0xffc01000 0x1000>,
 925                       <0xffc02000 0x1000>,
 926                       <0xffc04000 0x2000>,
 927                       <0xffc06000 0x2000>;
 928                 interrupts = <GIC_PPI 9 0xf04>;
 929         };
 930
 931         usbphy: phy {
 932                 compatible = "rockchip,rk3288-usb-phy";
 933                 rockchip,grf = <&grf>;
 934                 #address-cells = <1>;
 935                 #size-cells = <0>;
 936                 status = "disabled";
 937
 938                 usbphy0: usb-phy0 {
 939                         #phy-cells = <0>;
 940                         reg = <0x320>;
 941                         clocks = <&cru SCLK_OTGPHY0>;
 942                         clock-names = "phyclk";
 943                 };
 944
 945                 usbphy1: usb-phy1 {
 946                         #phy-cells = <0>;
 947                         reg = <0x334>;
 948                         clocks = <&cru SCLK_OTGPHY1>;
 949                         clock-names = "phyclk";
 950                 };
 951
 952                 usbphy2: usb-phy2 {
 953                         #phy-cells = <0>;
 954                         reg = <0x348>;
 955                         clocks = <&cru SCLK_OTGPHY2>;
 956                         clock-names = "phyclk";
 957                 };
 958         };
 959
 960         pinctrl: pinctrl {
 961                 compatible = "rockchip,rk3288-pinctrl";
 962                 rockchip,grf = <&grf>;
 963                 rockchip,pmu = <&pmu>;
 964                 #address-cells = <1>;
 965                 #size-cells = <1>;
 966                 ranges;
 967
 968                 gpio0: gpio0@ff750000 {
 969                         compatible = "rockchip,gpio-bank";
 970                         reg =   <0xff750000 0x100>;
 971                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&cru PCLK_GPIO0>;
 973
 974                         gpio-controller;
 975                         #gpio-cells = <2>;
 976
 977                         interrupt-controller;
 978                         #interrupt-cells = <2>;
 979                 };
 980
 981                 gpio1: gpio1@ff780000 {
 982                         compatible = "rockchip,gpio-bank";
 983                         reg = <0xff780000 0x100>;
 984                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 985                         clocks = <&cru PCLK_GPIO1>;
 986
 987                         gpio-controller;
 988                         #gpio-cells = <2>;
 989
 990                         interrupt-controller;
 991                         #interrupt-cells = <2>;
 992                 };
 993
 994                 gpio2: gpio2@ff790000 {
 995                         compatible = "rockchip,gpio-bank";
 996                         reg = <0xff790000 0x100>;
 997                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 998                         clocks = <&cru PCLK_GPIO2>;
 999
1000                         gpio-controller;
1001                         #gpio-cells = <2>;
1002
1003                         interrupt-controller;
1004                         #interrupt-cells = <2>;
1005                 };
1006
1007                 gpio3: gpio3@ff7a0000 {
1008                         compatible = "rockchip,gpio-bank";
1009                         reg = <0xff7a0000 0x100>;
1010                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1011                         clocks = <&cru PCLK_GPIO3>;
1012
1013                         gpio-controller;
1014                         #gpio-cells = <2>;
1015
1016                         interrupt-controller;
1017                         #interrupt-cells = <2>;
1018                 };
1019
1020                 gpio4: gpio4@ff7b0000 {
1021                         compatible = "rockchip,gpio-bank";
1022                         reg = <0xff7b0000 0x100>;
1023                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1024                         clocks = <&cru PCLK_GPIO4>;
1025
1026                         gpio-controller;
1027                         #gpio-cells = <2>;
1028
1029                         interrupt-controller;
1030                         #interrupt-cells = <2>;
1031                 };
1032
1033                 gpio5: gpio5@ff7c0000 {
1034                         compatible = "rockchip,gpio-bank";
1035                         reg = <0xff7c0000 0x100>;
1036                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1037                         clocks = <&cru PCLK_GPIO5>;
1038
1039                         gpio-controller;
1040                         #gpio-cells = <2>;
1041
1042                         interrupt-controller;
1043                         #interrupt-cells = <2>;
1044                 };
1045
1046                 gpio6: gpio6@ff7d0000 {
1047                         compatible = "rockchip,gpio-bank";
1048                         reg = <0xff7d0000 0x100>;
1049                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1050                         clocks = <&cru PCLK_GPIO6>;
1051
1052                         gpio-controller;
1053                         #gpio-cells = <2>;
1054
1055                         interrupt-controller;
1056                         #interrupt-cells = <2>;
1057                 };
1058
1059                 gpio7: gpio7@ff7e0000 {
1060                         compatible = "rockchip,gpio-bank";
1061                         reg = <0xff7e0000 0x100>;
1062                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1063                         clocks = <&cru PCLK_GPIO7>;
1064
1065                         gpio-controller;
1066                         #gpio-cells = <2>;
1067
1068                         interrupt-controller;
1069                         #interrupt-cells = <2>;
1070                 };
1071
1072                 gpio8: gpio8@ff7f0000 {
1073                         compatible = "rockchip,gpio-bank";
1074                         reg = <0xff7f0000 0x100>;
1075                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1076                         clocks = <&cru PCLK_GPIO8>;
1077
1078                         gpio-controller;
1079                         #gpio-cells = <2>;
1080
1081                         interrupt-controller;
1082                         #interrupt-cells = <2>;
1083                 };
1084
1085                 hdmi {
1086                         hdmi_ddc: hdmi-ddc {
1087                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1088                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1089                         };
1090                 };
1091
1092                 pcfg_pull_up: pcfg-pull-up {
1093                         bias-pull-up;
1094                 };
1095
1096                 pcfg_pull_down: pcfg-pull-down {
1097                         bias-pull-down;
1098                 };
1099
1100                 pcfg_pull_none: pcfg-pull-none {
1101                         bias-disable;
1102                 };
1103
1104                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1105                         bias-disable;
1106                         drive-strength = <12>;
1107                 };
1108
1109                 sleep {
1110                         global_pwroff: global-pwroff {
1111                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113
1114                         ddrio_pwroff: ddrio-pwroff {
1115                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1116                         };
1117
1118                         ddr0_retention: ddr0-retention {
1119                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1120                         };
1121
1122                         ddr1_retention: ddr1-retention {
1123                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1124                         };
1125                 };
1126
1127                 i2c0 {
1128                         i2c0_xfer: i2c0-xfer {
1129                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1130                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1131                         };
1132                 };
1133
1134                 i2c1 {
1135                         i2c1_xfer: i2c1-xfer {
1136                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1137                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1138                         };
1139                 };
1140
1141                 i2c2 {
1142                         i2c2_xfer: i2c2-xfer {
1143                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1144                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1145                         };
1146                 };
1147
1148                 i2c3 {
1149                         i2c3_xfer: i2c3-xfer {
1150                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1151                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1152                         };
1153                 };
1154
1155                 i2c4 {
1156                         i2c4_xfer: i2c4-xfer {
1157                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1158                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1159                         };
1160                 };
1161
1162                 i2c5 {
1163                         i2c5_xfer: i2c5-xfer {
1164                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1165                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1166                         };
1167                 };
1168
1169                 i2s0 {
1170                         i2s0_bus: i2s0-bus {
1171                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1172                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1173                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1174                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1175                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1176                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1177                         };
1178                 };
1179
1180                 sdmmc {
1181                         sdmmc_clk: sdmmc-clk {
1182                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1183                         };
1184
1185                         sdmmc_cmd: sdmmc-cmd {
1186                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1187                         };
1188
1189                         sdmmc_cd: sdmcc-cd {
1190                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1191                         };
1192
1193                         sdmmc_bus1: sdmmc-bus1 {
1194                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1195                         };
1196
1197                         sdmmc_bus4: sdmmc-bus4 {
1198                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1199                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1200                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1201                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1202                         };
1203                 };
1204
1205                 sdio0 {
1206                         sdio0_bus1: sdio0-bus1 {
1207                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1208                         };
1209
1210                         sdio0_bus4: sdio0-bus4 {
1211                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1212                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1213                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1214                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1215                         };
1216
1217                         sdio0_cmd: sdio0-cmd {
1218                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1219                         };
1220
1221                         sdio0_clk: sdio0-clk {
1222                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1223                         };
1224
1225                         sdio0_cd: sdio0-cd {
1226                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1227                         };
1228
1229                         sdio0_wp: sdio0-wp {
1230                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1231                         };
1232
1233                         sdio0_pwr: sdio0-pwr {
1234                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1235                         };
1236
1237                         sdio0_bkpwr: sdio0-bkpwr {
1238                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1239                         };
1240
1241                         sdio0_int: sdio0-int {
1242                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1243                         };
1244                 };
1245
1246                 sdio1 {
1247                         sdio1_bus1: sdio1-bus1 {
1248                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1249                         };
1250
1251                         sdio1_bus4: sdio1-bus4 {
1252                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1253                                                 <3 25 4 &pcfg_pull_up>,
1254                                                 <3 26 4 &pcfg_pull_up>,
1255                                                 <3 27 4 &pcfg_pull_up>;
1256                         };
1257
1258                         sdio1_cd: sdio1-cd {
1259                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1260                         };
1261
1262                         sdio1_wp: sdio1-wp {
1263                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1264                         };
1265
1266                         sdio1_bkpwr: sdio1-bkpwr {
1267                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1268                         };
1269
1270                         sdio1_int: sdio1-int {
1271                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1272                         };
1273
1274                         sdio1_cmd: sdio1-cmd {
1275                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1276                         };
1277
1278                         sdio1_clk: sdio1-clk {
1279                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1280                         };
1281
1282                         sdio1_pwr: sdio1-pwr {
1283                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1284                         };
1285                 };
1286
1287                 emmc {
1288                         emmc_clk: emmc-clk {
1289                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1290                         };
1291
1292                         emmc_cmd: emmc-cmd {
1293                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1294                         };
1295
1296                         emmc_pwr: emmc-pwr {
1297                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1298                         };
1299
1300                         emmc_bus1: emmc-bus1 {
1301                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1302                         };
1303
1304                         emmc_bus4: emmc-bus4 {
1305                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1306                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1307                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1308                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1309                         };
1310
1311                         emmc_bus8: emmc-bus8 {
1312                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1313                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1314                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1315                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1316                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1317                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1318                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1319                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1320                         };
1321                 };
1322
1323                 spi0 {
1324                         spi0_clk: spi0-clk {
1325                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1326                         };
1327                         spi0_cs0: spi0-cs0 {
1328                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1329                         };
1330                         spi0_tx: spi0-tx {
1331                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1332                         };
1333                         spi0_rx: spi0-rx {
1334                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1335                         };
1336                         spi0_cs1: spi0-cs1 {
1337                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1338                         };
1339                 };
1340                 spi1 {
1341                         spi1_clk: spi1-clk {
1342                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1343                         };
1344                         spi1_cs0: spi1-cs0 {
1345                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1346                         };
1347                         spi1_rx: spi1-rx {
1348                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1349                         };
1350                         spi1_tx: spi1-tx {
1351                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1352                         };
1353                 };
1354
1355                 spi2 {
1356                         spi2_cs1: spi2-cs1 {
1357                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1358                         };
1359                         spi2_clk: spi2-clk {
1360                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1361                         };
1362                         spi2_cs0: spi2-cs0 {
1363                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1364                         };
1365                         spi2_rx: spi2-rx {
1366                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1367                         };
1368                         spi2_tx: spi2-tx {
1369                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1370                         };
1371                 };
1372
1373                 uart0 {
1374                         uart0_xfer: uart0-xfer {
1375                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1376                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1377                         };
1378
1379                         uart0_cts: uart0-cts {
1380                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1381                         };
1382
1383                         uart0_rts: uart0-rts {
1384                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1385                         };
1386                 };
1387
1388                 uart1 {
1389                         uart1_xfer: uart1-xfer {
1390                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1391                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1392                         };
1393
1394                         uart1_cts: uart1-cts {
1395                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1396                         };
1397
1398                         uart1_rts: uart1-rts {
1399                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1400                         };
1401                 };
1402
1403                 uart2 {
1404                         uart2_xfer: uart2-xfer {
1405                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1406                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1407                         };
1408                         /* no rts / cts for uart2 */
1409                 };
1410
1411                 uart3 {
1412                         uart3_xfer: uart3-xfer {
1413                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1414                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1415                         };
1416
1417                         uart3_cts: uart3-cts {
1418                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1419                         };
1420
1421                         uart3_rts: uart3-rts {
1422                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1423                         };
1424                 };
1425
1426                 uart4 {
1427                         uart4_xfer: uart4-xfer {
1428                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1429                                                 <5 13 3 &pcfg_pull_none>;
1430                         };
1431
1432                         uart4_cts: uart4-cts {
1433                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1434                         };
1435
1436                         uart4_rts: uart4-rts {
1437                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1438                         };
1439                 };
1440
1441                 tsadc {
1442                         otp_gpio: otp-gpio {
1443                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1444                         };
1445
1446                         otp_out: otp-out {
1447                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1448                         };
1449                 };
1450
1451                 pwm0 {
1452                         pwm0_pin: pwm0-pin {
1453                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1454                         };
1455                 };
1456
1457                 pwm1 {
1458                         pwm1_pin: pwm1-pin {
1459                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1460                         };
1461                 };
1462
1463                 pwm2 {
1464                         pwm2_pin: pwm2-pin {
1465                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 pwm3 {
1470                         pwm3_pin: pwm3-pin {
1471                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 gmac {
1476                         rgmii_pins: rgmii-pins {
1477                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1478                                                 <3 31 3 &pcfg_pull_none>,
1479                                                 <3 26 3 &pcfg_pull_none>,
1480                                                 <3 27 3 &pcfg_pull_none>,
1481                                                 <3 28 3 &pcfg_pull_none_12ma>,
1482                                                 <3 29 3 &pcfg_pull_none_12ma>,
1483                                                 <3 24 3 &pcfg_pull_none_12ma>,
1484                                                 <3 25 3 &pcfg_pull_none_12ma>,
1485                                                 <4 0 3 &pcfg_pull_none>,
1486                                                 <4 5 3 &pcfg_pull_none>,
1487                                                 <4 6 3 &pcfg_pull_none>,
1488                                                 <4 9 3 &pcfg_pull_none_12ma>,
1489                                                 <4 4 3 &pcfg_pull_none_12ma>,
1490                                                 <4 1 3 &pcfg_pull_none>,
1491                                                 <4 3 3 &pcfg_pull_none>;
1492                         };
1493
1494                         rmii_pins: rmii-pins {
1495                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1496                                                 <3 31 3 &pcfg_pull_none>,
1497                                                 <3 28 3 &pcfg_pull_none>,
1498                                                 <3 29 3 &pcfg_pull_none>,
1499                                                 <4 0 3 &pcfg_pull_none>,
1500                                                 <4 5 3 &pcfg_pull_none>,
1501                                                 <4 4 3 &pcfg_pull_none>,
1502                                                 <4 1 3 &pcfg_pull_none>,
1503                                                 <4 2 3 &pcfg_pull_none>,
1504                                                 <4 3 3 &pcfg_pull_none>;
1505                         };
1506                 };
1507
1508                 spdif {
1509                         spdif_tx: spdif-tx {
1510                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1511                         };
1512                 };
1513         };
1514 };