arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 mshc0 = &emmc;
  63                 mshc1 = &sdmmc;
  64                 mshc2 = &sdio0;
  65                 mshc3 = &sdio1;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         arm-pmu {
  77                 compatible = "arm,cortex-a12-pmu";
  78                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88                 enable-method = "rockchip,rk3066-smp";
  89                 rockchip,pmu = <&pmu>;
  90
  91                 cpu0: cpu@500 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x500>;
  95                         resets = <&cru SRST_CORE0>;
  96                         operating-points = <
  97                                 /* KHz    uV */
  98                                 1608000 1350000
  99                                 1512000 1300000
 100                                 1416000 1200000
 101                                 1200000 1100000
 102                                 1008000 1050000
 103                                  816000 1000000
 104                                  696000  950000
 105                                  600000  900000
 106                                  408000  900000
 107                                  312000  900000
 108                                  216000  900000
 109                                  126000  900000
 110                         >;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clock-latency = <40000>;
 113                         clocks = <&cru ARMCLK>;
 114                 };
 115                 cpu1: cpu@501 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a12";
 118                         reg = <0x501>;
 119                         resets = <&cru SRST_CORE1>;
 120                 };
 121                 cpu2: cpu@502 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x502>;
 125                         resets = <&cru SRST_CORE2>;
 126                 };
 127                 cpu3: cpu@503 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a12";
 130                         reg = <0x503>;
 131                         resets = <&cru SRST_CORE3>;
 132                 };
 133         };
 134
 135         amba {
 136                 compatible = "arm,amba-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 dmac_peri: dma-controller@ff250000 {
 142                         compatible = "arm,pl330", "arm,primecell";
 143                         reg = <0xff250000 0x4000>;
 144                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 146                         #dma-cells = <1>;
 147                         arm,pl330-broken-no-flushp;
 148                         peripherals-req-type-burst;
 149                         clocks = <&cru ACLK_DMAC2>;
 150                         clock-names = "apb_pclk";
 151                 };
 152
 153                 dmac_bus_ns: dma-controller@ff600000 {
 154                         compatible = "arm,pl330", "arm,primecell";
 155                         reg = <0xff600000 0x4000>;
 156                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 158                         #dma-cells = <1>;
 159                         arm,pl330-broken-no-flushp;
 160                         peripherals-req-type-burst;
 161                         clocks = <&cru ACLK_DMAC1>;
 162                         clock-names = "apb_pclk";
 163                         status = "disabled";
 164                 };
 165
 166                 dmac_bus_s: dma-controller@ffb20000 {
 167                         compatible = "arm,pl330", "arm,primecell";
 168                         reg = <0xffb20000 0x4000>;
 169                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 171                         #dma-cells = <1>;
 172                         arm,pl330-broken-no-flushp;
 173                         peripherals-req-type-burst;
 174                         clocks = <&cru ACLK_DMAC1>;
 175                         clock-names = "apb_pclk";
 176                 };
 177         };
 178
 179         reserved-memory {
 180                 #address-cells = <1>;
 181                 #size-cells = <1>;
 182                 ranges;
 183
 184                 /*
 185                  * The rk3288 cannot use the memory area above 0xfe000000
 186                  * for dma operations for some reason. While there is
 187                  * probably a better solution available somewhere, we
 188                  * haven't found it yet and while devices with 2GB of ram
 189                  * are not affected, this issue prevents 4GB from booting.
 190                  * So to make these devices at least bootable, block
 191                  * this area for the time being until the real solution
 192                  * is found.
 193                  */
 194                 dma-unusable@fe000000 {
 195                         reg = <0xfe000000 0x1000000>;
 196                 };
 197         };
 198
 199         xin24m: oscillator {
 200                 compatible = "fixed-clock";
 201                 clock-frequency = <24000000>;
 202                 clock-output-names = "xin24m";
 203                 #clock-cells = <0>;
 204         };
 205
 206         edp_phy: edp-phy {
 207                 compatible = "rockchip,rk3288-dp-phy";
 208                 clocks = <&cru SCLK_EDP_24M>;
 209                 clock-names = "24m";
 210                 rockchip,grf = <&grf>;
 211                 #phy-cells = <0>;
 212                 status = "disabled";
 213         };
 214
 215         timer {
 216                 compatible = "arm,armv7-timer";
 217                 arm,cpu-registers-not-fw-configured;
 218                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 219                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 222                 clock-frequency = <24000000>;
 223         };
 224
 225         timer: timer@ff810000 {
 226                 compatible = "rockchip,rk3288-timer";
 227                 reg = <0xff810000 0x20>;
 228                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 230                 clock-names = "timer", "pclk";
 231         };
 232
 233         display-subsystem {
 234                 compatible = "rockchip,display-subsystem";
 235                 ports = <&vopl_out>, <&vopb_out>;
 236         };
 237
 238         sdmmc: dwmmc@ff0c0000 {
 239                 compatible = "rockchip,rk3288-dw-mshc";
 240                 clock-freq-min-max = <400000 150000000>;
 241                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 242                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 243                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 244                 fifo-depth = <0x100>;
 245                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 246                 reg = <0xff0c0000 0x4000>;
 247                 status = "disabled";
 248         };
 249
 250         sdio0: dwmmc@ff0d0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 clock-freq-min-max = <400000 150000000>;
 253                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 254                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0xff0d0000 0x4000>;
 259                 status = "disabled";
 260         };
 261
 262         sdio1: dwmmc@ff0e0000 {
 263                 compatible = "rockchip,rk3288-dw-mshc";
 264                 clock-freq-min-max = <400000 150000000>;
 265                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 266                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 267                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 268                 fifo-depth = <0x100>;
 269                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 270                 reg = <0xff0e0000 0x4000>;
 271                 status = "disabled";
 272         };
 273
 274         emmc: dwmmc@ff0f0000 {
 275                 compatible = "rockchip,rk3288-dw-mshc";
 276                 clock-freq-min-max = <400000 150000000>;
 277                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 278                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 279                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 280                 fifo-depth = <0x100>;
 281                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 282                 reg = <0xff0f0000 0x4000>;
 283                 status = "disabled";
 284         };
 285
 286         saradc: saradc@ff100000 {
 287                 compatible = "rockchip,saradc";
 288                 reg = <0xff100000 0x100>;
 289                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 290                 #io-channel-cells = <1>;
 291                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 292                 clock-names = "saradc", "apb_pclk";
 293                 status = "disabled";
 294         };
 295
 296         spi0: spi@ff110000 {
 297                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 298                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 299                 clock-names = "spiclk", "apb_pclk";
 300                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 301                 dma-names = "tx", "rx";
 302                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 305                 reg = <0xff110000 0x1000>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 status = "disabled";
 309         };
 310
 311         spi1: spi@ff120000 {
 312                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 313                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 314                 clock-names = "spiclk", "apb_pclk";
 315                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 316                 dma-names = "tx", "rx";
 317                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 320                 reg = <0xff120000 0x1000>;
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 status = "disabled";
 324         };
 325
 326         spi2: spi@ff130000 {
 327                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 328                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 329                 clock-names = "spiclk", "apb_pclk";
 330                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 331                 dma-names = "tx", "rx";
 332                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 335                 reg = <0xff130000 0x1000>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 status = "disabled";
 339         };
 340
 341         i2c1: i2c@ff140000 {
 342                 compatible = "rockchip,rk3288-i2c";
 343                 reg = <0xff140000 0x1000>;
 344                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 clock-names = "i2c";
 348                 clocks = <&cru PCLK_I2C1>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&i2c1_xfer>;
 351                 status = "disabled";
 352         };
 353
 354         i2c3: i2c@ff150000 {
 355                 compatible = "rockchip,rk3288-i2c";
 356                 reg = <0xff150000 0x1000>;
 357                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 clock-names = "i2c";
 361                 clocks = <&cru PCLK_I2C3>;
 362                 pinctrl-names = "default";
 363                 pinctrl-0 = <&i2c3_xfer>;
 364                 status = "disabled";
 365         };
 366
 367         i2c4: i2c@ff160000 {
 368                 compatible = "rockchip,rk3288-i2c";
 369                 reg = <0xff160000 0x1000>;
 370                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 clock-names = "i2c";
 374                 clocks = <&cru PCLK_I2C4>;
 375                 pinctrl-names = "default";
 376                 pinctrl-0 = <&i2c4_xfer>;
 377                 status = "disabled";
 378         };
 379
 380         i2c5: i2c@ff170000 {
 381                 compatible = "rockchip,rk3288-i2c";
 382                 reg = <0xff170000 0x1000>;
 383                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 clock-names = "i2c";
 387                 clocks = <&cru PCLK_I2C5>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&i2c5_xfer>;
 390                 status = "disabled";
 391         };
 392
 393         uart0: serial@ff180000 {
 394                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 395                 reg = <0xff180000 0x100>;
 396                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 397                 reg-shift = <2>;
 398                 reg-io-width = <4>;
 399                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 400                 clock-names = "baudclk", "apb_pclk";
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&uart0_xfer>;
 403                 status = "disabled";
 404         };
 405
 406         uart1: serial@ff190000 {
 407                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 408                 reg = <0xff190000 0x100>;
 409                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 410                 reg-shift = <2>;
 411                 reg-io-width = <4>;
 412                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 413                 clock-names = "baudclk", "apb_pclk";
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&uart1_xfer>;
 416                 status = "disabled";
 417         };
 418
 419         uart2: serial@ff690000 {
 420                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 421                 reg = <0xff690000 0x100>;
 422                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 423                 reg-shift = <2>;
 424                 reg-io-width = <4>;
 425                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 426                 clock-names = "baudclk", "apb_pclk";
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&uart2_xfer>;
 429                 status = "disabled";
 430         };
 431
 432         uart3: serial@ff1b0000 {
 433                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 434                 reg = <0xff1b0000 0x100>;
 435                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 436                 reg-shift = <2>;
 437                 reg-io-width = <4>;
 438                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 439                 clock-names = "baudclk", "apb_pclk";
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&uart3_xfer>;
 442                 status = "disabled";
 443         };
 444
 445         uart4: serial@ff1c0000 {
 446                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 447                 reg = <0xff1c0000 0x100>;
 448                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 449                 reg-shift = <2>;
 450                 reg-io-width = <4>;
 451                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 452                 clock-names = "baudclk", "apb_pclk";
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&uart4_xfer>;
 455                 status = "disabled";
 456         };
 457
 458         thermal-zones {
 459                 #include "rk3288-thermal.dtsi"
 460         };
 461
 462         tsadc: tsadc@ff280000 {
 463                 compatible = "rockchip,rk3288-tsadc";
 464                 reg = <0xff280000 0x100>;
 465                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 466                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 467                 clock-names = "tsadc", "apb_pclk";
 468                 resets = <&cru SRST_TSADC>;
 469                 reset-names = "tsadc-apb";
 470                 pinctrl-names = "init", "default", "sleep";
 471                 pinctrl-0 = <&otp_gpio>;
 472                 pinctrl-1 = <&otp_out>;
 473                 pinctrl-2 = <&otp_gpio>;
 474                 #thermal-sensor-cells = <1>;
 475                 rockchip,hw-tshut-temp = <95000>;
 476                 status = "disabled";
 477         };
 478
 479         gmac: ethernet@ff290000 {
 480                 compatible = "rockchip,rk3288-gmac";
 481                 reg = <0xff290000 0x10000>;
 482                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 483                 interrupt-names = "macirq";
 484                 rockchip,grf = <&grf>;
 485                 clocks = <&cru SCLK_MAC>,
 486                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 487                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 488                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 489                 clock-names = "stmmaceth",
 490                         "mac_clk_rx", "mac_clk_tx",
 491                         "clk_mac_ref", "clk_mac_refout",
 492                         "aclk_mac", "pclk_mac";
 493                 resets = <&cru SRST_MAC>;
 494                 reset-names = "stmmaceth";
 495                 status = "disabled";
 496         };
 497
 498         usb_host0_ehci: usb@ff500000 {
 499                 compatible = "generic-ehci";
 500                 reg = <0xff500000 0x100>;
 501                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 502                 clocks = <&cru HCLK_USBHOST0>;
 503                 clock-names = "usbhost";
 504                 phys = <&usbphy1>;
 505                 phy-names = "usb";
 506                 status = "disabled";
 507         };
 508
 509         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 510
 511         usb_host1: usb@ff540000 {
 512                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 513                                 "snps,dwc2";
 514                 reg = <0xff540000 0x40000>;
 515                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&cru HCLK_USBHOST1>;
 517                 clock-names = "otg";
 518                 dr_mode = "host";
 519                 phys = <&usbphy2>;
 520                 phy-names = "usb2-phy";
 521                 status = "disabled";
 522         };
 523
 524         usb_otg: usb@ff580000 {
 525                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 526                                 "snps,dwc2";
 527                 reg = <0xff580000 0x40000>;
 528                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 529                 clocks = <&cru HCLK_OTG0>;
 530                 clock-names = "otg";
 531                 dr_mode = "otg";
 532                 g-np-tx-fifo-size = <16>;
 533                 g-rx-fifo-size = <275>;
 534                 g-tx-fifo-size = <256 128 128 64 64 32>;
 535                 g-use-dma;
 536                 phys = <&usbphy0>;
 537                 phy-names = "usb2-phy";
 538                 status = "disabled";
 539         };
 540
 541         usb_hsic: usb@ff5c0000 {
 542                 compatible = "generic-ehci";
 543                 reg = <0xff5c0000 0x100>;
 544                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&cru HCLK_HSIC>;
 546                 clock-names = "usbhost";
 547                 status = "disabled";
 548         };
 549
 550         i2c0: i2c@ff650000 {
 551                 compatible = "rockchip,rk3288-i2c";
 552                 reg = <0xff650000 0x1000>;
 553                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 clock-names = "i2c";
 557                 clocks = <&cru PCLK_I2C0>;
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&i2c0_xfer>;
 560                 status = "disabled";
 561         };
 562
 563         i2c2: i2c@ff660000 {
 564                 compatible = "rockchip,rk3288-i2c";
 565                 reg = <0xff660000 0x1000>;
 566                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 clock-names = "i2c";
 570                 clocks = <&cru PCLK_I2C2>;
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&i2c2_xfer>;
 573                 status = "disabled";
 574         };
 575
 576         pwm0: pwm@ff680000 {
 577                 compatible = "rockchip,rk3288-pwm";
 578                 reg = <0xff680000 0x10>;
 579                 #pwm-cells = <3>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&pwm0_pin>;
 582                 clocks = <&cru PCLK_PWM>;
 583                 clock-names = "pwm";
 584                 status = "disabled";
 585         };
 586
 587         pwm1: pwm@ff680010 {
 588                 compatible = "rockchip,rk3288-pwm";
 589                 reg = <0xff680010 0x10>;
 590                 #pwm-cells = <3>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&pwm1_pin>;
 593                 clocks = <&cru PCLK_PWM>;
 594                 clock-names = "pwm";
 595                 status = "disabled";
 596         };
 597
 598         pwm2: pwm@ff680020 {
 599                 compatible = "rockchip,rk3288-pwm";
 600                 reg = <0xff680020 0x10>;
 601                 #pwm-cells = <3>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&pwm2_pin>;
 604                 clocks = <&cru PCLK_PWM>;
 605                 clock-names = "pwm";
 606                 status = "disabled";
 607         };
 608
 609         pwm3: pwm@ff680030 {
 610                 compatible = "rockchip,rk3288-pwm";
 611                 reg = <0xff680030 0x10>;
 612                 #pwm-cells = <2>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&pwm3_pin>;
 615                 clocks = <&cru PCLK_PWM>;
 616                 clock-names = "pwm";
 617                 status = "disabled";
 618         };
 619
 620         bus_intmem@ff700000 {
 621                 compatible = "mmio-sram";
 622                 reg = <0xff700000 0x18000>;
 623                 #address-cells = <1>;
 624                 #size-cells = <1>;
 625                 ranges = <0 0xff700000 0x18000>;
 626                 smp-sram@0 {
 627                         compatible = "rockchip,rk3066-smp-sram";
 628                         reg = <0x00 0x10>;
 629                 };
 630         };
 631
 632         sram@ff720000 {
 633                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 634                 reg = <0xff720000 0x1000>;
 635         };
 636
 637         pmu: power-management@ff730000 {
 638                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 639                 reg = <0xff730000 0x100>;
 640
 641                 power: power-controller {
 642                         compatible = "rockchip,rk3288-power-controller";
 643                         #power-domain-cells = <1>;
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646
 647                         /*
 648                          * Note: Although SCLK_* are the working clocks
 649                          * of device without including on the NOC, needed for
 650                          * synchronous reset.
 651                          *
 652                          * The clocks on the which NOC:
 653                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 654                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 655                          * ACLK_RGA is on ACLK_RGA_NIU.
 656                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 657                          *
 658                          * Which clock are device clocks:
 659                          *      clocks          devices
 660                          *      *_IEP           IEP:Image Enhancement Processor
 661                          *      *_ISP           ISP:Image Signal Processing
 662                          *      *_VIP           VIP:Video Input Processor
 663                          *      *_VOP*          VOP:Visual Output Processor
 664                          *      *_RGA           RGA
 665                          *      *_EDP*          EDP
 666                          *      *_LVDS_*        LVDS
 667                          *      *_HDMI          HDMI
 668                          *      *_MIPI_*        MIPI
 669                          */
 670                         pd_vio {
 671                                 reg = <RK3288_PD_VIO>;
 672                                 clocks = <&cru ACLK_IEP>,
 673                                          <&cru ACLK_ISP>,
 674                                          <&cru ACLK_RGA>,
 675                                          <&cru ACLK_VIP>,
 676                                          <&cru ACLK_VOP0>,
 677                                          <&cru ACLK_VOP1>,
 678                                          <&cru DCLK_VOP0>,
 679                                          <&cru DCLK_VOP1>,
 680                                          <&cru HCLK_IEP>,
 681                                          <&cru HCLK_ISP>,
 682                                          <&cru HCLK_RGA>,
 683                                          <&cru HCLK_VIP>,
 684                                          <&cru HCLK_VOP0>,
 685                                          <&cru HCLK_VOP1>,
 686                                          <&cru PCLK_EDP_CTRL>,
 687                                          <&cru PCLK_HDMI_CTRL>,
 688                                          <&cru PCLK_LVDS_PHY>,
 689                                          <&cru PCLK_MIPI_CSI>,
 690                                          <&cru PCLK_MIPI_DSI0>,
 691                                          <&cru PCLK_MIPI_DSI1>,
 692                                          <&cru SCLK_EDP_24M>,
 693                                          <&cru SCLK_EDP>,
 694                                          <&cru SCLK_ISP_JPE>,
 695                                          <&cru SCLK_ISP>,
 696                                          <&cru SCLK_RGA>;
 697                         };
 698
 699                         /*
 700                          * Note: The following 3 are HEVC(H.265) clocks,
 701                          * and on the ACLK_HEVC_NIU (NOC).
 702                          */
 703                         pd_hevc {
 704                                 reg = <RK3288_PD_HEVC>;
 705                                 clocks = <&cru ACLK_HEVC>,
 706                                          <&cru SCLK_HEVC_CABAC>,
 707                                          <&cru SCLK_HEVC_CORE>;
 708                         };
 709
 710                         /*
 711                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 712                          * (video endecoder & decoder) clocks that on the
 713                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 714                          */
 715                         pd_video {
 716                                 reg = <RK3288_PD_VIDEO>;
 717                                 clocks = <&cru ACLK_VCODEC>,
 718                                          <&cru HCLK_VCODEC>;
 719                         };
 720
 721                         /*
 722                          * Note: ACLK_GPU is the GPU clock,
 723                          * and on the ACLK_GPU_NIU (NOC).
 724                          */
 725                         pd_gpu {
 726                                 reg = <RK3288_PD_GPU>;
 727                                 clocks = <&cru ACLK_GPU>;
 728                         };
 729                 };
 730         };
 731
 732         sgrf: syscon@ff740000 {
 733                 compatible = "rockchip,rk3288-sgrf", "syscon";
 734                 reg = <0xff740000 0x1000>;
 735         };
 736
 737         cru: clock-controller@ff760000 {
 738                 compatible = "rockchip,rk3288-cru";
 739                 reg = <0xff760000 0x1000>;
 740                 rockchip,grf = <&grf>;
 741                 #clock-cells = <1>;
 742                 #reset-cells = <1>;
 743                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 744                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 745                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 746                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 747                                   <&cru PCLK_PERI>;
 748                 assigned-clock-rates = <594000000>, <400000000>,
 749                                        <500000000>, <300000000>,
 750                                        <150000000>, <75000000>,
 751                                        <300000000>, <150000000>,
 752                                        <75000000>;
 753         };
 754
 755         grf: syscon@ff770000 {
 756                 compatible = "rockchip,rk3288-grf", "syscon";
 757                 reg = <0xff770000 0x1000>;
 758         };
 759
 760         wdt: watchdog@ff800000 {
 761                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 762                 reg = <0xff800000 0x100>;
 763                 clocks = <&cru PCLK_WDT>;
 764                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 765                 status = "disabled";
 766         };
 767
 768         spdif: sound@ff88b0000 {
 769                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 770                 reg = <0xff8b0000 0x10000>;
 771                 #sound-dai-cells = <0>;
 772                 clock-names = "hclk", "mclk";
 773                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 774                 dmas = <&dmac_bus_s 3>;
 775                 dma-names = "tx";
 776                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 777                 pinctrl-names = "default";
 778                 pinctrl-0 = <&spdif_tx>;
 779                 rockchip,grf = <&grf>;
 780                 status = "disabled";
 781         };
 782
 783         i2s: i2s@ff890000 {
 784                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 785                 reg = <0xff890000 0x10000>;
 786                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 787                 #address-cells = <1>;
 788                 #size-cells = <0>;
 789                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 790                 dma-names = "tx", "rx";
 791                 clock-names = "i2s_hclk", "i2s_clk";
 792                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 793                 pinctrl-names = "default";
 794                 pinctrl-0 = <&i2s0_bus>;
 795                 status = "disabled";
 796         };
 797
 798         vopb: vop@ff930000 {
 799                 compatible = "rockchip,rk3288-vop";
 800                 reg = <0xff930000 0x19c>;
 801                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 802                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 803                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 804                 power-domains = <&power RK3288_PD_VIO>;
 805                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 806                 reset-names = "axi", "ahb", "dclk";
 807                 iommus = <&vopb_mmu>;
 808                 status = "disabled";
 809
 810                 vopb_out: port {
 811                         #address-cells = <1>;
 812                         #size-cells = <0>;
 813
 814                         vopb_out_hdmi: endpoint@0 {
 815                                 reg = <0>;
 816                                 remote-endpoint = <&hdmi_in_vopb>;
 817                         };
 818                         vopb_out_mipi: endpoint@2 {
 819                                 reg = <2>;
 820                                 remote-endpoint = <&mipi_in_vopb>;
 821                         };
 822                 };
 823         };
 824
 825         vopb_mmu: iommu@ff930300 {
 826                 compatible = "rockchip,iommu";
 827                 reg = <0xff930300 0x100>;
 828                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 829                 interrupt-names = "vopb_mmu";
 830                 power-domains = <&power RK3288_PD_VIO>;
 831                 #iommu-cells = <0>;
 832                 status = "disabled";
 833         };
 834
 835         vopl: vop@ff940000 {
 836                 compatible = "rockchip,rk3288-vop";
 837                 reg = <0xff940000 0x19c>;
 838                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 840                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 841                 power-domains = <&power RK3288_PD_VIO>;
 842                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 843                 reset-names = "axi", "ahb", "dclk";
 844                 iommus = <&vopl_mmu>;
 845                 status = "disabled";
 846
 847                 vopl_out: port {
 848                         #address-cells = <1>;
 849                         #size-cells = <0>;
 850
 851                         vopl_out_hdmi: endpoint@0 {
 852                                 reg = <0>;
 853                                 remote-endpoint = <&hdmi_in_vopl>;
 854                         };
 855                         vopl_out_mipi: endpoint@2 {
 856                                 reg = <2>;
 857                                 remote-endpoint = <&mipi_in_vopl>;
 858                         };
 859                 };
 860         };
 861
 862         vopl_mmu: iommu@ff940300 {
 863                 compatible = "rockchip,iommu";
 864                 reg = <0xff940300 0x100>;
 865                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 866                 interrupt-names = "vopl_mmu";
 867                 power-domains = <&power RK3288_PD_VIO>;
 868                 #iommu-cells = <0>;
 869                 status = "disabled";
 870         };
 871
 872         mipi_dsi: mipi@ff960000 {
 873                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 874                 reg = <0xff960000 0x4000>;
 875                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 876                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 877                 clock-names = "ref", "pclk";
 878                 rockchip,grf = <&grf>;
 879                 #address-cells = <1>;
 880                 #size-cells = <0>;
 881                 status = "disabled";
 882
 883                 ports {
 884                         #address-cells = <1>;
 885                         #size-cells = <0>;
 886                         reg = <1>;
 887
 888                         mipi_in: port {
 889                                 #address-cells = <1>;
 890                                 #size-cells = <0>;
 891                                 mipi_in_vopb: endpoint@0 {
 892                                         reg = <0>;
 893                                         remote-endpoint = <&vopb_out_mipi>;
 894                                 };
 895                                 mipi_in_vopl: endpoint@1 {
 896                                         reg = <1>;
 897                                         remote-endpoint = <&vopl_out_mipi>;
 898                                 };
 899                         };
 900                 };
 901         };
 902
 903         hdmi: hdmi@ff980000 {
 904                 compatible = "rockchip,rk3288-dw-hdmi";
 905                 reg = <0xff980000 0x20000>;
 906                 reg-io-width = <4>;
 907                 rockchip,grf = <&grf>;
 908                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 909                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 910                 clock-names = "iahb", "isfr";
 911                 power-domains = <&power RK3288_PD_VIO>;
 912                 status = "disabled";
 913
 914                 ports {
 915                         hdmi_in: port {
 916                                 #address-cells = <1>;
 917                                 #size-cells = <0>;
 918                                 hdmi_in_vopb: endpoint@0 {
 919                                         reg = <0>;
 920                                         remote-endpoint = <&vopb_out_hdmi>;
 921                                 };
 922                                 hdmi_in_vopl: endpoint@1 {
 923                                         reg = <1>;
 924                                         remote-endpoint = <&vopl_out_hdmi>;
 925                                 };
 926                         };
 927                 };
 928         };
 929
 930         gic: interrupt-controller@ffc01000 {
 931                 compatible = "arm,gic-400";
 932                 interrupt-controller;
 933                 #interrupt-cells = <3>;
 934                 #address-cells = <0>;
 935
 936                 reg = <0xffc01000 0x1000>,
 937                       <0xffc02000 0x1000>,
 938                       <0xffc04000 0x2000>,
 939                       <0xffc06000 0x2000>;
 940                 interrupts = <GIC_PPI 9 0xf04>;
 941         };
 942
 943         usbphy: phy {
 944                 compatible = "rockchip,rk3288-usb-phy";
 945                 rockchip,grf = <&grf>;
 946                 #address-cells = <1>;
 947                 #size-cells = <0>;
 948                 status = "disabled";
 949
 950                 usbphy0: usb-phy0 {
 951                         #phy-cells = <0>;
 952                         reg = <0x320>;
 953                         clocks = <&cru SCLK_OTGPHY0>;
 954                         clock-names = "phyclk";
 955                 };
 956
 957                 usbphy1: usb-phy1 {
 958                         #phy-cells = <0>;
 959                         reg = <0x334>;
 960                         clocks = <&cru SCLK_OTGPHY1>;
 961                         clock-names = "phyclk";
 962                 };
 963
 964                 usbphy2: usb-phy2 {
 965                         #phy-cells = <0>;
 966                         reg = <0x348>;
 967                         clocks = <&cru SCLK_OTGPHY2>;
 968                         clock-names = "phyclk";
 969                 };
 970         };
 971
 972         pinctrl: pinctrl {
 973                 compatible = "rockchip,rk3288-pinctrl";
 974                 rockchip,grf = <&grf>;
 975                 rockchip,pmu = <&pmu>;
 976                 #address-cells = <1>;
 977                 #size-cells = <1>;
 978                 ranges;
 979
 980                 gpio0: gpio0@ff750000 {
 981                         compatible = "rockchip,gpio-bank";
 982                         reg =   <0xff750000 0x100>;
 983                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 984                         clocks = <&cru PCLK_GPIO0>;
 985
 986                         gpio-controller;
 987                         #gpio-cells = <2>;
 988
 989                         interrupt-controller;
 990                         #interrupt-cells = <2>;
 991                 };
 992
 993                 gpio1: gpio1@ff780000 {
 994                         compatible = "rockchip,gpio-bank";
 995                         reg = <0xff780000 0x100>;
 996                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 997                         clocks = <&cru PCLK_GPIO1>;
 998
 999                         gpio-controller;
1000                         #gpio-cells = <2>;
1001
1002                         interrupt-controller;
1003                         #interrupt-cells = <2>;
1004                 };
1005
1006                 gpio2: gpio2@ff790000 {
1007                         compatible = "rockchip,gpio-bank";
1008                         reg = <0xff790000 0x100>;
1009                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1010                         clocks = <&cru PCLK_GPIO2>;
1011
1012                         gpio-controller;
1013                         #gpio-cells = <2>;
1014
1015                         interrupt-controller;
1016                         #interrupt-cells = <2>;
1017                 };
1018
1019                 gpio3: gpio3@ff7a0000 {
1020                         compatible = "rockchip,gpio-bank";
1021                         reg = <0xff7a0000 0x100>;
1022                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1023                         clocks = <&cru PCLK_GPIO3>;
1024
1025                         gpio-controller;
1026                         #gpio-cells = <2>;
1027
1028                         interrupt-controller;
1029                         #interrupt-cells = <2>;
1030                 };
1031
1032                 gpio4: gpio4@ff7b0000 {
1033                         compatible = "rockchip,gpio-bank";
1034                         reg = <0xff7b0000 0x100>;
1035                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1036                         clocks = <&cru PCLK_GPIO4>;
1037
1038                         gpio-controller;
1039                         #gpio-cells = <2>;
1040
1041                         interrupt-controller;
1042                         #interrupt-cells = <2>;
1043                 };
1044
1045                 gpio5: gpio5@ff7c0000 {
1046                         compatible = "rockchip,gpio-bank";
1047                         reg = <0xff7c0000 0x100>;
1048                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1049                         clocks = <&cru PCLK_GPIO5>;
1050
1051                         gpio-controller;
1052                         #gpio-cells = <2>;
1053
1054                         interrupt-controller;
1055                         #interrupt-cells = <2>;
1056                 };
1057
1058                 gpio6: gpio6@ff7d0000 {
1059                         compatible = "rockchip,gpio-bank";
1060                         reg = <0xff7d0000 0x100>;
1061                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1062                         clocks = <&cru PCLK_GPIO6>;
1063
1064                         gpio-controller;
1065                         #gpio-cells = <2>;
1066
1067                         interrupt-controller;
1068                         #interrupt-cells = <2>;
1069                 };
1070
1071                 gpio7: gpio7@ff7e0000 {
1072                         compatible = "rockchip,gpio-bank";
1073                         reg = <0xff7e0000 0x100>;
1074                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1075                         clocks = <&cru PCLK_GPIO7>;
1076
1077                         gpio-controller;
1078                         #gpio-cells = <2>;
1079
1080                         interrupt-controller;
1081                         #interrupt-cells = <2>;
1082                 };
1083
1084                 gpio8: gpio8@ff7f0000 {
1085                         compatible = "rockchip,gpio-bank";
1086                         reg = <0xff7f0000 0x100>;
1087                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1088                         clocks = <&cru PCLK_GPIO8>;
1089
1090                         gpio-controller;
1091                         #gpio-cells = <2>;
1092
1093                         interrupt-controller;
1094                         #interrupt-cells = <2>;
1095                 };
1096
1097                 hdmi {
1098                         hdmi_ddc: hdmi-ddc {
1099                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1100                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1101                         };
1102                 };
1103
1104                 pcfg_pull_up: pcfg-pull-up {
1105                         bias-pull-up;
1106                 };
1107
1108                 pcfg_pull_down: pcfg-pull-down {
1109                         bias-pull-down;
1110                 };
1111
1112                 pcfg_pull_none: pcfg-pull-none {
1113                         bias-disable;
1114                 };
1115
1116                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1117                         bias-disable;
1118                         drive-strength = <12>;
1119                 };
1120
1121                 sleep {
1122                         global_pwroff: global-pwroff {
1123                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1124                         };
1125
1126                         ddrio_pwroff: ddrio-pwroff {
1127                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129
1130                         ddr0_retention: ddr0-retention {
1131                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1132                         };
1133
1134                         ddr1_retention: ddr1-retention {
1135                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1136                         };
1137                 };
1138
1139                 i2c0 {
1140                         i2c0_xfer: i2c0-xfer {
1141                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1142                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1143                         };
1144                 };
1145
1146                 i2c1 {
1147                         i2c1_xfer: i2c1-xfer {
1148                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1149                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151                 };
1152
1153                 i2c2 {
1154                         i2c2_xfer: i2c2-xfer {
1155                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1156                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1157                         };
1158                 };
1159
1160                 i2c3 {
1161                         i2c3_xfer: i2c3-xfer {
1162                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1163                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1164                         };
1165                 };
1166
1167                 i2c4 {
1168                         i2c4_xfer: i2c4-xfer {
1169                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1170                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1171                         };
1172                 };
1173
1174                 i2c5 {
1175                         i2c5_xfer: i2c5-xfer {
1176                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1177                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1178                         };
1179                 };
1180
1181                 i2s0 {
1182                         i2s0_bus: i2s0-bus {
1183                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1184                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1185                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1186                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1187                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1188                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1189                         };
1190                 };
1191
1192                 sdmmc {
1193                         sdmmc_clk: sdmmc-clk {
1194                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1195                         };
1196
1197                         sdmmc_cmd: sdmmc-cmd {
1198                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1199                         };
1200
1201                         sdmmc_cd: sdmcc-cd {
1202                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1203                         };
1204
1205                         sdmmc_bus1: sdmmc-bus1 {
1206                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1207                         };
1208
1209                         sdmmc_bus4: sdmmc-bus4 {
1210                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1211                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1212                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1213                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1214                         };
1215                 };
1216
1217                 sdio0 {
1218                         sdio0_bus1: sdio0-bus1 {
1219                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1220                         };
1221
1222                         sdio0_bus4: sdio0-bus4 {
1223                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1224                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1225                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1226                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1227                         };
1228
1229                         sdio0_cmd: sdio0-cmd {
1230                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1231                         };
1232
1233                         sdio0_clk: sdio0-clk {
1234                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1235                         };
1236
1237                         sdio0_cd: sdio0-cd {
1238                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1239                         };
1240
1241                         sdio0_wp: sdio0-wp {
1242                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1243                         };
1244
1245                         sdio0_pwr: sdio0-pwr {
1246                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1247                         };
1248
1249                         sdio0_bkpwr: sdio0-bkpwr {
1250                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1251                         };
1252
1253                         sdio0_int: sdio0-int {
1254                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1255                         };
1256                 };
1257
1258                 sdio1 {
1259                         sdio1_bus1: sdio1-bus1 {
1260                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1261                         };
1262
1263                         sdio1_bus4: sdio1-bus4 {
1264                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1265                                                 <3 25 4 &pcfg_pull_up>,
1266                                                 <3 26 4 &pcfg_pull_up>,
1267                                                 <3 27 4 &pcfg_pull_up>;
1268                         };
1269
1270                         sdio1_cd: sdio1-cd {
1271                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1272                         };
1273
1274                         sdio1_wp: sdio1-wp {
1275                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1276                         };
1277
1278                         sdio1_bkpwr: sdio1-bkpwr {
1279                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1280                         };
1281
1282                         sdio1_int: sdio1-int {
1283                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1284                         };
1285
1286                         sdio1_cmd: sdio1-cmd {
1287                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1288                         };
1289
1290                         sdio1_clk: sdio1-clk {
1291                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1292                         };
1293
1294                         sdio1_pwr: sdio1-pwr {
1295                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1296                         };
1297                 };
1298
1299                 emmc {
1300                         emmc_clk: emmc-clk {
1301                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1302                         };
1303
1304                         emmc_cmd: emmc-cmd {
1305                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1306                         };
1307
1308                         emmc_pwr: emmc-pwr {
1309                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1310                         };
1311
1312                         emmc_bus1: emmc-bus1 {
1313                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1314                         };
1315
1316                         emmc_bus4: emmc-bus4 {
1317                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1318                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1319                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1320                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1321                         };
1322
1323                         emmc_bus8: emmc-bus8 {
1324                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1325                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1326                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1327                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1328                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1329                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1330                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1331                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1332                         };
1333                 };
1334
1335                 spi0 {
1336                         spi0_clk: spi0-clk {
1337                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1338                         };
1339                         spi0_cs0: spi0-cs0 {
1340                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1341                         };
1342                         spi0_tx: spi0-tx {
1343                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1344                         };
1345                         spi0_rx: spi0-rx {
1346                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1347                         };
1348                         spi0_cs1: spi0-cs1 {
1349                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1350                         };
1351                 };
1352                 spi1 {
1353                         spi1_clk: spi1-clk {
1354                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1355                         };
1356                         spi1_cs0: spi1-cs0 {
1357                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1358                         };
1359                         spi1_rx: spi1-rx {
1360                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1361                         };
1362                         spi1_tx: spi1-tx {
1363                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1364                         };
1365                 };
1366
1367                 spi2 {
1368                         spi2_cs1: spi2-cs1 {
1369                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1370                         };
1371                         spi2_clk: spi2-clk {
1372                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1373                         };
1374                         spi2_cs0: spi2-cs0 {
1375                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1376                         };
1377                         spi2_rx: spi2-rx {
1378                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1379                         };
1380                         spi2_tx: spi2-tx {
1381                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1382                         };
1383                 };
1384
1385                 uart0 {
1386                         uart0_xfer: uart0-xfer {
1387                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1388                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1389                         };
1390
1391                         uart0_cts: uart0-cts {
1392                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1393                         };
1394
1395                         uart0_rts: uart0-rts {
1396                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398                 };
1399
1400                 uart1 {
1401                         uart1_xfer: uart1-xfer {
1402                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1403                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1404                         };
1405
1406                         uart1_cts: uart1-cts {
1407                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1408                         };
1409
1410                         uart1_rts: uart1-rts {
1411                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1412                         };
1413                 };
1414
1415                 uart2 {
1416                         uart2_xfer: uart2-xfer {
1417                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1418                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1419                         };
1420                         /* no rts / cts for uart2 */
1421                 };
1422
1423                 uart3 {
1424                         uart3_xfer: uart3-xfer {
1425                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1426                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428
1429                         uart3_cts: uart3-cts {
1430                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1431                         };
1432
1433                         uart3_rts: uart3-rts {
1434                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1435                         };
1436                 };
1437
1438                 uart4 {
1439                         uart4_xfer: uart4-xfer {
1440                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1441                                                 <5 13 3 &pcfg_pull_none>;
1442                         };
1443
1444                         uart4_cts: uart4-cts {
1445                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1446                         };
1447
1448                         uart4_rts: uart4-rts {
1449                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1450                         };
1451                 };
1452
1453                 tsadc {
1454                         otp_gpio: otp-gpio {
1455                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1456                         };
1457
1458                         otp_out: otp-out {
1459                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1460                         };
1461                 };
1462
1463                 pwm0 {
1464                         pwm0_pin: pwm0-pin {
1465                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 pwm1 {
1470                         pwm1_pin: pwm1-pin {
1471                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 pwm2 {
1476                         pwm2_pin: pwm2-pin {
1477                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1478                         };
1479                 };
1480
1481                 pwm3 {
1482                         pwm3_pin: pwm3-pin {
1483                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1484                         };
1485                 };
1486
1487                 gmac {
1488                         rgmii_pins: rgmii-pins {
1489                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1490                                                 <3 31 3 &pcfg_pull_none>,
1491                                                 <3 26 3 &pcfg_pull_none>,
1492                                                 <3 27 3 &pcfg_pull_none>,
1493                                                 <3 28 3 &pcfg_pull_none_12ma>,
1494                                                 <3 29 3 &pcfg_pull_none_12ma>,
1495                                                 <3 24 3 &pcfg_pull_none_12ma>,
1496                                                 <3 25 3 &pcfg_pull_none_12ma>,
1497                                                 <4 0 3 &pcfg_pull_none>,
1498                                                 <4 5 3 &pcfg_pull_none>,
1499                                                 <4 6 3 &pcfg_pull_none>,
1500                                                 <4 9 3 &pcfg_pull_none_12ma>,
1501                                                 <4 4 3 &pcfg_pull_none_12ma>,
1502                                                 <4 1 3 &pcfg_pull_none>,
1503                                                 <4 3 3 &pcfg_pull_none>;
1504                         };
1505
1506                         rmii_pins: rmii-pins {
1507                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1508                                                 <3 31 3 &pcfg_pull_none>,
1509                                                 <3 28 3 &pcfg_pull_none>,
1510                                                 <3 29 3 &pcfg_pull_none>,
1511                                                 <4 0 3 &pcfg_pull_none>,
1512                                                 <4 5 3 &pcfg_pull_none>,
1513                                                 <4 4 3 &pcfg_pull_none>,
1514                                                 <4 1 3 &pcfg_pull_none>,
1515                                                 <4 2 3 &pcfg_pull_none>,
1516                                                 <4 3 3 &pcfg_pull_none>;
1517                         };
1518                 };
1519
1520                 spdif {
1521                         spdif_tx: spdif-tx {
1522                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1523                         };
1524                 };
1525         };
1526 };