arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x500>;
  45                 };
  46                 cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x501>;
  50                 };
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <0x502>;
  55                 };
  56                 cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x503>;
  60                 };
  61         };
  62
  63         gic: interrupt-controller@ffc01000 {
  64                 compatible = "arm,cortex-a15-gic";
  65                 interrupt-controller;
  66                 #interrupt-cells = <3>;
  67                 #address-cells = <0>;
  68                 reg = <0xffc01000 0x1000>,
  69                       <0xffc02000 0x1000>;
  70         };
  71
  72         cpu_axi_bus: cpu_axi_bus {
  73                 compatible = "rockchip,cpu_axi_bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77                 qos {
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges;
  81                         /* service core */
  82                         cpup {
  83                                 reg = <0xffa80000 0x20>;
  84                         };
  85                         cpum_r {
  86                                 reg = <0xffa80080 0x20>;
  87                         };
  88                         cpum_w {
  89                                 reg = <0xffa80100 0x20>;
  90                         };
  91                         /* service dmac */
  92                         bus_dmac {
  93                                 reg = <0xffa90000 0x20>;
  94                         };
  95                         host {
  96                                 reg = <0xffa90080 0x20>;
  97                         };
  98                         crypto {
  99                                 reg = <0xffa90100 0x20>;
 100                         };
 101                         ccp {
 102                                 reg = <0xffa90180 0x20>;
 103                         };
 104                         ccs {
 105                                 reg = <0xffa90200 0x20>;
 106                         };
 107                         /* service gpu */
 108                         gpu_r {
 109                                 reg = <0xffaa0000 0x20>;
 110                         };
 111                         gpu_w {
 112                                 reg = <0xffaa0080 0x20>;
 113                         };
 114                         /* service peri */
 115                         peri {
 116                                 reg = <0xffab0000 0x20>;
 117                         };
 118                         /* service vio */
 119                         vio1_vop {
 120                                 reg = <0xffad0000 0x20>;
 121                                 rockchip,priority = <2 2>;
 122                         };
 123                         vio1_isp_w0 {
 124                                 reg = <0xffad0100 0x20>;
 125                         };
 126                         vio1_isp_w1 {
 127                                 reg = <0xffad0180 0x20>;
 128                         };
 129                         vio0_vop {
 130                                 reg = <0xffad0400 0x20>;
 131                                 rockchip,priority = <2 2>;
 132                         };
 133                         vio0_vip {
 134                                 reg = <0xffad0480 0x20>;
 135                         };
 136                         vio0_iep {
 137                                 reg = <0xffad0500 0x20>;
 138                         };
 139                         vio2_rga_r {
 140                                 reg = <0xffad0800 0x20>;
 141                         };
 142                         vio2_rga_w {
 143                                 reg = <0xffad0880 0x20>;
 144                         };
 145                         vio1_isp_r {
 146                                 reg = <0xffad0900 0x20>;
 147                         };
 148                         /* service video */
 149                         video {
 150                                 reg = <0xffae0000 0x20>;
 151                         };
 152                         /* service hevc */
 153                         hevc_r {
 154                                 reg = <0xffaf0000 0x20>;
 155                         };
 156                         hevc_w {
 157                                 reg = <0xffaf0080 0x20>;
 158                         };
 159                 };
 160                 msch {
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges;
 164                         msch@0 {
 165                                 reg = <0xffac0000 0x40>;
 166                                 rockchip,read-latency = <0xff>;
 167                         };
 168                         msch@1 {
 169                                 reg = <0xffac0080 0x40>;
 170                                 rockchip,read-latency = <0xff>;
 171                         };
 172                 };
 173         };
 174
 175         sram: sram@ff710000 {
 176                 compatible = "mmio-sram";
 177                 reg = <0xff710000 0x8000>; /* 32k */
 178                 map-exec;
 179         };
 180
 181         timer {
 182                 compatible = "arm,armv7-timer";
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 185                 clock-frequency = <24000000>;
 186         };
 187
 188         timer@ff810000 {
 189                 compatible = "rockchip,timer";
 190                 reg = <0xff810000 0x20>;
 191                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 192                 rockchip,broadcast = <1>;
 193         };
 194
 195         watchdog:wdt@2004c000 {
 196                 compatible = "rockchip,watch dog";
 197                 reg = <0xff800000 0x100>;
 198                 clocks = <&pclk_pd_alive>;
 199                 clock-names = "pclk_wdt";
 200                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,irq = <0>;
 202                 rockchip,timeout = <60>;
 203                 rockchip,atboot = <1>;
 204                 rockchip,debug = <0>;
 205                 status = "disable";
 206         };
 207
 208     amba {
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 compatible = "arm,amba-bus";
 212                 interrupt-parent = <&gic>;
 213                 ranges;
 214
 215                 pdma0: pdma@ffb20000 {
 216                         compatible = "arm,pl330", "arm,primecell";
 217                         reg = <0xffb20000 0x4000>;
 218                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 220                         #dma-cells = <1>;
 221                 };
 222
 223                 pdma1: pdma@ff250000 {
 224                         compatible = "arm,pl330", "arm,primecell";
 225                         reg = <0xff250000 0x4000>;
 226                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 228                         #dma-cells = <1>;
 229                 };
 230         };
 231
 232
 233         nandc0: nandc@0xff400000 {
 234                 compatible = "rockchip,rk-nandc";
 235                 reg = <0xff400000 0x4000>;
 236                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;/*irq=70*/
 237                 nandc_id = <0>;
 238                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 239                 clock-names = "clk_nandc", "g_clk_nandc","hclk_nandc";
 240                 status = "okay";
 241         };
 242
 243         nandc1: nandc@0xff410000 {
 244             compatible = "rockchip,rk-nandc";
 245                 reg = <0xff410000 0x4000>;
 246                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /*irq=72*/
 247                 nandc_id = <1>;
 248                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 249                 clock-names = "clk_nandc","g_clk_nandc","hclk_nandc";
 250                 status = "okay";
 251         };
 252
 253         emmc: rksdmmc@ff0f0000 {
 254                 compatible = "rockchip,rk_mmc";
 255                 reg = <0xff0f0000 0x4000>;
 256                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 //pinctrl-names = "default",,"suspend";
 260                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 261
 262                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 263                 clock-names = "clk_mmc", "hclk_mmc";
 264                 num-slots = <1>;
 265                 fifo-depth = <0x100>;
 266                 bus-width = <8>;
 267         };
 268
 269         sdmmc: rksdmmc@ff0c0000 {
 270           compatible = "rockchip,rk_mmc";
 271                 reg = <0xff0c0000 0x4000>;
 272                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 273           #address-cells = <1>;
 274           #size-cells = <0>;
 275
 276                 pinctrl-names = "default","idle";
 277           pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 278           pinctrl-1 = <&sdmmc0_gpio>;
 279
 280                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 281                 clock-names = "clk_mmc", "hclk_mmc";
 282         num-slots = <1>;
 283           fifo-depth = <0x100>;
 284           bus-width = <4>;
 285
 286         };
 287
 288         sdio: rksdmmc@ff0d0000 {
 289                 compatible = "rockchip,rk_mmc";
 290           reg = <0xff0d0000 0x4000>;
 291           interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 292           #address-cells = <1>;
 293           #size-cells = <0>;
 294           pinctrl-names = "default","idle";
 295           pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 296                                          &sdio0_intn &sdio0_bus4>;
 297           pinctrl-1 = <&sdio0_gpio>;
 298
 299                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 300                 clock-names = "clk_mmc", "hclk_mmc";
 301     num-slots = <1>;
 302
 303           fifo-depth = <0x100>;
 304           bus-width = <4>;
 305         };
 306
 307         sdio1: rksdmmc@ff0e0000 {
 308                 compatible = "rockchip,rk_mmc";
 309                 reg = <0xff0e0000 0x4000>;
 310                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313                 //pinctrl-names = "default","suspend";
 314                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 315
 316                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 317                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 318                 clock-names = "clk_mmc", "hclk_mmc";
 319                 num-slots = <1>;
 320
 321                 fifo-depth = <0x100>;
 322                 bus-width = <4>;
 323                 status = "disabled";
 324         };
 325
 326         spi0: spi@ff110000 {
 327                 compatible = "rockchip,rockchip-spi";
 328                 reg = <0xff110000 0x1000>;
 329                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 334                 rockchip,spi-src-clk = <0>;
 335                 num-cs = <2>;
 336                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 337                 clock-names = "spi","pclk_spi0";
 338                 //dmas = <&pdma1 11>, <&pdma1 12>;
 339                 //#dma-cells = <2>;
 340                 //dma-names = "tx", "rx";
 341                 status = "disabled";
 342         };
 343
 344         spi1: spi@ff120000 {
 345                 compatible = "rockchip,rockchip-spi";
 346                 reg = <0xff120000 0x1000>;
 347                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 352                 rockchip,spi-src-clk = <1>;
 353                 num-cs = <1>;
 354                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 355                 clock-names = "spi","pclk_spi1";
 356                 //dmas = <&pdma1 13>, <&pdma1 14>;
 357                 //#dma-cells = <2>;
 358                 //dma-names = "tx", "rx";
 359                 status = "disabled";
 360         };
 361
 362         spi2: spi@ff130000 {
 363                 compatible = "rockchip,rockchip-spi";
 364                 reg = <0xff130000 0x1000>;
 365                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 370                 rockchip,spi-src-clk = <2>;
 371                 num-cs = <2>;
 372                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 373                 clock-names = "spi","pclk_spi2";
 374                 //dmas = <&pdma1 15>, <&pdma1 16>;
 375                 //#dma-cells = <2>;
 376                 //dma-names = "tx", "rx";
 377                 status = "disabled";
 378         };
 379
 380         uart_bt: serial@ff180000 {
 381                 compatible = "rockchip,serial";
 382                 reg = <0xff180000 0x100>;
 383                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 384                 clock-frequency = <24000000>;
 385                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 386                 clock-names = "sclk_uart", "pclk_uart";
 387                 reg-shift = <2>;
 388                 reg-io-width = <4>;
 389                 dmas = <&pdma1 1>, <&pdma1 2>;
 390                 #dma-cells = <2>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 393                 status = "disabled";
 394         };
 395
 396         uart_bb: serial@ff190000 {
 397                 compatible = "rockchip,serial";
 398                 reg = <0xff190000 0x100>;
 399                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 400                 clock-frequency = <24000000>;
 401                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 402                 clock-names = "sclk_uart", "pclk_uart";
 403                 reg-shift = <2>;
 404                 reg-io-width = <4>;
 405                 dmas = <&pdma1 3>, <&pdma1 4>;
 406                 #dma-cells = <2>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 409                 status = "disabled";
 410         };
 411
 412         uart_dbg: serial@ff690000 {
 413                 compatible = "rockchip,serial";
 414                 reg = <0xff690000 0x100>;
 415                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 416                 clock-frequency = <24000000>;
 417                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 418                 clock-names = "sclk_uart", "pclk_uart";
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 dmas = <&pdma0 4>, <&pdma0 5>;
 422                 #dma-cells = <2>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&uart2_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         uart_gps: serial@ff1b0000 {
 429                 compatible = "rockchip,serial";
 430                 reg = <0xff1b0000 0x100>;
 431                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 432                 clock-frequency = <24000000>;
 433                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 434                 clock-names = "sclk_uart", "pclk_uart";
 435                 current-speed = <115200>;
 436                 reg-shift = <2>;
 437                 reg-io-width = <4>;
 438                 dmas = <&pdma1 7>, <&pdma1 8>;
 439                 #dma-cells = <2>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 442                 status = "disabled";
 443         };
 444
 445         uart_exp: serial@ff1c0000 {
 446                 compatible = "rockchip,serial";
 447                 reg = <0xff1c0000 0x100>;
 448                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 449                 clock-frequency = <24000000>;
 450                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 451                 clock-names = "sclk_uart", "pclk_uart";
 452                 reg-shift = <2>;
 453                 reg-io-width = <4>;
 454                 dmas = <&pdma1 9>, <&pdma1 10>;
 455                 #dma-cells = <2>;
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 458                 status = "disabled";
 459         };
 460
 461         fiq-debugger {
 462                 compatible = "rockchip,fiq-debugger";
 463                 rockchip,serial-id = <2>;
 464                 rockchip,signal-irq = <106>;
 465                 rockchip,wake-irq = <0>;
 466                 status = "disabled";
 467         };
 468
 469         clocks-init{
 470                 compatible = "rockchip,clocks-init";
 471                 rockchip,clocks-init-parent =
 472                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 473                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 474                         <&clk_i2s_pll &clk_cpll>, <&usbphy_480m &otgphy2_480m>;
 475                 rockchip,clocks-init-rate =
 476                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 477                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 478                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 479                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 480                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 481                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 482                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 483                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 484                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 485                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 486                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 487                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 488                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 489                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 490                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 491                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 492         };
 493
 494         clocks-enable {
 495                 compatible = "rockchip,clocks-enable";
 496                 clocks =
 497                                 /*PD_CORE*/
 498                                 <&clk_gates0 2>, <&clk_core0>,
 499                                 <&clk_core1>, <&clk_core2>,
 500                                 <&clk_core3>, <&clk_l2ram>,
 501                                 <&aclk_core_m0>, <&aclk_core_mp>,
 502                                 <&atclk_core>, <&pclk_dbg_src>,
 503
 504                                 /*PD_BUS*/
 505                                 <&aclk_bus>, <&clk_gates0 3>,
 506                                 <&hclk_bus>, <&pclk_bus>,
 507                                 <&clk_gates13 8>, <&clk_crypto>,
 508                                 <&clk_gates0 7>,
 509
 510                                 /*TIMER*/
 511                                 <&clk_gates1 0>, <&clk_gates1 1>,
 512                                 <&clk_gates1 2>, <&clk_gates1 3>,
 513                                 <&clk_gates1 4>, <&clk_gates1 5>,
 514
 515                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 516
 517                                 /*PD_PERI*/
 518                                 <&aclk_peri>, <&hclk_peri>,
 519                                 <&pclk_peri>,
 520
 521                                 /*JTAG*/
 522                                 /*<&clk_gates4 14>,*/
 523
 524                                 /*aclk_bus*/
 525                                 <&clk_gates10 5>,/*aclk_intmem0*/
 526                                 <&clk_gates10 6>,/*aclk_intmem1*/
 527                                 <&clk_gates10 7>,/*aclk_intmem2*/
 528                                 <&clk_gates10 12>,/*aclk_dma1*/
 529                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 530                                 <&clk_gates10 4>,/*aclk_intmem*/
 531                                 <&clk_gates11 6>,/*aclk_crypto*/
 532                                 <&clk_gates11 8>,/*aclk_ccp*/
 533
 534                                 /*hclk_bus*/
 535                                 <&clk_gates11 7>,/*hclk_crypto*/
 536                                 <&clk_gates10 9>,/*hclk_rom*/
 537
 538                                 /*pclk_bus*/
 539                                 <&clk_gates10 1>,/*pclk_timer*/
 540                                 <&clk_gates10 9>,/*rom*/
 541                                 <&clk_gates10 13>,/*aclk strc*/
 542
 543                                 <&clk_gates12 8>,/*aclk strc*/
 544
 545                                 /*aclk_peri*/
 546                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 547                                 <&clk_gates6 3>,/*aclk_dmac2*/
 548                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 549                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 550
 551                                 /*hclk_peri*/
 552                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 553                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 554                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 555                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 556
 557                                 /*pclk_peri*/
 558                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 559
 560                                 /*pclk_pd_alive*/
 561                                 <&clk_gates14 11>,/*pclk_grf*/
 562                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 563
 564                                 /*pclk_pd_pmu*/
 565                                 <&clk_gates17 0>,/*pclk_pmu*/
 566                                 <&clk_gates17 1>,/*pclk_intmem1*/
 567                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 568                                 <&clk_gates17 3>,/*pclk_sgrf*/
 569
 570                                 /*hclk_vio*/
 571                                 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
 572                                 <&clk_gates15 10>,/*hclk_vio_niu*/
 573                                 <&clk_gates16 10>,/*hclk_vio2_h2p*/
 574                                 <&clk_gates16 11>,/*pclk_vio2_h2p*/
 575
 576                                 /*aclk_vio0*/
 577                                 <&clk_gates15 11>,/*aclk_vio0_niu*/
 578
 579                                 /*aclk_vio1*/
 580                                 <&clk_gates15 12>,/*aclk_vio1_niu*/
 581
 582                                 /*HDMI*/
 583                                 <&clk_gates5 12>,/*hdmi_hdcp_clk*/
 584
 585                                 /*UART*/
 586                                 <&clk_gates11 9>,/*pclk_uart2*/
 587
 588                                 /*480M*/
 589                                 <&usbphy_480m>,
 590
 591                                 /*PD*/
 592                                 <&pd_gpu>,
 593                                 <&pd_video>,
 594                                 <&pd_vio>,
 595                                 <&pd_hevc>;
 596         };
 597
 598         i2c0: i2c@ff650000 {
 599                 compatible = "rockchip,rk30-i2c";
 600                 reg = <0xff650000 0x1000>;
 601                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 pinctrl-names = "default", "gpio";
 605                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 606                 pinctrl-1 = <&i2c0_gpio>;
 607                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 608                 clocks = <&clk_gates10 2>;
 609                 rockchip,check-idle = <1>;
 610                 status = "disabled";
 611         };
 612
 613         i2c1: i2c@ff140000 {
 614                 compatible = "rockchip,rk30-i2c";
 615                 reg = <0xff140000 0x1000>;
 616                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 pinctrl-names = "default", "gpio";
 620                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 621                 pinctrl-1 = <&i2c1_gpio>;
 622                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 623                 clocks = <&clk_gates10 3>;
 624                 rockchip,check-idle = <1>;
 625                 status = "disabled";
 626         };
 627
 628         i2c2: i2c@ff660000 {
 629                 compatible = "rockchip,rk30-i2c";
 630                 reg = <0xff660000 0x1000>;
 631                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 pinctrl-names = "default", "gpio";
 635                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 636                 pinctrl-1 = <&i2c2_gpio>;
 637                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 638                 clocks = <&clk_gates6 13>;
 639                 rockchip,check-idle = <1>;
 640                 status = "disabled";
 641         };
 642
 643         i2c3: i2c@ff150000 {
 644                 compatible = "rockchip,rk30-i2c";
 645                 reg = <0xff150000 0x1000>;
 646                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 647                 #address-cells = <1>;
 648                 #size-cells = <0>;
 649                 pinctrl-names = "default", "gpio";
 650                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 651                 pinctrl-1 = <&i2c3_gpio>;
 652                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 653                 clocks = <&clk_gates6 14>;
 654                 rockchip,check-idle = <1>;
 655                 status = "disabled";
 656         };
 657
 658         i2c4: i2c@ff160000 {
 659                 compatible = "rockchip,rk30-i2c";
 660                 reg = <0xff160000 0x1000>;
 661                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 pinctrl-names = "default", "gpio";
 665                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 666                 pinctrl-1 = <&i2c4_gpio>;
 667                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 668                 clocks = <&clk_gates6 15>;
 669                 rockchip,check-idle = <1>;
 670                 status = "disabled";
 671         };
 672
 673         i2c5: i2c@ff170000 {
 674                 compatible = "rockchip,rk30-i2c";
 675                 reg = <0xff170000 0x1000>;
 676                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 677                 #address-cells = <1>;
 678                 #size-cells = <0>;
 679                 pinctrl-names = "default", "gpio";
 680                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 681                 pinctrl-1 = <&i2c5_gpio>;
 682                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 683                 clocks = <&clk_gates7 0>;
 684                 rockchip,check-idle = <1>;
 685                 status = "disabled";
 686         };
 687
 688
 689         fb: fb{
 690                 compatible = "rockchip,rk-fb";
 691                 rockchip,disp-mode = <DUAL>;
 692         };
 693
 694         rk_screen: rk_screen{
 695                         compatible = "rockchip,screen";
 696         };
 697
 698         dsihost0: mipi@ff960000{
 699                 compatible = "rockchip,rk32-dsi";
 700                 rockchip,prop = <0>;
 701                 reg = <0xff960000 0x4000>;
 702                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 703                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 704                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 705                 status = "disabled";
 706         };
 707
 708         dsihost1: mipi@ff964000{
 709                 compatible = "rockchip,rk32-dsi";
 710                 rockchip,prop = <1>;
 711                 reg = <0xff964000 0x4000>;
 712                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 713                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 714                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 715                 status = "disabled";
 716         };
 717
 718         lvds: lvds@ff96c000 {
 719                 compatible = "rockchip,rk32-lvds";
 720                 reg = <0xff96c000 0x4000>;
 721                 clocks = <&clk_gates16 7>;
 722                 clock-names = "pclk_lvds";
 723         };
 724
 725         edp: edp@ff970000 {
 726                 compatible = "rockchip,rk32-edp";
 727                 reg = <0xff970000 0x4000>;
 728                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 730                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 731                 };
 732
 733         hdmi: hdmi@ff980000 {
 734                 compatible = "rockchip,rk3288-hdmi";
 735                 reg = <0xff980000 0x20000>;
 736                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 737                 pinctrl-names = "default", "gpio";
 738                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 739                 pinctrl-1 = <&i2c5_gpio>;
 740                 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
 741                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
 742                 status = "disabled";
 743         };
 744
 745         lcdc1: lcdc@ff940000 {
 746                 compatible = "rockchip,rk3288-lcdc";
 747                 rockchip,prop = <PRMRY>;
 748                 rochchip,pwr18 = <0>;
 749                 reg = <0xff940000 0x10000>;
 750                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 751                 pinctrl-names = "default", "gpio";
 752                 pinctrl-0 = <&lcdc0_lcdc>;
 753                 pinctrl-1 = <&lcdc0_gpio>;
 754                 status = "disabled";
 755                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
 756                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 757         };
 758
 759         lcdc0: lcdc@ff930000 {
 760                 compatible = "rockchip,rk3288-lcdc";
 761                 rockchip,prop = <EXTEND>;
 762                 rockchip,pwr18 = <0>;
 763                 reg = <0xff930000 0x10000>;
 764                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 765                 //pinctrl-names = "default", "gpio";
 766                 //pinctrl-0 = <&lcdc0_lcdc>;
 767                 //pinctrl-1 = <&lcdc0_gpio>;
 768                 status = "disabled";
 769                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
 770                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 771         };
 772
 773         adc: adc@ff100000 {
 774                 compatible = "rockchip,saradc";
 775                 reg = <0xff100000 0x100>;
 776                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 777                 #io-channel-cells = <1>;
 778                 io-channel-ranges;
 779                 rockchip,adc-vref = <1800>;
 780                 clock-frequency = <1000000>;
 781                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 782                 clock-names = "saradc", "pclk_saradc";
 783                 status = "disabled";
 784         };
 785
 786         rga@ff920000 {
 787                 compatible = "rockchip,rga";
 788                 reg = <0xff920000 0x1000>;
 789                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 790                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 791                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 792         };
 793
 794         i2s: rockchip-i2s@0xff890000 {
 795                 compatible = "rockchip-i2s";
 796                 reg = <0xff890000 0x10000>;
 797                 i2s-id = <0>;
 798                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 799                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 800                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 801                 dmas = <&pdma0 0>,
 802                         <&pdma0 1>;
 803                 //#dma-cells = <2>;
 804                 dma-names = "tx", "rx";
 805                 pinctrl-names = "default", "sleep";
 806                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 807                 pinctrl-1 = <&i2s_gpio>;
 808         };
 809
 810         spdif: rockchip-spdif@0xff8b0000 {
 811                 compatible = "rockchip-spdif";
 812                 reg = <0xff8b0000 0x10000>;     //8channel
 813                 //reg = <ff880000 0x10000>;//2channel
 814                 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
 815                 clock-names = "spdif_mclk","spdif_8ch_mclk";
 816                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 817                 dmas = <&pdma0 3>;
 818                 //dmas = <&pdma0 2>; //2channel
 819                 //#dma-cells = <1>;
 820                 dma-names = "tx";
 821                 pinctrl-names = "default";
 822                 pinctrl-0 = <&spdif_tx>;
 823         };
 824
 825         pwm0: pwm@ff680000 {
 826                 compatible = "rockchip,rk-pwm";
 827                 reg = <0xff680000 0x10>;
 828                 #pwm-cells = <2>;
 829                 pinctrl-names = "default";
 830                 pinctrl-0 = <&pwm0_pin>;
 831                 clocks = <&clk_gates11 11>;
 832                 clock-names = "pclk_pwm";
 833                 status = "okay";
 834         };
 835
 836         pwm1: pwm@ff680010 {
 837                 compatible = "rockchip,rk-pwm";
 838                 reg = <0xff680010 0x10>;
 839                 #pwm-cells = <2>;
 840                 pinctrl-names = "default";
 841                 pinctrl-0 = <&pwm1_pin>;
 842                 clocks = <&clk_gates11 11>;
 843                 clock-names = "pclk_pwm";
 844                 status = "disabled";
 845         };
 846
 847         pwm2: pwm@ff680020 {
 848                 compatible = "rockchip,rk-pwm";
 849                 reg = <0xff680020 0x10>;
 850                 #pwm-cells = <2>;
 851                 pinctrl-names = "default";
 852                 pinctrl-0 = <&pwm2_pin>;
 853                 clocks = <&clk_gates11 11>;
 854                 clock-names = "pclk_pwm";
 855                 status = "disabled";
 856         };
 857
 858         pwm3: pwm@ff680030 {
 859                 compatible = "rockchip,rk-pwm";
 860                 reg = <0xff680030 0x10>;
 861                 #pwm-cells = <2>;
 862                 pinctrl-names = "default";
 863                 pinctrl-0 = <&pwm3_pin>;
 864                 clocks = <&clk_gates11 11>;
 865                 clock-names = "pclk_pwm";
 866                 status = "disabled";
 867         };
 868         dvfs {
 869                 vd_arm:
 870                 vd_arm {
 871                         regulator_name="vdd_arm";
 872                         suspend_volt=<1000>; //mV
 873                         pd_core {
 874                                 clk_core_dvfs_table:
 875                                 clk_core {
 876                                         operating-points = <
 877                                                 /* KHz    uV */
 878                                                 312000 1100000
 879                                                 504000 1100000
 880                                                 816000 1100000
 881                                                 1008000 1100000
 882                                                 >;
 883                                         temp-channel=<1>;
 884                                         temp-limit = <
 885                                                 /*temp    freq*/
 886                                                 110     816000
 887                                                 >;
 888                                         status = "okay";
 889                                 };
 890                         };
 891                 };
 892
 893                 vd_logic:
 894                 vd_logic {
 895                         regulator_name="vdd_logic";
 896                         suspend_volt=<1000>; //mV
 897                         pd_ddr {
 898                                 clk_ddr_dvfs_table:
 899                                 clk_ddr {
 900                                         operating-points = <
 901                                                 /* KHz    uV */
 902                                                 200000 1200000
 903                                                 300000 1200000
 904                                                 400000 1200000
 905                                                 >;
 906                                         status = "disable";
 907                                 };
 908                         };
 909
 910                         pd_vpu {
 911                                 clk_ddr_vepu_table:
 912                                 clk_vepu {
 913                                         operating-points = <
 914                                                 /* KHz    uV */
 915                                                 200000 1300000
 916                                                 300000 1300000
 917                                                 400000 1300000
 918                                                 >;
 919                                         status = "disable";
 920                                 };
 921                         };
 922                 };
 923
 924                 vd_gpu:
 925                 vd_gpu {
 926                         regulator_name="vdd_gpu";
 927                         suspend_volt=<1000>; //mV
 928                         pd_gpu {
 929                                 clk_gpu_dvfs_table:
 930                                 clk_gpu {
 931                                         operating-points = <
 932                                                 /* KHz    uV */
 933                                                 200000 1200000
 934                                                 300000 1200000
 935                                                 400000 1200000
 936                                                 >;
 937                                         //temp-channel=<2>;
 938                                         temp-limit = <
 939                                                 /*temp    freq*/
 940                                                 50      600000
 941                                                 70      500000
 942                                                 80      400000
 943                                                 100     300000
 944                                                 >;
 945                                         status = "okay";
 946                                 };
 947                         };
 948                 };
 949         };
 950
 951         ion {
 952                 compatible = "rockchip,ion";
 953                 #address-cells = <1>;
 954                 #size-cells = <0>;
 955                 rockchip,ion-heap@1 { /* CMA HEAP */
 956                         compatible = "rockchip,ion-reserve";
 957                         reg = <1>;
 958                         memory-reservation = <0x00000000 0x18000000>; /* 384MB */
 959                 };
 960                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 961                         reg = <3>;
 962                 };
 963         };
 964
 965
 966         vpu: vpu_service@ff9a0000 {
 967                 compatible = "vpu_service";
 968                 reg = <0xff9a0000 0x800>;
 969                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 970                 interrupt-names = "irq_enc", "irq_dec";
 971                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 972                 clock-names = "aclk_vcodec", "hclk_vcodec";
 973                 name = "vpu_service";
 974                 //status = "disabled";
 975         };
 976
 977         hevc: hevc_service@ff9c0000 {
 978                 compatible = "rockchip,hevc_service";
 979                 reg = <0xff9c0000 0x800>;
 980                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 981                 interrupt-names = "irq_dec";
 982                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 983                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 984                 name = "hevc_service";
 985                 //status = "disabled";
 986         };
 987
 988         iep: iep@ff900000 {
 989                 compatible = "rockchip,iep";
 990                 reg = <0xff900000 0x800>;
 991                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 992                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 993                 clock-names = "aclk_iep", "hclk_iep";
 994                 status = "okay";
 995         };
 996
 997         dwc_control_usb: dwc-control-usb@ff770284 {
 998                 compatible = "rockchip,rk3288-dwc-control-usb";
 999                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1000                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1001                       <0xff770320 0x14>, <0xff770334 0x14>,
1002                       <0xff770348 0x10>, <0xff770358 0x08>,
1003                       <0xff770360 0x08>;
1004                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1005                     "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1006                     "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1007                     "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1008                     "GRF_UOC4_BASE";
1009                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1010                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1011                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1012                 interrupt-names = "otg_id", "otg_bvalid",
1013                           "otg_linestate", "host0_linestate",
1014                           "host1_linestate";
1015                 gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,/*HOST_VBUS_DRV*/
1016                         <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;/*OTG_VBUS_DRV*/
1017                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1018                  <&otgphy1_480m>, <&otgphy2_480m>;
1019                 clock-names = "hclk_usb_peri", "usbphy_480m",
1020                       "usbphy1_480m", "usbphy2_480m";
1021                 rockchip,remote_wakeup;
1022                 rockchip,usb_irq_wakeup;
1023
1024                 usb_bc{
1025                         compatible = "synopsys,phy";
1026                                         /* offset bit mask */
1027                         rk_usb,bvalid     = <0x288 14 1>;
1028                         rk_usb,dcdenb     = <0x328 14 1>;
1029                         rk_usb,vdatsrcenb = <0x328  7 1>;
1030                         rk_usb,vdatdetenb = <0x328  6 1>;
1031                         rk_usb,chrgsel    = <0x328  5 1>;
1032                         rk_usb,chgdet     = <0x2cc 23 1>;
1033                         rk_usb,fsvminus   = <0x2cc 25 1>;
1034                         rk_usb,fsvplus    = <0x2cc 24 1>;
1035                 };
1036         };
1037
1038         usb0: usb@ff580000 {
1039                 compatible = "rockchip,rk3288_usb20_otg";
1040                 reg = <0xff580000 0x40000>;
1041                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1042                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1043                 clock-names = "clk_usbphy0", "hclk_usb0";
1044                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1045                 rockchip,usb-mode = <0>;
1046         };
1047
1048         usb1: usb@ff540000 {
1049                 compatible = "rockchip,rk3288_usb20_host";
1050                 reg = <0xff540000 0x40000>;
1051                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1052                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1053                          <&usbphy_480m>;
1054                 clock-names = "clk_usbphy1", "hclk_usb1",
1055                               "usbphy_480m";
1056         };
1057
1058         usb2: usb@ff500000 {
1059                 compatible = "rockchip,rk3288_rk_ehci_host";
1060                 reg = <0xff500000 0x20000>;
1061                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1062                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1063                 clock-names = "clk_usbphy2", "hclk_usb2";
1064         };
1065
1066         usb3: usb@ff520000 {
1067                 compatible = "rockchip,rk3288_rk_ohci_host";
1068                 reg = <0xff520000 0x20000>;
1069                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1070                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1071                 clock-names = "clk_usbphy3", "hclk_usb3";
1072         };
1073
1074         hsic: hsic@ff5c0000 {
1075                 compatible = "rockchip,rk3288_rk_hsic_host";
1076                 reg = <0xff5c0000 0x40000>;
1077                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1078                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1079                          <&hsicphy_12m>, <&usbphy_480m>,
1080                          <&otgphy1_480m>, <&otgphy2_480m>;
1081                 clock-names = "hsicphy_480m", "hclk_hsic",
1082                               "hsicphy_12m", "usbphy_480m",
1083                               "hsic_usbphy1", "hsic_usbphy2";
1084         };
1085
1086         gmac: eth@ff290000 {
1087                 compatible = "rockchip,gmac";
1088                 reg = <0xff290000 0x10000>;
1089                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1090                 interrupt-names = "macirq";
1091                 //phy-mode = "rmii";
1092                 phy-mode = "rgmii";
1093                 pinctrl-names = "default";
1094                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1095         };
1096     gpu{
1097         compatible = "arm,malit764",
1098                      "arm,malit76x",
1099                      "arm,malit7xx",
1100                      "arm,mali-midgard";
1101         reg = <0xffa30000 0x10000>;
1102         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1103                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1104                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1105         interrupt-names = "JOB",
1106                           "MMU",
1107                           "GPU";
1108     };
1109
1110     iep_mmu{
1111         dbgname = "iep";
1112         compatible = "iommu,iep_mmu";
1113         reg = <0xff900800 0x100>;
1114         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1115         interrupt-names = "iep_mmu";
1116     };
1117
1118     vip_mmu{
1119         dbgname = "vip";
1120         compatible = "iommu,vip_mmu";
1121         reg = <0xff950800 0x100>;
1122         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1123         interrupt-names = "vip_mmu";
1124     };
1125     vopb_mmu{
1126         dbgname = "vopb";
1127         compatible = "iommu,vopb_mmu";
1128         reg = <0xff930300 0x100>;
1129         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1130         interrupt-names = "vopb_mmu";
1131     };
1132
1133     vopl_mmu{
1134         dbgname = "vopl";
1135         compatible = "iommu,vopl_mmu";
1136         reg = <0xff940300 0x100>;
1137         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1138         interrupt-names = "vopl_mmu";
1139     };
1140
1141     hevc_mmu{
1142         dbgname = "hevc";
1143         compatible = "iommu,hevc_mmu";
1144         reg = <0xff9c0440 0x100>,
1145                           <0xff9c0480 0x100>;
1146         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1147         interrupt-names = "hevc_mmu";
1148     };
1149
1150                 vpu_mmu{
1151         dbgname = "vpu";
1152         compatible = "iommu,vpu_mmu";
1153         reg = <0xff9a0800 0x100>;
1154         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1155         interrupt-names = "vpu_mmu";
1156     };
1157
1158         isp_mmu{
1159        dbgname = "isp_mmu";
1160        compatible = "iommu,isp_mmu";
1161        reg = <0xff914000 0x100>,
1162                          <0xff915000 0x100>;
1163        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1164        interrupt-names = "isp_mmu";
1165     };
1166
1167
1168     rockchip_suspend {
1169                   rockchip,ctrbits = <
1170                                             (0
1171                                             |RKPM_CTR_PWR_DMNS
1172                                             |RKPM_CTR_GTCLKS
1173                                             |RKPM_CTR_PLLS
1174                                             //|RKPM_CTR_SYSCLK_DIV
1175                                             //|RKPM_CTR_IDLEAUTO_MD
1176                                            // |RKPM_CTR_ARMOFF_LPMD
1177                                             |RKPM_CTR_ARMOFF_LOGDP_LPMD
1178                                             )
1179                                         >;
1180                   rockchip,pmic-gpios=<
1181                                                     RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1182                                                     RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1183                                                     >;
1184             };
1185
1186            isp:isp@ff910000{
1187                 compatible = "rockchip,isp";
1188                 reg = <0xff910000 0x10000>;
1189                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1190                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>,<&clk_gates5 15>,<&clk_cif_pll>,<&pd_isp>;
1191                         clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout","clk_mipi_24m","cif0_out_div","pd_isp";
1192                         pinctrl-names = "default", "isp_dvp8bit","isp_dvp10bit","isp_dvp12bit";
1193                         pinctrl-0 = <&isp_mipi>;
1194                         pinctrl-1 = <&isp_mipi &isp_dvp_sync_d2d9>;
1195                         pinctrl-2 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1>;
1196                         pinctrl-3 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1 &isp_dvpd10d11>;
1197
1198                         status = "okay";
1199         };
1200
1201         tsadc: tsadc@ff280000{
1202                         compatible = "rockchip,tsadc";
1203                         reg = <0xff280000 0x100>;
1204                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1205                         #io-channel-cells = <1>;
1206                         io-channel-ranges;
1207                         clock-frequency = <50000>;
1208                         clocks = <&clk_tsadc>, <&clk_gates7 2>;
1209                         clock-names = "tsadc", "pclk_tsadc";
1210                         status = "okay";
1211         };
1212
1213         lcdc_vdd_domain: lcdc-vdd-domain{
1214                         compatible = "rockchip,io_vol_domain";
1215                         pinctrl-names = "default", "1.8V", "3.3V";
1216                         pinctrl-0 = <&lcdc_vcc>;
1217                         pinctrl-1 = <&lcdc_vcc_18>;
1218                         pinctrl-2 = <&lcdc_vcc_33>;
1219         };
1220         dpio_vdd_domain: dpio-vdd-domain{
1221                         compatible = "rockchip,io_vol_domain";
1222                         pinctrl-names = "default", "1.8V", "3.3V";
1223                         pinctrl-0 = <&dvp_vcc>;
1224                         pinctrl-1 = <&dvp_vcc_18>;
1225                         pinctrl-2 = <&dvp_vcc_33>;
1226         };
1227         flash0_vdd_domain: flash0-vdd-domain{
1228                         compatible = "rockchip,io_vol_domain";
1229                         pinctrl-names = "default", "1.8V", "3.3V";
1230                         pinctrl-0 = <&flash0_vcc>;
1231                         pinctrl-1 = <&flash0_vcc_18>;
1232                         pinctrl-2 = <&flash0_vcc_33>;
1233         };
1234         flash1_vdd_domain: flash1-vdd-domain{
1235                         compatible = "rockchip,io_vol_domain";
1236                         pinctrl-names = "default", "1.8V", "3.3V";
1237                         pinctrl-0 = <&flash1_vcc>;
1238                         pinctrl-1 = <&flash1_vcc_18>;
1239                         pinctrl-2 = <&flash1_vcc_33>;
1240         };
1241         apio3_vdd_domain: apio3-vdd-domain{
1242                         compatible = "rockchip,io_vol_domain";
1243                         pinctrl-names = "default", "1.8V", "3.3V";
1244                         pinctrl-0 = <&wifi_vcc>;
1245                         pinctrl-1 = <&wifi_vcc_18>;
1246                         pinctrl-2 = <&wifi_vcc_33>;
1247         };
1248         apio5_vdd_domain: apio5-vdd-domain{
1249                         compatible = "rockchip,io_vol_domain";
1250                         pinctrl-names = "default", "1.8V", "3.3V";
1251                         pinctrl-0 = <&bb_vcc>;
1252                         pinctrl-1 = <&bb_vcc_18>;
1253                         pinctrl-2 = <&bb_vcc_33>;
1254         };
1255         apio4_vdd_domain: apio4-vdd-domain{
1256                         compatible = "rockchip,io_vol_domain";
1257                         pinctrl-names = "default", "1.8V", "3.3V";
1258                         pinctrl-0 = <&audio_vcc>;
1259                         pinctrl-1 = <&audio_vcc_18>;
1260                         pinctrl-2 = <&audio_vcc_33>;
1261         };
1262         apio1_vdd_domain: apio0-vdd-domain{
1263                         compatible = "rockchip,io_vol_domain";
1264                         pinctrl-names = "default", "1.8V", "3.3V";
1265                         pinctrl-0 = <&gpio30_vcc>;
1266                         pinctrl-1 = <&gpio30_vcc_18>;
1267                         pinctrl-2 = <&gpio30_vcc_33>;
1268         };
1269         apio2_vdd_domain: apio2-vdd-domain{
1270                         compatible = "rockchip,io_vol_domain";
1271                         pinctrl-names = "default", "1.8V", "3.3V";
1272                         pinctrl-0 = <&gpio1830_vcc>;
1273                         pinctrl-1 = <&gpio1830_vcc_18>;
1274                         pinctrl-2 = <&gpio1830_vcc_33>;
1275         };
1276         sdmmc0_vdd_domain: sdmmc0-vdd-domain{
1277                         compatible = "rockchip,io_vol_domain";
1278                         pinctrl-names = "default", "1.8V", "3.3V";
1279                         pinctrl-0 = <&sdcard_vcc>;
1280                         pinctrl-1 = <&sdcard_vcc_18>;
1281                         pinctrl-2 = <&sdcard_vcc_33>;
1282         };
1283
1284 };