2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
79 compatible = "arm,cortex-a12-pmu";
80 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
90 enable-method = "rockchip,rk3066-smp";
91 rockchip,pmu = <&pmu>;
95 compatible = "arm,cortex-a12";
97 resets = <&cru SRST_CORE0>;
98 operating-points-v2 = <&cpu0_opp_table>;
99 #cooling-cells = <2>; /* min followed by max */
100 clocks = <&cru ARMCLK>;
104 compatible = "arm,cortex-a12";
106 resets = <&cru SRST_CORE1>;
107 operating-points-v2 = <&cpu0_opp_table>;
111 compatible = "arm,cortex-a12";
113 resets = <&cru SRST_CORE2>;
114 operating-points-v2 = <&cpu0_opp_table>;
118 compatible = "arm,cortex-a12";
120 resets = <&cru SRST_CORE3>;
121 operating-points-v2 = <&cpu0_opp_table>;
125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
130 opp-hz = /bits/ 64 <126000000>;
131 opp-microvolt = <900000>;
132 clock-latency-ns = <40000>;
135 opp-hz = /bits/ 64 <216000000>;
136 opp-microvolt = <900000>;
137 clock-latency-ns = <40000>;
140 opp-hz = /bits/ 64 <408000000>;
141 opp-microvolt = <900000>;
142 clock-latency-ns = <40000>;
145 opp-hz = /bits/ 64 <600000000>;
146 opp-microvolt = <900000>;
147 clock-latency-ns = <40000>;
150 opp-hz = /bits/ 64 <696000000>;
151 opp-microvolt = <950000>;
152 clock-latency-ns = <40000>;
155 opp-hz = /bits/ 64 <816000000>;
156 opp-microvolt = <1000000>;
157 clock-latency-ns = <40000>;
161 opp-hz = /bits/ 64 <1008000000>;
162 opp-microvolt = <1050000>;
163 clock-latency-ns = <40000>;
166 opp-hz = /bits/ 64 <1200000000>;
167 opp-microvolt = <1100000>;
168 clock-latency-ns = <40000>;
171 opp-hz = /bits/ 64 <1416000000>;
172 opp-microvolt = <1200000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <1512000000>;
177 opp-microvolt = <1300000>;
178 clock-latency-ns = <40000>;
181 opp-hz = /bits/ 64 <1608000000>;
182 opp-microvolt = <1350000>;
183 clock-latency-ns = <40000>;
190 min-volt = <900000>; /* uV */
191 min-freq = <126000>; /* KHz */
192 leakage-adjust-volt = <
196 nvmem-cells = <&cpu_leakage>;
197 nvmem-cell-names = "cpu_leakage";
202 compatible = "arm,amba-bus";
203 #address-cells = <1>;
207 dmac_peri: dma-controller@ff250000 {
208 compatible = "arm,pl330", "arm,primecell";
209 reg = <0xff250000 0x4000>;
210 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
213 arm,pl330-broken-no-flushp;
214 peripherals-req-type-burst;
215 clocks = <&cru ACLK_DMAC2>;
216 clock-names = "apb_pclk";
219 dmac_bus_ns: dma-controller@ff600000 {
220 compatible = "arm,pl330", "arm,primecell";
221 reg = <0xff600000 0x4000>;
222 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
225 arm,pl330-broken-no-flushp;
226 peripherals-req-type-burst;
227 clocks = <&cru ACLK_DMAC1>;
228 clock-names = "apb_pclk";
232 dmac_bus_s: dma-controller@ffb20000 {
233 compatible = "arm,pl330", "arm,primecell";
234 reg = <0xffb20000 0x4000>;
235 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
238 arm,pl330-broken-no-flushp;
239 peripherals-req-type-burst;
240 clocks = <&cru ACLK_DMAC1>;
241 clock-names = "apb_pclk";
246 #address-cells = <1>;
251 * The rk3288 cannot use the memory area above 0xfe000000
252 * for dma operations for some reason. While there is
253 * probably a better solution available somewhere, we
254 * haven't found it yet and while devices with 2GB of ram
255 * are not affected, this issue prevents 4GB from booting.
256 * So to make these devices at least bootable, block
257 * this area for the time being until the real solution
260 dma-unusable@fe000000 {
261 reg = <0xfe000000 0x1000000>;
266 compatible = "fixed-clock";
267 clock-frequency = <24000000>;
268 clock-output-names = "xin24m";
273 compatible = "arm,armv7-timer";
274 arm,cpu-registers-not-fw-configured;
275 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
276 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
277 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
278 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
279 clock-frequency = <24000000>;
282 timer: timer@ff810000 {
283 compatible = "rockchip,rk3288-timer";
284 reg = <0xff810000 0x20>;
285 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&xin24m>, <&cru PCLK_TIMER>;
287 clock-names = "timer", "pclk";
291 compatible = "rockchip,display-subsystem";
292 ports = <&vopl_out>, <&vopb_out>;
295 sdmmc: dwmmc@ff0c0000 {
296 compatible = "rockchip,rk3288-dw-mshc";
297 clock-freq-min-max = <400000 150000000>;
298 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
299 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
300 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
301 fifo-depth = <0x100>;
302 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
303 reg = <0xff0c0000 0x4000>;
307 sdio0: dwmmc@ff0d0000 {
308 compatible = "rockchip,rk3288-dw-mshc";
309 clock-freq-min-max = <400000 150000000>;
310 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
311 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
312 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
313 fifo-depth = <0x100>;
314 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
315 reg = <0xff0d0000 0x4000>;
319 sdio1: dwmmc@ff0e0000 {
320 compatible = "rockchip,rk3288-dw-mshc";
321 clock-freq-min-max = <400000 150000000>;
322 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
323 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
324 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
325 fifo-depth = <0x100>;
326 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
327 reg = <0xff0e0000 0x4000>;
331 emmc: dwmmc@ff0f0000 {
332 compatible = "rockchip,rk3288-dw-mshc";
333 clock-freq-min-max = <400000 150000000>;
334 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
335 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
336 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
337 fifo-depth = <0x100>;
338 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
339 reg = <0xff0f0000 0x4000>;
344 saradc: saradc@ff100000 {
345 compatible = "rockchip,saradc";
346 reg = <0xff100000 0x100>;
347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
348 #io-channel-cells = <1>;
349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
350 clock-names = "saradc", "apb_pclk";
351 resets = <&cru SRST_SARADC>;
352 reset-names = "saradc-apb";
357 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
358 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
359 clock-names = "spiclk", "apb_pclk";
360 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
361 dma-names = "tx", "rx";
362 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
365 reg = <0xff110000 0x1000>;
366 #address-cells = <1>;
372 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
373 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
374 clock-names = "spiclk", "apb_pclk";
375 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
376 dma-names = "tx", "rx";
377 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
380 reg = <0xff120000 0x1000>;
381 #address-cells = <1>;
387 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
388 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
389 clock-names = "spiclk", "apb_pclk";
390 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
391 dma-names = "tx", "rx";
392 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
395 reg = <0xff130000 0x1000>;
396 #address-cells = <1>;
402 compatible = "rockchip,rk3288-i2c";
403 reg = <0xff140000 0x1000>;
404 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
405 #address-cells = <1>;
408 clocks = <&cru PCLK_I2C1>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c1_xfer>;
415 compatible = "rockchip,rk3288-i2c";
416 reg = <0xff150000 0x1000>;
417 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
421 clocks = <&cru PCLK_I2C3>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c3_xfer>;
428 compatible = "rockchip,rk3288-i2c";
429 reg = <0xff160000 0x1000>;
430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
434 clocks = <&cru PCLK_I2C4>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c4_xfer>;
441 compatible = "rockchip,rk3288-i2c";
442 reg = <0xff170000 0x1000>;
443 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
447 clocks = <&cru PCLK_I2C5>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&i2c5_xfer>;
453 uart0: serial@ff180000 {
454 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
455 reg = <0xff180000 0x100>;
456 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
460 clock-names = "baudclk", "apb_pclk";
461 pinctrl-names = "default";
462 pinctrl-0 = <&uart0_xfer>;
466 uart1: serial@ff190000 {
467 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
468 reg = <0xff190000 0x100>;
469 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
473 clock-names = "baudclk", "apb_pclk";
474 pinctrl-names = "default";
475 pinctrl-0 = <&uart1_xfer>;
479 uart2: serial@ff690000 {
480 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
481 reg = <0xff690000 0x100>;
482 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
486 clock-names = "baudclk", "apb_pclk";
487 pinctrl-names = "default";
488 pinctrl-0 = <&uart2_xfer>;
492 uart3: serial@ff1b0000 {
493 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
494 reg = <0xff1b0000 0x100>;
495 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
499 clock-names = "baudclk", "apb_pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart3_xfer>;
505 uart4: serial@ff1c0000 {
506 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
507 reg = <0xff1c0000 0x100>;
508 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
512 clock-names = "baudclk", "apb_pclk";
513 pinctrl-names = "default";
514 pinctrl-0 = <&uart4_xfer>;
519 reserve_thermal: reserve_thermal {
520 polling-delay-passive = <1000>; /* milliseconds */
521 polling-delay = <5000>; /* milliseconds */
523 thermal-sensors = <&tsadc 0>;
526 cpu_thermal: cpu_thermal {
527 polling-delay-passive = <250>; /* milliseconds */
528 polling-delay = <5000>; /* milliseconds */
530 thermal-sensors = <&tsadc 1>;
533 cpu_alert0: cpu_alert0 {
534 temperature = <70000>; /* millicelsius */
535 hysteresis = <2000>; /* millicelsius */
538 cpu_alert1: cpu_alert1 {
539 temperature = <80000>; /* millicelsius */
540 hysteresis = <2000>; /* millicelsius */
544 temperature = <90000>; /* millicelsius */
545 hysteresis = <2000>; /* millicelsius */
552 trip = <&cpu_alert0>;
554 <&cpu0 THERMAL_NO_LIMIT 6>;
557 trip = <&cpu_alert1>;
559 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
564 gpu_thermal: gpu_thermal {
565 polling-delay-passive = <250>; /* milliseconds */
566 polling-delay = <5000>; /* milliseconds */
568 thermal-sensors = <&tsadc 2>;
571 gpu_alert0: gpu_alert0 {
572 temperature = <80000>; /* millicelsius */
573 hysteresis = <2000>; /* millicelsius */
577 temperature = <90000>; /* millicelsius */
578 hysteresis = <2000>; /* millicelsius */
585 trip = <&gpu_alert0>;
587 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
593 tsadc: tsadc@ff280000 {
594 compatible = "rockchip,rk3288-tsadc";
595 reg = <0xff280000 0x100>;
596 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
598 clock-names = "tsadc", "apb_pclk";
599 resets = <&cru SRST_TSADC>;
600 reset-names = "tsadc-apb";
601 pinctrl-names = "init", "default", "sleep";
602 pinctrl-0 = <&otp_gpio>;
603 pinctrl-1 = <&otp_out>;
604 pinctrl-2 = <&otp_gpio>;
605 #thermal-sensor-cells = <1>;
606 rockchip,hw-tshut-temp = <95000>;
610 gmac: ethernet@ff290000 {
611 compatible = "rockchip,rk3288-gmac";
612 reg = <0xff290000 0x10000>;
613 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "macirq", "eth_wake_irq";
616 rockchip,grf = <&grf>;
617 clocks = <&cru SCLK_MAC>,
618 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
619 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
620 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
621 clock-names = "stmmaceth",
622 "mac_clk_rx", "mac_clk_tx",
623 "clk_mac_ref", "clk_mac_refout",
624 "aclk_mac", "pclk_mac";
625 resets = <&cru SRST_MAC>;
626 reset-names = "stmmaceth";
631 usb_host0_ehci: usb@ff500000 {
632 compatible = "generic-ehci";
633 reg = <0xff500000 0x100>;
634 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cru HCLK_USBHOST0>;
636 clock-names = "usbhost";
642 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
644 usb_host1: usb@ff540000 {
645 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
647 reg = <0xff540000 0x40000>;
648 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cru HCLK_USBHOST1>;
653 phy-names = "usb2-phy";
657 usb_otg: usb@ff580000 {
658 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
660 reg = <0xff580000 0x40000>;
661 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cru HCLK_OTG0>;
665 g-np-tx-fifo-size = <16>;
666 g-rx-fifo-size = <275>;
667 g-tx-fifo-size = <256 128 128 64 64 32>;
670 phy-names = "usb2-phy";
674 usb_hsic: usb@ff5c0000 {
675 compatible = "generic-ehci";
676 reg = <0xff5c0000 0x100>;
677 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&cru HCLK_HSIC>;
679 clock-names = "usbhost";
684 compatible = "rockchip,rk3288-i2c";
685 reg = <0xff650000 0x1000>;
686 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
687 #address-cells = <1>;
690 clocks = <&cru PCLK_I2C0>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&i2c0_xfer>;
697 compatible = "rockchip,rk3288-i2c";
698 reg = <0xff660000 0x1000>;
699 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
700 #address-cells = <1>;
703 clocks = <&cru PCLK_I2C2>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&i2c2_xfer>;
710 compatible = "rockchip,rk3288-pwm";
711 reg = <0xff680000 0x10>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&pwm0_pin>;
715 clocks = <&cru PCLK_PWM>;
721 compatible = "rockchip,rk3288-pwm";
722 reg = <0xff680010 0x10>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&pwm1_pin>;
726 clocks = <&cru PCLK_PWM>;
732 compatible = "rockchip,rk3288-pwm";
733 reg = <0xff680020 0x10>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&pwm2_pin>;
737 clocks = <&cru PCLK_PWM>;
743 compatible = "rockchip,rk3288-pwm";
744 reg = <0xff680030 0x10>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&pwm3_pin>;
748 clocks = <&cru PCLK_PWM>;
753 bus_intmem@ff700000 {
754 compatible = "mmio-sram";
755 reg = <0xff700000 0x18000>;
756 #address-cells = <1>;
758 ranges = <0 0xff700000 0x18000>;
760 compatible = "rockchip,rk3066-smp-sram";
766 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
767 reg = <0xff720000 0x1000>;
770 qos_gpu_r: qos@ffaa0000 {
771 compatible = "syscon";
772 reg = <0xffaa0000 0x20>;
775 qos_gpu_w: qos@ffaa0080 {
776 compatible = "syscon";
777 reg = <0xffaa0080 0x20>;
780 qos_vio1_vop: qos@ffad0000 {
781 compatible = "syscon";
782 reg = <0xffad0000 0x20>;
785 qos_vio1_isp_w0: qos@ffad0100 {
786 compatible = "syscon";
787 reg = <0xffad0100 0x20>;
790 qos_vio1_isp_w1: qos@ffad0180 {
791 compatible = "syscon";
792 reg = <0xffad0180 0x20>;
795 qos_vio0_vop: qos@ffad0400 {
796 compatible = "syscon";
797 reg = <0xffad0400 0x20>;
800 qos_vio0_vip: qos@ffad0480 {
801 compatible = "syscon";
802 reg = <0xffad0480 0x20>;
805 qos_vio0_iep: qos@ffad0500 {
806 compatible = "syscon";
807 reg = <0xffad0500 0x20>;
810 qos_vio2_rga_r: qos@ffad0800 {
811 compatible = "syscon";
812 reg = <0xffad0800 0x20>;
815 qos_vio2_rga_w: qos@ffad0880 {
816 compatible = "syscon";
817 reg = <0xffad0880 0x20>;
820 qos_vio1_isp_r: qos@ffad0900 {
821 compatible = "syscon";
822 reg = <0xffad0900 0x20>;
825 qos_video: qos@ffae0000 {
826 compatible = "syscon";
827 reg = <0xffae0000 0x20>;
830 qos_hevc_r: qos@ffaf0000 {
831 compatible = "syscon";
832 reg = <0xffaf0000 0x20>;
835 qos_hevc_w: qos@ffaf0080 {
836 compatible = "syscon";
837 reg = <0xffaf0080 0x20>;
840 pmu: power-management@ff730000 {
841 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
842 reg = <0xff730000 0x100>;
844 power: power-controller {
845 compatible = "rockchip,rk3288-power-controller";
846 #power-domain-cells = <1>;
847 #address-cells = <1>;
851 * Note: Although SCLK_* are the working clocks
852 * of device without including on the NOC, needed for
855 * The clocks on the which NOC:
856 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
857 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
858 * ACLK_RGA is on ACLK_RGA_NIU.
859 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
861 * Which clock are device clocks:
863 * *_IEP IEP:Image Enhancement Processor
864 * *_ISP ISP:Image Signal Processing
865 * *_VIP VIP:Video Input Processor
866 * *_VOP* VOP:Visual Output Processor
873 pd_vio@RK3288_PD_VIO {
874 reg = <RK3288_PD_VIO>;
875 clocks = <&cru ACLK_IEP>,
889 <&cru PCLK_EDP_CTRL>,
890 <&cru PCLK_HDMI_CTRL>,
891 <&cru PCLK_LVDS_PHY>,
892 <&cru PCLK_MIPI_CSI>,
893 <&cru PCLK_MIPI_DSI0>,
894 <&cru PCLK_MIPI_DSI1>,
900 pm_qos = <&qos_vio0_iep>,
912 * Note: The following 3 are HEVC(H.265) clocks,
913 * and on the ACLK_HEVC_NIU (NOC).
915 pd_hevc@RK3288_PD_HEVC {
916 reg = <RK3288_PD_HEVC>;
917 clocks = <&cru ACLK_HEVC>,
918 <&cru SCLK_HEVC_CABAC>,
919 <&cru SCLK_HEVC_CORE>;
920 pm_qos = <&qos_hevc_r>,
925 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
926 * (video endecoder & decoder) clocks that on the
927 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
929 pd_video@RK3288_PD_VIDEO {
930 reg = <RK3288_PD_VIDEO>;
931 clocks = <&cru ACLK_VCODEC>,
933 pm_qos = <&qos_video>;
937 * Note: ACLK_GPU is the GPU clock,
938 * and on the ACLK_GPU_NIU (NOC).
940 pd_gpu@RK3288_PD_GPU {
941 reg = <RK3288_PD_GPU>;
942 clocks = <&cru ACLK_GPU>;
943 pm_qos = <&qos_gpu_r>,
949 compatible = "syscon-reboot-mode";
951 mode-normal = <BOOT_NORMAL>;
952 mode-recovery = <BOOT_RECOVERY>;
953 mode-bootloader = <BOOT_FASTBOOT>;
954 mode-loader = <BOOT_BL_DOWNLOAD>;
955 mode-ums = <BOOT_UMS>;
959 sgrf: syscon@ff740000 {
960 compatible = "rockchip,rk3288-sgrf", "syscon";
961 reg = <0xff740000 0x1000>;
964 cru: clock-controller@ff760000 {
965 compatible = "rockchip,rk3288-cru";
966 reg = <0xff760000 0x1000>;
967 rockchip,grf = <&grf>;
970 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
971 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
972 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
973 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
974 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
976 assigned-clock-rates = <0>, <0>,
977 <594000000>, <400000000>,
978 <500000000>, <300000000>,
979 <150000000>, <75000000>,
980 <300000000>, <150000000>,
982 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
985 grf: syscon@ff770000 {
986 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
987 reg = <0xff770000 0x1000>;
990 compatible = "rockchip,rk3288-dp-phy";
991 clocks = <&cru SCLK_EDP_24M>;
997 io_domains: io-domains {
998 compatible = "rockchip,rk3288-io-voltage-domain";
1003 compatible = "rockchip,rk3288-usb-phy";
1004 #address-cells = <1>;
1006 status = "disabled";
1008 usbphy0: usb-phy@320 {
1011 clocks = <&cru SCLK_OTGPHY0>;
1012 clock-names = "phyclk";
1014 resets = <&cru SRST_USBOTG_PHY>;
1015 reset-names = "phy-reset";
1018 usbphy1: usb-phy@334 {
1021 clocks = <&cru SCLK_OTGPHY1>;
1022 clock-names = "phyclk";
1026 usbphy2: usb-phy@348 {
1029 clocks = <&cru SCLK_OTGPHY2>;
1030 clock-names = "phyclk";
1032 resets = <&cru SRST_USBHOST1_PHY>;
1033 reset-names = "phy-reset";
1038 wdt: watchdog@ff800000 {
1039 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1040 reg = <0xff800000 0x100>;
1041 clocks = <&cru PCLK_WDT>;
1042 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1043 status = "disabled";
1046 spdif: sound@ff88b0000 {
1047 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1048 reg = <0xff8b0000 0x10000>;
1049 #sound-dai-cells = <0>;
1050 clock-names = "hclk", "mclk";
1051 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1052 dmas = <&dmac_bus_s 3>;
1054 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1055 pinctrl-names = "default";
1056 pinctrl-0 = <&spdif_tx>;
1057 rockchip,grf = <&grf>;
1058 status = "disabled";
1062 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1063 reg = <0xff890000 0x10000>;
1064 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1065 #address-cells = <1>;
1067 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1068 dma-names = "tx", "rx";
1069 clock-names = "i2s_hclk", "i2s_clk";
1070 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&i2s0_bus>;
1073 rockchip,playback-channels = <8>;
1074 rockchip,capture-channels = <2>;
1075 status = "disabled";
1079 compatible = "rockchip,rk3288-rga";
1080 reg = <0xff920000 0x180>;
1081 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1082 interrupt-names = "rga";
1083 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1084 clock-names = "aclk", "hclk", "sclk";
1085 power-domains = <&power RK3288_PD_VIO>;
1086 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1087 reset-names = "core", "axi", "ahb";
1088 status = "disabled";
1091 vopb: vop@ff930000 {
1092 compatible = "rockchip,rk3288-vop";
1093 reg = <0xff930000 0x19c>;
1094 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1096 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1097 power-domains = <&power RK3288_PD_VIO>;
1098 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1099 reset-names = "axi", "ahb", "dclk";
1100 iommus = <&vopb_mmu>;
1101 status = "disabled";
1104 #address-cells = <1>;
1107 vopb_out_hdmi: endpoint@0 {
1109 remote-endpoint = <&hdmi_in_vopb>;
1112 vopb_out_edp: endpoint@1 {
1114 remote-endpoint = <&edp_in_vopb>;
1117 vopb_out_mipi: endpoint@2 {
1119 remote-endpoint = <&mipi_in_vopb>;
1122 vopb_out_lvds: endpoint@3 {
1124 remote-endpoint = <&lvds_in_vopb>;
1129 vopb_mmu: iommu@ff930300 {
1130 compatible = "rockchip,iommu";
1131 reg = <0xff930300 0x100>;
1132 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1133 interrupt-names = "vopb_mmu";
1134 power-domains = <&power RK3288_PD_VIO>;
1136 status = "disabled";
1139 vopl: vop@ff940000 {
1140 compatible = "rockchip,rk3288-vop";
1141 reg = <0xff940000 0x19c>;
1142 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1144 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1145 power-domains = <&power RK3288_PD_VIO>;
1146 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1147 reset-names = "axi", "ahb", "dclk";
1148 iommus = <&vopl_mmu>;
1149 status = "disabled";
1152 #address-cells = <1>;
1155 vopl_out_hdmi: endpoint@0 {
1157 remote-endpoint = <&hdmi_in_vopl>;
1160 vopl_out_edp: endpoint@1 {
1162 remote-endpoint = <&edp_in_vopl>;
1165 vopl_out_mipi: endpoint@2 {
1167 remote-endpoint = <&mipi_in_vopl>;
1170 vopl_out_lvds: endpoint@3 {
1172 remote-endpoint = <&lvds_in_vopl>;
1178 vopl_mmu: iommu@ff940300 {
1179 compatible = "rockchip,iommu";
1180 reg = <0xff940300 0x100>;
1181 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1182 interrupt-names = "vopl_mmu";
1183 power-domains = <&power RK3288_PD_VIO>;
1185 status = "disabled";
1188 mipi_dsi: mipi@ff960000 {
1189 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1190 reg = <0xff960000 0x4000>;
1191 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1193 clock-names = "ref", "pclk";
1194 power-domains = <&power RK3288_PD_VIO>;
1195 rockchip,grf = <&grf>;
1196 #address-cells = <1>;
1198 status = "disabled";
1202 #address-cells = <1>;
1204 mipi_in_vopb: endpoint@0 {
1206 remote-endpoint = <&vopb_out_mipi>;
1208 mipi_in_vopl: endpoint@1 {
1210 remote-endpoint = <&vopl_out_mipi>;
1217 compatible = "rockchip,rk3288-dp";
1218 reg = <0xff970000 0x4000>;
1219 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1221 clock-names = "dp", "pclk";
1222 power-domains = <&power RK3288_PD_VIO>;
1225 resets = <&cru SRST_EDP>;
1227 rockchip,grf = <&grf>;
1228 status = "disabled";
1231 #address-cells = <1>;
1235 #address-cells = <1>;
1237 edp_in_vopb: endpoint@0 {
1239 remote-endpoint = <&vopb_out_edp>;
1241 edp_in_vopl: endpoint@1 {
1243 remote-endpoint = <&vopl_out_edp>;
1249 lvds: lvds@ff96c000 {
1250 compatible = "rockchip,rk3288-lvds";
1251 reg = <0xff96c000 0x4000>;
1252 clocks = <&cru PCLK_LVDS_PHY>;
1253 clock-names = "pclk_lvds";
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&lcdc0_ctl>;
1256 power-domains = <&power RK3288_PD_VIO>;
1257 rockchip,grf = <&grf>;
1258 status = "disabled";
1261 #address-cells = <1>;
1267 #address-cells = <1>;
1270 lvds_in_vopb: endpoint@0 {
1272 remote-endpoint = <&vopb_out_lvds>;
1274 lvds_in_vopl: endpoint@1 {
1276 remote-endpoint = <&vopl_out_lvds>;
1282 hdmi: hdmi@ff980000 {
1283 compatible = "rockchip,rk3288-dw-hdmi";
1284 reg = <0xff980000 0x20000>;
1286 rockchip,grf = <&grf>;
1287 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1289 clock-names = "iahb", "isfr";
1290 power-domains = <&power RK3288_PD_VIO>;
1291 status = "disabled";
1295 #address-cells = <1>;
1297 hdmi_in_vopb: endpoint@0 {
1299 remote-endpoint = <&vopb_out_hdmi>;
1301 hdmi_in_vopl: endpoint@1 {
1303 remote-endpoint = <&vopl_out_hdmi>;
1310 compatible = "arm,malit764",
1314 reg = <0xffa30000 0x10000>;
1315 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1318 interrupt-names = "JOB", "MMU", "GPU";
1319 clocks = <&cru ACLK_GPU>;
1320 clock-names = "clk_mali";
1321 operating-points-v2 = <&gpu_opp_table>;
1322 #cooling-cells = <2>; /* min followed by max */
1323 power-domains = <&power RK3288_PD_GPU>;
1324 status = "disabled";
1326 gpu_power_model: power_model {
1327 compatible = "arm,mali-simple-power-model";
1330 static-power = <300>;
1331 dynamic-power = <396>;
1332 ts = <32000 4700 (-80) 2>;
1333 thermal-zone = "gpu_thermal";
1337 gpu_opp_table: opp-table1 {
1338 compatible = "operating-points-v2";
1341 opp-hz = /bits/ 64 <100000000>;
1342 opp-microvolt = <950000>;
1345 opp-hz = /bits/ 64 <200000000>;
1346 opp-microvolt = <950000>;
1349 opp-hz = /bits/ 64 <300000000>;
1350 opp-microvolt = <1000000>;
1353 opp-hz = /bits/ 64 <400000000>;
1354 opp-microvolt = <1100000>;
1357 opp-hz = /bits/ 64 <600000000>;
1358 opp-microvolt = <1250000>;
1362 vpu: video-codec@ff9a0000 {
1363 compatible = "rockchip,rk3288-vpu";
1364 reg = <0xff9a0000 0x800>;
1365 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1367 interrupt-names = "vepu", "vdpu";
1368 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1369 clock-names = "aclk", "hclk";
1370 power-domains = <&power RK3288_PD_VIDEO>;
1371 iommus = <&vpu_mmu>;
1372 assigned-clocks = <&cru ACLK_VCODEC>;
1373 assigned-clock-rates = <400000000>;
1374 status = "disabled";
1377 vpu_service: vpu-service@ff9a0000 {
1378 compatible = "rockchip,vpu_service";
1379 reg = <0xff9a0000 0x800>;
1380 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1382 interrupt-names = "irq_enc", "irq_dec";
1383 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1384 clock-names = "aclk_vcodec", "hclk_vcodec";
1385 power-domains = <&power RK3288_PD_VIDEO>;
1386 rockchip,grf = <&grf>;
1387 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1388 reset-names = "video_a", "video_h";
1389 iommus = <&vpu_mmu>;
1390 iommu_enabled = <1>;
1392 status = "disabled";
1393 /* 0 means ion, 1 means drm */
1397 vpu_mmu: iommu@ff9a0800 {
1398 compatible = "rockchip,iommu";
1399 reg = <0xff9a0800 0x100>;
1400 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1401 interrupt-names = "vpu_mmu";
1402 power-domains = <&power RK3288_PD_VIDEO>;
1406 hevc_service: hevc-service@ff9c0000 {
1407 compatible = "rockchip,hevc_service";
1408 reg = <0xff9c0000 0x400>;
1409 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1410 interrupt-names = "irq_dec";
1411 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1412 <&cru SCLK_HEVC_CORE>,
1413 <&cru SCLK_HEVC_CABAC>;
1414 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1417 * The 4K hevc would also work well with 500/125/300/300,
1418 * no more err irq and reset request.
1420 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1421 <&cru SCLK_HEVC_CORE>,
1422 <&cru SCLK_HEVC_CABAC>;
1423 assigned-clock-rates = <400000000>, <100000000>,
1424 <300000000>, <300000000>;
1426 resets = <&cru SRST_HEVC>;
1427 reset-names = "video";
1428 power-domains = <&power RK3288_PD_HEVC>;
1429 rockchip,grf = <&grf>;
1431 iommus = <&hevc_mmu>;
1432 iommu_enabled = <1>;
1433 status = "disabled";
1434 /* 0 means ion, 1 means drm */
1438 hevc_mmu: iommu@ff9c0440 {
1439 compatible = "rockchip,iommu";
1440 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1441 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1442 interrupt-names = "hevc_mmu";
1443 power-domains = <&power RK3288_PD_HEVC>;
1447 gic: interrupt-controller@ffc01000 {
1448 compatible = "arm,gic-400";
1449 interrupt-controller;
1450 #interrupt-cells = <3>;
1451 #address-cells = <0>;
1453 reg = <0xffc01000 0x1000>,
1454 <0xffc02000 0x1000>,
1455 <0xffc04000 0x2000>,
1456 <0xffc06000 0x2000>;
1457 interrupts = <GIC_PPI 9 0xf04>;
1460 efuse: efuse@ffb40000 {
1461 compatible = "rockchip,rockchip-efuse";
1462 reg = <0xffb40000 0x20>;
1463 #address-cells = <1>;
1465 clocks = <&cru PCLK_EFUSE256>;
1466 clock-names = "pclk_efuse";
1468 cpu_leakage: cpu_leakage@17 {
1473 cif_isp0: cif_isp@ff910000 {
1474 compatible = "rockchip,rk3288-cif-isp";
1475 rockchip,grf = <&grf>;
1476 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1477 reg-names = "register", "csihost-register";
1478 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1479 <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1480 <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1481 <&cru SCLK_MIPIDSI_24M>;
1482 clock-names = "aclk_isp", "hclk_isp",
1483 "sclk_isp", "sclk_isp_jpe",
1484 "pclk_mipi_csi", "pclk_isp_in",
1486 resets = <&cru SRST_ISP>;
1487 reset-names = "rst_isp";
1488 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1489 interrupt-names = "cif_isp10_irq";
1490 status = "disabled";
1494 compatible = "rockchip,rk3288-pinctrl";
1495 rockchip,grf = <&grf>;
1496 rockchip,pmu = <&pmu>;
1497 #address-cells = <1>;
1501 gpio0: gpio0@ff750000 {
1502 compatible = "rockchip,gpio-bank";
1503 reg = <0xff750000 0x100>;
1504 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&cru PCLK_GPIO0>;
1510 interrupt-controller;
1511 #interrupt-cells = <2>;
1514 gpio1: gpio1@ff780000 {
1515 compatible = "rockchip,gpio-bank";
1516 reg = <0xff780000 0x100>;
1517 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1518 clocks = <&cru PCLK_GPIO1>;
1523 interrupt-controller;
1524 #interrupt-cells = <2>;
1527 gpio2: gpio2@ff790000 {
1528 compatible = "rockchip,gpio-bank";
1529 reg = <0xff790000 0x100>;
1530 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1531 clocks = <&cru PCLK_GPIO2>;
1536 interrupt-controller;
1537 #interrupt-cells = <2>;
1540 gpio3: gpio3@ff7a0000 {
1541 compatible = "rockchip,gpio-bank";
1542 reg = <0xff7a0000 0x100>;
1543 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1544 clocks = <&cru PCLK_GPIO3>;
1549 interrupt-controller;
1550 #interrupt-cells = <2>;
1553 gpio4: gpio4@ff7b0000 {
1554 compatible = "rockchip,gpio-bank";
1555 reg = <0xff7b0000 0x100>;
1556 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1557 clocks = <&cru PCLK_GPIO4>;
1562 interrupt-controller;
1563 #interrupt-cells = <2>;
1566 gpio5: gpio5@ff7c0000 {
1567 compatible = "rockchip,gpio-bank";
1568 reg = <0xff7c0000 0x100>;
1569 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1570 clocks = <&cru PCLK_GPIO5>;
1575 interrupt-controller;
1576 #interrupt-cells = <2>;
1579 gpio6: gpio6@ff7d0000 {
1580 compatible = "rockchip,gpio-bank";
1581 reg = <0xff7d0000 0x100>;
1582 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1583 clocks = <&cru PCLK_GPIO6>;
1588 interrupt-controller;
1589 #interrupt-cells = <2>;
1592 gpio7: gpio7@ff7e0000 {
1593 compatible = "rockchip,gpio-bank";
1594 reg = <0xff7e0000 0x100>;
1595 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1596 clocks = <&cru PCLK_GPIO7>;
1601 interrupt-controller;
1602 #interrupt-cells = <2>;
1605 gpio8: gpio8@ff7f0000 {
1606 compatible = "rockchip,gpio-bank";
1607 reg = <0xff7f0000 0x100>;
1608 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cru PCLK_GPIO8>;
1614 interrupt-controller;
1615 #interrupt-cells = <2>;
1619 hdmi_ddc: hdmi-ddc {
1620 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1621 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1625 pcfg_pull_up: pcfg-pull-up {
1629 pcfg_pull_down: pcfg-pull-down {
1633 pcfg_pull_none: pcfg-pull-none {
1637 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1639 drive-strength = <12>;
1643 global_pwroff: global-pwroff {
1644 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1647 ddrio_pwroff: ddrio-pwroff {
1648 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1651 ddr0_retention: ddr0-retention {
1652 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1655 ddr1_retention: ddr1-retention {
1656 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1662 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1667 i2c0_xfer: i2c0-xfer {
1668 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1669 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1674 i2c1_xfer: i2c1-xfer {
1675 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1676 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1681 i2c2_xfer: i2c2-xfer {
1682 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1683 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1688 i2c3_xfer: i2c3-xfer {
1689 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1690 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1695 i2c4_xfer: i2c4-xfer {
1696 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1697 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1702 i2c5_xfer: i2c5-xfer {
1703 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1704 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1709 i2s0_bus: i2s0-bus {
1710 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1711 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1712 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1713 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1714 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1715 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1720 lcdc0_ctl: lcdc0-ctl {
1721 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1722 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1723 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1724 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1729 sdmmc_clk: sdmmc-clk {
1730 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1733 sdmmc_cmd: sdmmc-cmd {
1734 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1737 sdmmc_cd: sdmcc-cd {
1738 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1741 sdmmc_bus1: sdmmc-bus1 {
1742 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1745 sdmmc_bus4: sdmmc-bus4 {
1746 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1747 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1748 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1749 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1754 sdio0_bus1: sdio0-bus1 {
1755 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1758 sdio0_bus4: sdio0-bus4 {
1759 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1760 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1761 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1762 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1765 sdio0_cmd: sdio0-cmd {
1766 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1769 sdio0_clk: sdio0-clk {
1770 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1773 sdio0_cd: sdio0-cd {
1774 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1777 sdio0_wp: sdio0-wp {
1778 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1781 sdio0_pwr: sdio0-pwr {
1782 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1785 sdio0_bkpwr: sdio0-bkpwr {
1786 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1789 sdio0_int: sdio0-int {
1790 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1795 sdio1_bus1: sdio1-bus1 {
1796 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1799 sdio1_bus4: sdio1-bus4 {
1800 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1801 <3 25 4 &pcfg_pull_up>,
1802 <3 26 4 &pcfg_pull_up>,
1803 <3 27 4 &pcfg_pull_up>;
1806 sdio1_cd: sdio1-cd {
1807 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1810 sdio1_wp: sdio1-wp {
1811 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1814 sdio1_bkpwr: sdio1-bkpwr {
1815 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1818 sdio1_int: sdio1-int {
1819 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1822 sdio1_cmd: sdio1-cmd {
1823 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1826 sdio1_clk: sdio1-clk {
1827 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1830 sdio1_pwr: sdio1-pwr {
1831 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1836 emmc_clk: emmc-clk {
1837 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1840 emmc_cmd: emmc-cmd {
1841 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1844 emmc_pwr: emmc-pwr {
1845 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1848 emmc_bus1: emmc-bus1 {
1849 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1852 emmc_bus4: emmc-bus4 {
1853 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1854 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1855 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1856 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1859 emmc_bus8: emmc-bus8 {
1860 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1861 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1862 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1863 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1864 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1865 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1866 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1867 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1872 spi0_clk: spi0-clk {
1873 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1875 spi0_cs0: spi0-cs0 {
1876 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1879 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1882 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1884 spi0_cs1: spi0-cs1 {
1885 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1889 spi1_clk: spi1-clk {
1890 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1892 spi1_cs0: spi1-cs0 {
1893 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1896 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1899 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1904 spi2_cs1: spi2-cs1 {
1905 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1907 spi2_clk: spi2-clk {
1908 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1910 spi2_cs0: spi2-cs0 {
1911 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1914 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1917 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1922 uart0_xfer: uart0-xfer {
1923 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1924 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1927 uart0_cts: uart0-cts {
1928 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1931 uart0_rts: uart0-rts {
1932 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1937 uart1_xfer: uart1-xfer {
1938 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1939 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1942 uart1_cts: uart1-cts {
1943 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1946 uart1_rts: uart1-rts {
1947 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1952 uart2_xfer: uart2-xfer {
1953 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1954 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1956 /* no rts / cts for uart2 */
1960 uart3_xfer: uart3-xfer {
1961 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1962 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1965 uart3_cts: uart3-cts {
1966 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1969 uart3_rts: uart3-rts {
1970 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1975 uart4_xfer: uart4-xfer {
1976 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1977 <5 13 3 &pcfg_pull_none>;
1980 uart4_cts: uart4-cts {
1981 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1984 uart4_rts: uart4-rts {
1985 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1990 otp_gpio: otp-gpio {
1991 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1995 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2000 pwm0_pin: pwm0-pin {
2001 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2006 pwm1_pin: pwm1-pin {
2007 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2012 pwm2_pin: pwm2-pin {
2013 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2018 pwm3_pin: pwm3-pin {
2019 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2024 rgmii_pins: rgmii-pins {
2025 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2026 <3 31 3 &pcfg_pull_none>,
2027 <3 26 3 &pcfg_pull_none>,
2028 <3 27 3 &pcfg_pull_none>,
2029 <3 28 3 &pcfg_pull_none_12ma>,
2030 <3 29 3 &pcfg_pull_none_12ma>,
2031 <3 24 3 &pcfg_pull_none_12ma>,
2032 <3 25 3 &pcfg_pull_none_12ma>,
2033 <4 0 3 &pcfg_pull_none>,
2034 <4 5 3 &pcfg_pull_none>,
2035 <4 6 3 &pcfg_pull_none>,
2036 <4 9 3 &pcfg_pull_none_12ma>,
2037 <4 4 3 &pcfg_pull_none_12ma>,
2038 <4 1 3 &pcfg_pull_none>,
2039 <4 3 3 &pcfg_pull_none>;
2042 rmii_pins: rmii-pins {
2043 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2044 <3 31 3 &pcfg_pull_none>,
2045 <3 28 3 &pcfg_pull_none>,
2046 <3 29 3 &pcfg_pull_none>,
2047 <4 0 3 &pcfg_pull_none>,
2048 <4 5 3 &pcfg_pull_none>,
2049 <4 4 3 &pcfg_pull_none>,
2050 <4 1 3 &pcfg_pull_none>,
2051 <4 2 3 &pcfg_pull_none>,
2052 <4 3 3 &pcfg_pull_none>;
2057 spdif_tx: spdif-tx {
2058 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2063 cif_dvp_d2d9: cif-dvp-d2d9 {
2064 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2065 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2066 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2067 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2068 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2069 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2070 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2071 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2072 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2073 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2074 <2 11 RK_FUNC_1 &pcfg_pull_none>;