arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/suspend/rockchip-pm.h>
   5 #include <dt-bindings/sensor-dev.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk3288-pinctrl.dtsi"
   9 #include "rk3288-clocks.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk3288";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial0 = &uart_bt;
  17                 serial1 = &uart_bb;
  18                 serial2 = &uart_dbg;
  19                 serial3 = &uart_gps;
  20                 serial4 = &uart_exp;
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 lcdc0 = &lcdc0;
  28                 lcdc1 = &lcdc1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a15";
  38                         reg = <0x500>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x501>;
  44                 };
  45                 cpu@2 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x502>;
  49                 };
  50                 cpu@3 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x503>;
  54                 };
  55         };
  56
  57         gic: interrupt-controller@ffc01000 {
  58                 compatible = "arm,cortex-a15-gic";
  59                 interrupt-controller;
  60                 #interrupt-cells = <3>;
  61                 #address-cells = <0>;
  62                 reg = <0xffc01000 0x1000>,
  63                       <0xffc02000 0x1000>;
  64         };
  65
  66         cpu_axi_bus: cpu_axi_bus {
  67                 compatible = "rockchip,cpu_axi_bus";
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 ranges;
  71                 qos {
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         ranges;
  75                         /* service core */
  76                         cpup {
  77                                 reg = <0xffa80000 0x20>;
  78                         };
  79                         cpum_r {
  80                                 reg = <0xffa80080 0x20>;
  81                         };
  82                         cpum_w {
  83                                 reg = <0xffa80100 0x20>;
  84                         };
  85                         /* service dmac */
  86                         bus_dmac {
  87                                 reg = <0xffa90000 0x20>;
  88                         };
  89                         host {
  90                                 reg = <0xffa90080 0x20>;
  91                         };
  92                         crypto {
  93                                 reg = <0xffa90100 0x20>;
  94                         };
  95                         ccp {
  96                                 reg = <0xffa90180 0x20>;
  97                         };
  98                         ccs {
  99                                 reg = <0xffa90200 0x20>;
 100                         };
 101                         /* service gpu */
 102                         gpu_r {
 103                                 reg = <0xffaa0000 0x20>;
 104                         };
 105                         gpu_w {
 106                                 reg = <0xffaa0080 0x20>;
 107                         };
 108                         /* service peri */
 109                         peri {
 110                                 reg = <0xffab0000 0x20>;
 111                         };
 112                         /* service vio */
 113                         vio1_vop {
 114                                 reg = <0xffad0000 0x20>;
 115                         };
 116                         vio1_isp_w0 {
 117                                 reg = <0xffad0100 0x20>;
 118                         };
 119                         vio1_isp_w1 {
 120                                 reg = <0xffad0180 0x20>;
 121                         };
 122                         vio0_vop {
 123                                 reg = <0xffad0400 0x20>;
 124                         };
 125                         vio0_vip {
 126                                 reg = <0xffad0480 0x20>;
 127                         };
 128                         vio0_iep {
 129                                 reg = <0xffad0500 0x20>;
 130                         };
 131                         vio2_rga_r {
 132                                 reg = <0xffad0800 0x20>;
 133                         };
 134                         vio2_rga_w {
 135                                 reg = <0xffad0880 0x20>;
 136                         };
 137                         vio1_isp_r {
 138                                 reg = <0xffad0900 0x20>;
 139                         };
 140                         /* service video */
 141                         video {
 142                                 reg = <0xffae0000 0x20>;
 143                         };
 144                         /* service hevc */
 145                         hevc_r {
 146                                 reg = <0xffaf0000 0x20>;
 147                         };
 148                         hevc_w {
 149                                 reg = <0xffaf0080 0x20>;
 150                         };
 151                 };
 152                 msch {
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         ranges;
 156                         msch@0 {
 157                                 reg = <0xffac0000 0x40>;
 158                                 rockchip,read-latency = <0xff>;
 159                         };
 160                         msch@1 {
 161                                 reg = <0xffac0080 0x40>;
 162                                 rockchip,read-latency = <0xff>;
 163                         };
 164                 };
 165         };
 166
 167         sram: sram@ff710000 {
 168                 compatible = "mmio-sram";
 169                 reg = <0xff710000 0x8000>; /* 32k */
 170                 map-exec;
 171         };
 172
 173         timer {
 174                 compatible = "arm,armv7-timer";
 175                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 176                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 177                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 178                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 179                 clock-frequency = <24000000>;
 180         };
 181
 182         timer@ff810000 {
 183                 compatible = "rockchip,timer";
 184                 reg = <0xff810000 0x20>;
 185                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 186                 rockchip,broadcast = <1>;
 187         };
 188
 189         timer@ff810020 {
 190                 compatible = "rockchip,timer";
 191                 reg = <0xff810020 0x20>;
 192                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 193                 rockchip,clocksource = <1>;
 194                 rockchip,count-up = <1>;
 195         };
 196
 197     amba {
 198                 #address-cells = <1>;
 199                 #size-cells = <1>;
 200                 compatible = "arm,amba-bus";
 201                 interrupt-parent = <&gic>;
 202                 ranges;
 203
 204                 pdma0: pdma@ffb20000 {
 205                         compatible = "arm,pl330", "arm,primecell";
 206                         reg = <0xffb20000 0x4000>;
 207                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 208                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 209                         #dma-cells = <1>;
 210                 };
 211
 212                 pdma1: pdma@ff250000 {
 213                         compatible = "arm,pl330", "arm,primecell";
 214                         reg = <0xff250000 0x4000>;
 215                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 217                         #dma-cells = <1>;
 218                 };
 219         };
 220
 221
 222         emmc: rksdmmc@ff0f0000 {
 223                 compatible = "rockchip,rk_mmc";
 224                 reg = <0xff0f0000 0x4000>;
 225                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 //pinctrl-names = "default",,"suspend";
 229                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 230
 231                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_3 --clk_emmc_src_gate_en*/
 232                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 233                 clock-names = "clk_mmc", "hclk_mmc";
 234                 num-slots = <1>;
 235                 fifo-depth = <0x80>;
 236                 bus-width = <4>;
 237         };
 238
 239         sdmmc: rksdmmc@ff0c0000 {
 240                 compatible = "rockchip,rk_mmc";
 241                 reg = <0xff0c0000 0x4000>;
 242                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245
 246                 //pinctrl-names = "default","suspend";
 247                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 248                 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 249
 250                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_0 --clk_mmc0_src_gate_en*/
 251                         clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 252                         clock-names = "clk_mmc", "hclk_mmc";
 253                 num-slots = <1>;
 254                 fifo-depth = <0x100>;
 255                 bus-width = <4>;
 256
 257         };
 258
 259         sdio: rksdmmc@ff0d0000 {
 260                 compatible = "rockchip,rk_mmc";
 261                 reg = <0xff0d0000 0x4000>;
 262                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 //pinctrl-names = "default","suspend";
 266                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 267
 268                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_1 --clk_sdio0_src_gate_en*/
 269                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 270                 clock-names = "clk_mmc", "hclk_mmc";
 271                 num-slots = <1>;
 272
 273                 fifo-depth = <0x100>;
 274                 bus-width = <4>;
 275         };
 276
 277         sdio1: rksdmmc@ff0e0000 {
 278                 compatible = "rockchip,rk_mmc";
 279                 reg = <0xff0e0000 0x4000>;
 280                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 //pinctrl-names = "default","suspend";
 284                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 285
 286                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 287                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 288                 clock-names = "clk_mmc", "hclk_mmc";
 289                 num-slots = <1>;
 290
 291                 fifo-depth = <0x100>;
 292                 bus-width = <4>;
 293         };
 294
 295         spi0: spi@ff110000 {
 296                 compatible = "rockchip,rockchip-spi";
 297                 reg = <0xff110000 0x1000>;
 298                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 303                 rockchip,spi-src-clk = <0>;
 304                 num-cs = <2>;
 305                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 306                 clock-names = "spi","pclk_spi0";
 307                 //dmas = <&pdma1 11>, <&pdma1 12>;
 308                 //#dma-cells = <2>;
 309                 //dma-names = "tx", "rx";
 310                 status = "disabled";
 311         };
 312
 313         spi1: spi@ff120000 {
 314                 compatible = "rockchip,rockchip-spi";
 315                 reg = <0xff120000 0x1000>;
 316                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 321                 rockchip,spi-src-clk = <1>;
 322                 num-cs = <1>;
 323                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 324                 clock-names = "spi","pclk_spi1";
 325                 //dmas = <&pdma1 13>, <&pdma1 14>;
 326                 //#dma-cells = <2>;
 327                 //dma-names = "tx", "rx";
 328                 status = "disabled";
 329         };
 330
 331         spi2: spi@ff130000 {
 332                 compatible = "rockchip,rockchip-spi";
 333                 reg = <0xff130000 0x1000>;
 334                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 339                 rockchip,spi-src-clk = <1>;
 340                 num-cs = <2>;
 341                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 342                 clock-names = "spi","pclk_spi2";
 343                 //dmas = <&pdma1 15>, <&pdma1 16>;
 344                 //#dma-cells = <2>;
 345                 //dma-names = "tx", "rx";
 346                 status = "disabled";
 347         };
 348
 349         uart_bt: serial@ff180000 {
 350                 compatible = "rockchip,serial";
 351                 reg = <0xff180000 0x100>;
 352                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 353                 clock-frequency = <24000000>;
 354                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 355                 clock-names = "sclk_uart", "pclk_uart";
 356                 reg-shift = <2>;
 357                 reg-io-width = <4>;
 358                 dmas = <&pdma1 1>, <&pdma1 2>;
 359                 #dma-cells = <2>;
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 362                 status = "disabled";
 363         };
 364
 365         uart_bb: serial@ff190000 {
 366                 compatible = "rockchip,serial";
 367                 reg = <0xff190000 0x100>;
 368                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 369                 clock-frequency = <24000000>;
 370                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 371                 clock-names = "sclk_uart", "pclk_uart";
 372                 reg-shift = <2>;
 373                 reg-io-width = <4>;
 374                 dmas = <&pdma1 3>, <&pdma1 4>;
 375                 #dma-cells = <2>;
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 378                 status = "disabled";
 379         };
 380
 381         uart_dbg: serial@ff690000 {
 382                 compatible = "rockchip,serial";
 383                 reg = <0xff690000 0x100>;
 384                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 385                 clock-frequency = <24000000>;
 386                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 387                 clock-names = "sclk_uart", "pclk_uart";
 388                 reg-shift = <2>;
 389                 reg-io-width = <4>;
 390                 dmas = <&pdma0 4>, <&pdma0 5>;
 391                 #dma-cells = <2>;
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&uart2_xfer>;
 394                 status = "disabled";
 395         };
 396
 397         uart_gps: serial@ff1b0000 {
 398                 compatible = "rockchip,serial";
 399                 reg = <0xff1b0000 0x100>;
 400                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 401                 clock-frequency = <24000000>;
 402                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 403                 clock-names = "sclk_uart", "pclk_uart";
 404                 current-speed = <115200>;
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 dmas = <&pdma1 7>, <&pdma1 8>;
 408                 #dma-cells = <2>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 411                 status = "disabled";
 412         };
 413
 414         uart_exp: serial@ff1c0000 {
 415                 compatible = "rockchip,serial";
 416                 reg = <0xff1c0000 0x100>;
 417                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 418                 clock-frequency = <24000000>;
 419                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 420                 clock-names = "sclk_uart", "pclk_uart";
 421                 reg-shift = <2>;
 422                 reg-io-width = <4>;
 423                 dmas = <&pdma1 9>, <&pdma1 10>;
 424                 #dma-cells = <2>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 427                 status = "disabled";
 428         };
 429
 430         fiq-debugger {
 431                 compatible = "rockchip,fiq-debugger";
 432                 rockchip,serial-id = <2>;
 433                 rockchip,signal-irq = <106>;
 434                 rockchip,wake-irq = <0>;
 435                 status = "disabled";
 436         };
 437
 438         clocks-init{
 439                 compatible = "rockchip,clocks-init";
 440                 rockchip,clocks-init-parent =
 441                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 442                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 443                         <&clk_i2s_pll &clk_cpll>;
 444                 rockchip,clocks-init-rate =
 445                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 446                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 447                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 448                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 449                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 450                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 451                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 452                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 453                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 454                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 455                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 456                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 457                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 458                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 459                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 460                         <&clk_tspout 80000000>, <&clk_mac 50000000>;
 461         };
 462
 463         i2c0: i2c@ff650000 {
 464                 compatible = "rockchip,rk30-i2c";
 465                 reg = <0xff650000 0x1000>;
 466                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 pinctrl-names = "default", "gpio";
 470                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 471                 pinctrl-1 = <&i2c0_gpio>;
 472                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 473                 clocks = <&clk_gates10 2>;
 474                 rockchip,check-idle = <1>;
 475                 status = "disabled";
 476         };
 477
 478         i2c1: i2c@ff140000 {
 479                 compatible = "rockchip,rk30-i2c";
 480                 reg = <0xff140000 0x1000>;
 481                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 pinctrl-names = "default", "gpio";
 485                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 486                 pinctrl-1 = <&i2c1_gpio>;
 487                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 488                 clocks = <&clk_gates10 3>;
 489                 rockchip,check-idle = <1>;
 490                 status = "disabled";
 491         };
 492
 493         i2c2: i2c@ff660000 {
 494                 compatible = "rockchip,rk30-i2c";
 495                 reg = <0xff660000 0x1000>;
 496                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 pinctrl-names = "default", "gpio";
 500                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 501                 pinctrl-1 = <&i2c2_gpio>;
 502                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 503                 clocks = <&clk_gates6 13>;
 504                 rockchip,check-idle = <1>;
 505                 status = "disabled";
 506         };
 507
 508         i2c3: i2c@ff150000 {
 509                 compatible = "rockchip,rk30-i2c";
 510                 reg = <0xff150000 0x1000>;
 511                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 pinctrl-names = "default", "gpio";
 515                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 516                 pinctrl-1 = <&i2c3_gpio>;
 517                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 518                 clocks = <&clk_gates6 14>;
 519                 rockchip,check-idle = <1>;
 520                 status = "disabled";
 521         };
 522
 523         i2c4: i2c@ff160000 {
 524                 compatible = "rockchip,rk30-i2c";
 525                 reg = <0xff160000 0x1000>;
 526                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 pinctrl-names = "default", "gpio";
 530                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 531                 pinctrl-1 = <&i2c4_gpio>;
 532                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 533                 clocks = <&clk_gates6 15>;
 534                 rockchip,check-idle = <1>;
 535                 status = "disabled";
 536         };
 537
 538         i2c5: i2c@ff170000 {
 539                 compatible = "rockchip,rk30-i2c";
 540                 reg = <0xff170000 0x1000>;
 541                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 pinctrl-names = "default", "gpio";
 545                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 546                 pinctrl-1 = <&i2c5_gpio>;
 547                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 548                 clocks = <&clk_gates7 0>;
 549                 rockchip,check-idle = <1>;
 550                 status = "disabled";
 551         };
 552
 553
 554         fb: fb{
 555                 compatible = "rockchip,rk-fb";
 556                 rockchip,disp-mode = <DUAL>;
 557         };
 558
 559         rk_screen: rk_screen{
 560                         compatible = "rockchip,screen";
 561         };
 562
 563         lvds: lvds@ff96c000 {
 564                 compatible = "rockchip, rk32-lvds";
 565                 reg = <0xff960000 0x20000>;
 566                 clocks = <&clk_gates16 7>;
 567                 clock-names = "pclk_lvds";
 568         };
 569
 570         edp: edp@ff970000 {
 571                 compatible = "rockchip,rk32-edp";
 572                 reg = <0xff970000 0x4000>;
 573                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 574                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 575                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 576         };
 577
 578         hdmi: hdmi@ff980000 {
 579                 compatible = "rockchip,rk3288-hdmi";
 580                 reg = <0xff980000 0x20000>;
 581                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 582                 pinctrl-names = "default", "gpio";
 583                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 584                 pinctrl-1 = <&i2c5_gpio>;
 585                 clocks = <&clk_gates16 9>;
 586                 clock-names = "pclk_hdmi";
 587                 status = "disabled";
 588         };
 589
 590         lcdc1: lcdc@ff940000 {
 591                 compatible = "rockchip,rk3288-lcdc";
 592                 rockchip,prop = <PRMRY>;
 593                 rochchip,pwr18 = <0>;
 594                 reg = <0xff940000 0x10000>;
 595                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 596                 pinctrl-names = "default", "gpio";
 597                 pinctrl-0 = <&lcdc0_lcdc>;
 598                 pinctrl-1 = <&lcdc0_gpio>;
 599                 status = "disabled";
 600                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>;
 601                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 602         };
 603
 604         lcdc0: lcdc@ff930000 {
 605                 compatible = "rockchip,rk3288-lcdc";
 606                 rockchip,prop = <EXTEND>;
 607                 rockchip,pwr18 = <0>;
 608                 reg = <0xff930000 0x10000>;
 609                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 610                 //pinctrl-names = "default", "gpio";
 611                 //pinctrl-0 = <&lcdc0_lcdc>;
 612                 //pinctrl-1 = <&lcdc0_gpio>;
 613                 status = "disabled";
 614                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>;
 615                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 616         };
 617
 618         adc: adc@ff100000 {
 619                 compatible = "rockchip,saradc";
 620                 reg = <0xff100000 0x100>;
 621                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 622                 #io-channel-cells = <1>;
 623                 io-channel-ranges;
 624                 rockchip,adc-vref = <1800>;
 625                 clock-frequency = <1000000>;
 626                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 627                 clock-names = "saradc", "pclk_saradc";
 628                 status = "disabled";
 629         };
 630
 631         rga@ff920000 {
 632                 compatible = "rockchip,rga";
 633                 reg = <0xff920000 0x1000>;
 634                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 636                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 637         };
 638
 639         i2s: rockchip-i2s@0xff890000 {
 640                 compatible = "rockchip-i2s";
 641                 reg = <0xff890000 0x10000>;
 642                 i2s-id = <0>;
 643                 clocks = <&clk_i2s>, <&clk_i2s_out>;
 644                 clock-names = "i2s_clk","i2s_mclk";
 645                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 646                 dmas = <&pdma0 0>,
 647                         <&pdma0 1>;
 648                 //#dma-cells = <2>;
 649                 dma-names = "tx", "rx";
 650                 pinctrl-names = "default", "sleep";
 651                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 652                 pinctrl-1 = <&i2s_gpio>;
 653         };
 654
 655         spdif: rockchip-spdif@0xff8b0000 {
 656                 compatible = "rockchip-spdif";
 657                 reg = <0xff8b0000 0x10000>;     //8channel
 658                 //reg = <ff880000 0x10000>;//2channel
 659                 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
 660                 clock-names = "spdif_mclk","spdif_8ch_mclk";
 661                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 662                 dmas = <&pdma0 3>;
 663                 //dmas = <&pdma0 2>; //2channel
 664                 //#dma-cells = <1>;
 665                 dma-names = "tx";
 666                 pinctrl-names = "default";
 667                 pinctrl-0 = <&spdif_tx>;
 668         };
 669
 670         pwm0: pwm@ff680000 {
 671                 compatible = "rockchip,rk-pwm";
 672                 reg = <0xff680000 0x10>;
 673                 #pwm-cells = <2>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&pwm0_pin>;
 676                 clocks = <&clk_gates11 11>;
 677                 clock-names = "pclk_pwm";
 678                 status = "okay";
 679         };
 680
 681         pwm1: pwm@ff680010 {
 682                 compatible = "rockchip,rk-pwm";
 683                 reg = <0xff680010 0x10>;
 684                 #pwm-cells = <2>;
 685                 pinctrl-names = "default";
 686                 pinctrl-0 = <&pwm1_pin>;
 687                 clocks = <&clk_gates11 11>;
 688                 clock-names = "pclk_pwm";
 689                 status = "disabled";
 690         };
 691
 692         pwm2: pwm@ff680020 {
 693                 compatible = "rockchip,rk-pwm";
 694                 reg = <0xff680020 0x10>;
 695                 #pwm-cells = <2>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&pwm2_pin>;
 698                 clocks = <&clk_gates11 11>;
 699                 clock-names = "pclk_pwm";
 700                 status = "disabled";
 701         };
 702
 703         pwm3: pwm@ff680030 {
 704                 compatible = "rockchip,rk-pwm";
 705                 reg = <0xff680030 0x10>;
 706                 #pwm-cells = <2>;
 707                 pinctrl-names = "default";
 708                 pinctrl-0 = <&pwm3_pin>;
 709                 clocks = <&clk_gates11 11>;
 710                 clock-names = "pclk_pwm";
 711                 status = "disabled";
 712         };
 713         dvfs {
 714                 vd_arm:
 715                 vd_arm {
 716                         regulator_name="vdd_arm";
 717                         suspend_volt=<1000>; //mV
 718                         pd_a12 {
 719                                 clk_core_dvfs_table:
 720                                 clk_core {
 721                                         operating-points = <
 722                                                 /* KHz    uV */
 723                                                 312000 1100000
 724                                                 504000 1100000
 725                                                 816000 1100000
 726                                                 1008000 1100000
 727                                                 >;
 728                                         status = "okay";
 729                                 };
 730                         };
 731                 };
 732
 733                 vd_logic:
 734                 vd_logic {
 735                         regulator_name="vdd_logic";
 736                         suspend_volt=<1000>; //mV
 737                         pd_ddr {
 738                                 clk_ddr_dvfs_table:
 739                                 clk_ddr {
 740                                         operating-points = <
 741                                                 /* KHz    uV */
 742                                                 200000 1200000
 743                                                 300000 1200000
 744                                                 400000 1200000
 745                                                 >;
 746                                         status = "disable";
 747                                 };
 748                         };
 749                 };
 750
 751                 vd_gpu:
 752                 vd_gpu {
 753                         regulator_name="vdd_gpu";
 754                         suspend_volt=<1000>; //mV
 755                         pd_gpu {
 756                                 clk_gpu_dvfs_table:
 757                                 clk_gpu {
 758                                         operating-points = <
 759                                                 /* KHz    uV */
 760                                                 200000 1200000
 761                                                 300000 1200000
 762                                                 400000 1200000
 763                                                 >;
 764                                         status = "okay";
 765                                 };
 766                         };
 767                 };
 768         };
 769
 770         ion {
 771                 compatible = "rockchip,ion";
 772                 #address-cells = <1>;
 773                 #size-cells = <0>;
 774                 rockchip,ion-heap@1 { /* CMA HEAP */
 775                         compatible = "rockchip,ion-reserve";
 776                         reg = <1>;
 777                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 778                 };
 779                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 780                         reg = <3>;
 781                 };
 782         };
 783
 784
 785         vpu: vpu_service@ff9a0000 {
 786                 compatible = "vpu_service";
 787                 reg = <0xff9a0000 0x800>;
 788                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 789                 interrupt-names = "irq_enc", "irq_dec";
 790                 clocks = <&clk_vepu>, <&hclk_vepu>;
 791                 clock-names = "aclk_vcodec", "hclk_vcodec";
 792                 name = "vpu_service";
 793                 status = "disabled";
 794         };
 795
 796         hevc: hevc_service@ff9c0000 {
 797                 compatible = "rockchip,hevc_service";
 798                 reg = <0xff9c0000 0x800>;
 799                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 800                 interrupt-names = "irq_dec";
 801                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 802         clock-names = "aclk_hevc", "hclk_hevc", "clk_core", "clk_cabac";
 803                 name = "hevc_service";
 804                 status = "disabled";
 805         };
 806
 807         iep: iep@ff900000 {
 808                 compatible = "rockchip,iep";
 809                 reg = <0xff900000 0x800>;
 810                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 811                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 812                 clock_names = "aclk_iep", "hclk_iep";
 813                 status = "disabled";
 814         };
 815
 816         dwc_control_usb: dwc-control-usb@ff770284 {
 817                 compatible = "rockchip,rk3288-dwc-control-usb";
 818                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 819                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 820                       <0xff770320 0x14>, <0xff770334 0x14>,
 821                       <0xff770348 0x10>, <0xff770358 0x08>,
 822                       <0xff770360 0x08>;
 823                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 824                     "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 825                     "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 826                     "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 827                     "GRF_UOC4_BASE";
 828                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 829                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 830                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 831                 interrupt-names = "otg_id", "otg_bvalid",
 832                           "otg_linestate", "host0_linestate",
 833                           "host1_linestate";
 834                 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
 835                 /*        <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
 836                 /*clocks = <&clk_gates7 9>;*/
 837                 /*clock-names = "hclk_usb_peri";*/
 838                 rockchip,remote_wakeup;
 839                 rockchip,usb_irq_wakeup;
 840
 841                 usb_bc{
 842                         compatible = "rockchip,ctrl";
 843                                         /* offset bit mask */
 844                         rk_usb,bvalid     = <0x288 14 1>;
 845                         rk_usb,dcdenb     = <0x328 14 1>;
 846                         rk_usb,vdatsrcenb = <0x328  7 1>;
 847                         rk_usb,vdatdetenb = <0x328  6 1>;
 848                         rk_usb,chrgsel    = <0x328  5 1>;
 849                         rk_usb,chgdet     = <0x2cc 23 1>;
 850                         rk_usb,fsvminus   = <0x2cc 25 1>;
 851                         rk_usb,fsvplus    = <0x2cc 24 1>;
 852                 };
 853         };
 854
 855         usb0: usb@ff580000 {
 856                 compatible = "rockchip,rk3288_usb20_otg";
 857                 reg = <0xff580000 0x40000>;
 858                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 859                 /*clocks = <&clk_gates13 4>, <&clk_gates7 4>;*/
 860                 /*clock-names = "clk_usbphy0", "hclk_usb0";*/
 861         };
 862
 863         usb1: usb@ff540000 {
 864                 compatible = "rockchip,rk3288_usb20_host";
 865                 reg = <0xff540000 0x40000>;
 866                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 867                 /*clocks = <&clk_gates13 5>, <&clk_gates7 6>;*/
 868                 /*clock-names = "clk_usbphy1", "hclk_usb1";*/
 869         };
 870
 871         usb2: usb@ff500000 {
 872                 compatible = "rockchip,rk3288_usbhs_host";
 873                 reg = <0xff500000 0x40000>;
 874                 /*clocks = <&clk_gates13 6>, <&clk_gates7 7>;*/
 875                 /*clock-names = "clk_usbphy2", "hclk_usb2";*/
 876                 #address-cells = <1>;
 877                 #size-cells = <1>;
 878                 ranges;
 879
 880                 ehci: ehci@ff500000 {
 881                         compatible = "rockchip,rk3288_rk_ehci_host";
 882                         reg = <0xff500000 0x20000>;
 883                         interrupt-parent = <&gic>;
 884                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 885                 };
 886
 887                 ohci: ohci@ff520000 {
 888                         compatible = "rockchip,rk3288_rk_ohci_host";
 889                         reg = <0xff520000 0x20000>;
 890                         interrupt-parent = <&gic>;
 891                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 892                 };
 893         };
 894
 895         hsic: hsic@ff5c0000 {
 896                 compatible = "rockchip,rk3288_rk_hsic_host";
 897                 reg = <0xff5c0000 0x40000>;
 898                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 899                 /*clocks = <&hsicphy_480m>, <&clk_gates7 8>,*/
 900                 /*         <&hsicphy_12m>, <&clk_otgphy1_480m>,*/
 901                 /*         <&clk_otgphy2_480m>;*/
 902                 /*clock-names = "hsicphy_480m", "hclk_hsic",*/
 903                 /*              "hsicphy_12m", "hsic_usbphy1",*/
 904                 /*              "hsic_usbphy2";*/
 905         };
 906
 907         gmac: eth@ff290000 {
 908                 compatible = "rockchip,gmac";
 909                 reg = <0xff290000 0x10000>;
 910                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 911                 interrupt-names = "macirq";
 912                 phy-mode = "rmii";
 913                 //phy-mode = "gmii";
 914                 pinctrl-names = "default";
 915                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 916         };
 917     gpu{
 918         compatible = "arm,malit764",
 919                      "arm,malit76x",
 920                      "arm,malit7xx",
 921                      "arm,mali-midgard";
 922         reg = <0xffa40000 0x1000>;
 923         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 924                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 925                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 926         interrupt-names = "JOB",
 927                           "MMU",
 928                           "GPU";
 929     };
 930
 931     iep_mmu{
 932         dbgname = "iep";
 933         compatible = "iommu,iep_mmu";
 934         reg = <0xffa40000 0x10000>;
 935         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 936         interrupt-names = "iep_mmu";
 937     };
 938
 939     vip_mmu{
 940         dbgname = "vip";
 941         compatible = "iommu,vip_mmu";
 942         reg = <0xffa40000 0x10000>;
 943         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 944         interrupt-names = "vip_mmu";
 945     };
 946
 947     isp0_mmu{
 948         dbgname = "isp0";
 949         compatible = "iommu,isp0_mmu";
 950         reg = <0xffa40000 0x10000>;
 951         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 952         interrupt-names = "isp0_mmu";
 953     };
 954
 955     isp1_mmu{
 956         dbgname = "isp1";
 957         compatible = "iommu,isp1_mmu";
 958         reg = <0xffa40000 0x10000>;
 959         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 960         interrupt-names = "isp1_mmu";
 961     };
 962
 963     vopb_mmu{
 964         dbgname = "vopb";
 965         compatible = "iommu,vopb_mmu";
 966         reg = <0xffa40000 0x10000>;
 967         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 968         interrupt-names = "vopb_mmu";
 969     };
 970
 971     vopl_mmu{
 972         dbgname = "vopl";
 973         compatible = "iommu,vopl_mmu";
 974         reg = <0xffa40000 0x10000>;
 975         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 976         interrupt-names = "vopl_mmu";
 977     };
 978
 979     rockchip_suspend {
 980                     rockchip,ctrbits = <
 981                                     (0
 982                                    // RKPM_CTR_PWR_DMNS
 983                                     //|RKPM_CTR_GTCLKS
 984                                     //|RKPM_CTR_PLLS
 985                                     //|RKPM_CTR_SYSCLK_DIV
 986                                     |RKPM_CTR_NORIDLE_MD
 987                                     )
 988                                 >;
 989                   rockchip,pmic-gpios=<
 990                                                     RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
 991                                                     RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
 992                                                     >;
 993             };
 994
 995 };