arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/suspend/rockchip-rk3288.h>
  50 #include <dt-bindings/display/drm_mipi_dsi.h>
  51 #include "skeleton64.dtsi"
  52
  53 / {
  54         compatible = "rockchip,rk3288";
  55
  56         interrupt-parent = <&gic>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 mshc0 = &emmc;
  67                 mshc1 = &sdmmc;
  68                 mshc2 = &sdio0;
  69                 mshc3 = &sdio1;
  70                 serial0 = &uart0;
  71                 serial1 = &uart1;
  72                 serial2 = &uart2;
  73                 serial3 = &uart3;
  74                 serial4 = &uart4;
  75                 spi0 = &spi0;
  76                 spi1 = &spi1;
  77                 spi2 = &spi2;
  78                 dsi0 = &dsi0;
  79                 dsi1 = &dsi1;
  80         };
  81
  82         arm-pmu {
  83                 compatible = "arm,cortex-a12-pmu";
  84                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  88                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  89         };
  90
  91         cpus {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94                 enable-method = "rockchip,rk3066-smp";
  95                 rockchip,pmu = <&pmu>;
  96
  97                 cpu0: cpu@500 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a12";
 100                         reg = <0x500>;
 101                         resets = <&cru SRST_CORE0>;
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                         #cooling-cells = <2>; /* min followed by max */
 104                         dynamic-power-coefficient = <322>;
 105                         clocks = <&cru ARMCLK>;
 106                 };
 107                 cpu1: cpu@501 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a12";
 110                         reg = <0x501>;
 111                         resets = <&cru SRST_CORE1>;
 112                         operating-points-v2 = <&cpu0_opp_table>;
 113                 };
 114                 cpu2: cpu@502 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a12";
 117                         reg = <0x502>;
 118                         resets = <&cru SRST_CORE2>;
 119                         operating-points-v2 = <&cpu0_opp_table>;
 120                 };
 121                 cpu3: cpu@503 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x503>;
 125                         resets = <&cru SRST_CORE3>;
 126                         operating-points-v2 = <&cpu0_opp_table>;
 127                 };
 128         };
 129
 130         cpu0_opp_table: opp_table0 {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 nvmem-cells = <&cpu_leakage>;
 135                 nvmem-cell-names = "cpu_leakage";
 136
 137                 opp-126000000 {
 138                         opp-hz = /bits/ 64 <126000000>;
 139                         opp-microvolt = <900000>;
 140                         clock-latency-ns = <40000>;
 141                 };
 142                 opp-216000000 {
 143                         opp-hz = /bits/ 64 <216000000>;
 144                         opp-microvolt = <900000>;
 145                         clock-latency-ns = <40000>;
 146                 };
 147                 opp-408000000 {
 148                         opp-hz = /bits/ 64 <408000000>;
 149                         opp-microvolt = <900000>;
 150                         clock-latency-ns = <40000>;
 151                 };
 152                 opp-600000000 {
 153                         opp-hz = /bits/ 64 <600000000>;
 154                         opp-microvolt = <900000>;
 155                         clock-latency-ns = <40000>;
 156                 };
 157                 opp-696000000 {
 158                         opp-hz = /bits/ 64 <696000000>;
 159                         opp-microvolt = <950000>;
 160                         clock-latency-ns = <40000>;
 161                 };
 162                 opp-816000000 {
 163                         opp-hz = /bits/ 64 <816000000>;
 164                         opp-microvolt = <1000000>;
 165                         clock-latency-ns = <40000>;
 166                         opp-suspend;
 167                 };
 168                 opp-1008000000 {
 169                         opp-hz = /bits/ 64 <1008000000>;
 170                         opp-microvolt = <1050000>;
 171                         clock-latency-ns = <40000>;
 172                 };
 173                 opp-1200000000 {
 174                         opp-hz = /bits/ 64 <1200000000>;
 175                         opp-microvolt = <1100000>;
 176                         clock-latency-ns = <40000>;
 177                 };
 178                 opp-1416000000 {
 179                         opp-hz = /bits/ 64 <1416000000>;
 180                         opp-microvolt = <1200000>;
 181                         clock-latency-ns = <40000>;
 182                 };
 183                 opp-1512000000 {
 184                         opp-hz = /bits/ 64 <1512000000>;
 185                         opp-microvolt = <1300000>;
 186                         clock-latency-ns = <40000>;
 187                 };
 188                 opp-1608000000 {
 189                         opp-hz = /bits/ 64 <1608000000>;
 190                         opp-microvolt = <1350000>;
 191                         clock-latency-ns = <40000>;
 192                 };
 193         };
 194
 195         amba {
 196                 compatible = "arm,amba-bus";
 197                 #address-cells = <2>;
 198                 #size-cells = <2>;
 199                 ranges;
 200
 201                 dmac_peri: dma-controller@ff250000 {
 202                         compatible = "arm,pl330", "arm,primecell";
 203                         reg = <0x0 0xff250000 0x0 0x4000>;
 204                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 206                         #dma-cells = <1>;
 207                         arm,pl330-broken-no-flushp;
 208                         peripherals-req-type-burst;
 209                         clocks = <&cru ACLK_DMAC2>;
 210                         clock-names = "apb_pclk";
 211                 };
 212
 213                 dmac_bus_ns: dma-controller@ff600000 {
 214                         compatible = "arm,pl330", "arm,primecell";
 215                         reg = <0x0 0xff600000 0x0 0x4000>;
 216                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 218                         #dma-cells = <1>;
 219                         arm,pl330-broken-no-flushp;
 220                         peripherals-req-type-burst;
 221                         clocks = <&cru ACLK_DMAC1>;
 222                         clock-names = "apb_pclk";
 223                         status = "disabled";
 224                 };
 225
 226                 dmac_bus_s: dma-controller@ffb20000 {
 227                         compatible = "arm,pl330", "arm,primecell";
 228                         reg = <0x0 0xffb20000 0x0 0x4000>;
 229                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 231                         #dma-cells = <1>;
 232                         arm,pl330-broken-no-flushp;
 233                         peripherals-req-type-burst;
 234                         clocks = <&cru ACLK_DMAC1>;
 235                         clock-names = "apb_pclk";
 236                 };
 237         };
 238
 239         reserved-memory {
 240                 #address-cells = <2>;
 241                 #size-cells = <2>;
 242                 ranges;
 243
 244                 /*
 245                  * The rk3288 cannot use the memory area above 0xfe000000
 246                  * for dma operations for some reason. While there is
 247                  * probably a better solution available somewhere, we
 248                  * haven't found it yet and while devices with 2GB of ram
 249                  * are not affected, this issue prevents 4GB from booting.
 250                  * So to make these devices at least bootable, block
 251                  * this area for the time being until the real solution
 252                  * is found.
 253                  */
 254                 dma-unusable@fe000000 {
 255                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 256                 };
 257         };
 258
 259         xin24m: oscillator {
 260                 compatible = "fixed-clock";
 261                 clock-frequency = <24000000>;
 262                 clock-output-names = "xin24m";
 263                 #clock-cells = <0>;
 264         };
 265
 266         timer {
 267                 compatible = "arm,armv7-timer";
 268                 arm,cpu-registers-not-fw-configured;
 269                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 270                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 271                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 272                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 273                 clock-frequency = <24000000>;
 274         };
 275
 276         display-subsystem {
 277                 compatible = "rockchip,display-subsystem";
 278                 ports = <&vopl_out>, <&vopb_out>;
 279         };
 280
 281         sdmmc: dwmmc@ff0c0000 {
 282                 compatible = "rockchip,rk3288-dw-mshc";
 283                 clock-freq-min-max = <400000 150000000>;
 284                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 285                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 286                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 287                 fifo-depth = <0x100>;
 288                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 289                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 290                 status = "disabled";
 291         };
 292
 293         sdio0: dwmmc@ff0d0000 {
 294                 compatible = "rockchip,rk3288-dw-mshc";
 295                 clock-freq-min-max = <400000 150000000>;
 296                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 297                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 298                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 299                 fifo-depth = <0x100>;
 300                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 301                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 302                 status = "disabled";
 303         };
 304
 305         sdio1: dwmmc@ff0e0000 {
 306                 compatible = "rockchip,rk3288-dw-mshc";
 307                 clock-freq-min-max = <400000 150000000>;
 308                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 309                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 310                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 311                 fifo-depth = <0x100>;
 312                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 313                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 314                 status = "disabled";
 315         };
 316
 317         emmc: dwmmc@ff0f0000 {
 318                 compatible = "rockchip,rk3288-dw-mshc";
 319                 clock-freq-min-max = <400000 150000000>;
 320                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 321                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 322                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 323                 fifo-depth = <0x100>;
 324                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 325                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 326                 status = "disabled";
 327                 supports-emmc;
 328         };
 329
 330         saradc: saradc@ff100000 {
 331                 compatible = "rockchip,saradc";
 332                 reg = <0x0 0xff100000 0x0 0x100>;
 333                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 334                 #io-channel-cells = <1>;
 335                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 336                 clock-names = "saradc", "apb_pclk";
 337                 resets = <&cru SRST_SARADC>;
 338                 reset-names = "saradc-apb";
 339                 status = "disabled";
 340         };
 341
 342         spi0: spi@ff110000 {
 343                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 344                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 345                 clock-names = "spiclk", "apb_pclk";
 346                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 347                 dma-names = "tx", "rx";
 348                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 351                 reg = <0x0 0xff110000 0x0 0x1000>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 status = "disabled";
 355         };
 356
 357         spi1: spi@ff120000 {
 358                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 359                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 360                 clock-names = "spiclk", "apb_pclk";
 361                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 362                 dma-names = "tx", "rx";
 363                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 366                 reg = <0x0 0xff120000 0x0 0x1000>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 status = "disabled";
 370         };
 371
 372         spi2: spi@ff130000 {
 373                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 374                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 377                 dma-names = "tx", "rx";
 378                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 381                 reg = <0x0 0xff130000 0x0 0x1000>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         i2c0: i2c@ff650000 {
 388                 compatible = "rockchip,rk3288-i2c";
 389                 reg = <0x0 0xff650000 0x0 0x1000>;
 390                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 clock-names = "i2c";
 394                 clocks = <&cru PCLK_I2C0>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&i2c0_xfer>;
 397                 status = "disabled";
 398         };
 399
 400         i2c1: i2c@ff140000 {
 401                 compatible = "rockchip,rk3288-i2c";
 402                 reg = <0x0 0xff140000 0x0 0x1000>;
 403                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clock-names = "i2c";
 407                 clocks = <&cru PCLK_I2C1>;
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&i2c1_xfer>;
 410                 status = "disabled";
 411         };
 412
 413         i2c3: i2c@ff150000 {
 414                 compatible = "rockchip,rk3288-i2c";
 415                 reg = <0x0 0xff150000 0x0 0x1000>;
 416                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clock-names = "i2c";
 420                 clocks = <&cru PCLK_I2C3>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&i2c3_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         i2c4: i2c@ff160000 {
 427                 compatible = "rockchip,rk3288-i2c";
 428                 reg = <0x0 0xff160000 0x0 0x1000>;
 429                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clock-names = "i2c";
 433                 clocks = <&cru PCLK_I2C4>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&i2c4_xfer>;
 436                 status = "disabled";
 437         };
 438
 439         i2c5: i2c@ff170000 {
 440                 compatible = "rockchip,rk3288-i2c";
 441                 reg = <0x0 0xff170000 0x0 0x1000>;
 442                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 clock-names = "i2c";
 446                 clocks = <&cru PCLK_I2C5>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&i2c5_xfer>;
 449                 status = "disabled";
 450         };
 451
 452         uart0: serial@ff180000 {
 453                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 454                 reg = <0x0 0xff180000 0x0 0x100>;
 455                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 456                 reg-shift = <2>;
 457                 reg-io-width = <4>;
 458                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 459                 clock-names = "baudclk", "apb_pclk";
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&uart0_xfer>;
 462                 status = "disabled";
 463         };
 464
 465         uart1: serial@ff190000 {
 466                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 467                 reg = <0x0 0xff190000 0x0 0x100>;
 468                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 469                 reg-shift = <2>;
 470                 reg-io-width = <4>;
 471                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 472                 clock-names = "baudclk", "apb_pclk";
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart1_xfer>;
 475                 status = "disabled";
 476         };
 477
 478         uart2: serial@ff690000 {
 479                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 480                 reg = <0x0 0xff690000 0x0 0x100>;
 481                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 482                 reg-shift = <2>;
 483                 reg-io-width = <4>;
 484                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 485                 clock-names = "baudclk", "apb_pclk";
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&uart2_xfer>;
 488                 status = "disabled";
 489         };
 490
 491         uart3: serial@ff1b0000 {
 492                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 493                 reg = <0x0 0xff1b0000 0x0 0x100>;
 494                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 495                 reg-shift = <2>;
 496                 reg-io-width = <4>;
 497                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 498                 clock-names = "baudclk", "apb_pclk";
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&uart3_xfer>;
 501                 status = "disabled";
 502         };
 503
 504         uart4: serial@ff1c0000 {
 505                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 506                 reg = <0x0 0xff1c0000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 508                 reg-shift = <2>;
 509                 reg-io-width = <4>;
 510                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 511                 clock-names = "baudclk", "apb_pclk";
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&uart4_xfer>;
 514                 status = "disabled";
 515         };
 516
 517         thermal_zones: thermal-zones {
 518                 soc_thermal: soc-thermal {
 519                         polling-delay-passive = <200>; /* milliseconds */
 520                         polling-delay = <1000>; /* milliseconds */
 521                         sustainable-power = <1200>; /* milliwatts */
 522
 523                         thermal-sensors = <&tsadc 1>;
 524                         trips {
 525                                 threshold: trip-point@0 {
 526                                         temperature = <75000>; /* millicelsius */
 527                                         hysteresis = <2000>; /* millicelsius */
 528                                         type = "passive";
 529                                 };
 530                                 target: trip-point@1 {
 531                                         temperature = <85000>; /* millicelsius */
 532                                         hysteresis = <2000>; /* millicelsius */
 533                                         type = "passive";
 534                                 };
 535                                 soc_crit: soc-crit {
 536                                         temperature = <90000>; /* millicelsius */
 537                                         hysteresis = <2000>; /* millicelsius */
 538                                         type = "critical";
 539                                 };
 540                         };
 541
 542                         cooling-maps {
 543                                 map0 {
 544                                         trip = <&target>;
 545                                         cooling-device =
 546                                         <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 547                                         contribution = <1024>;
 548                                 };
 549                                 map1 {
 550                                         trip = <&target>;
 551                                         cooling-device =
 552                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 553                                         contribution = <1024>;
 554                                 };
 555                         };
 556                 };
 557
 558                 gpu_thermal: gpu-thermal {
 559                         polling-delay-passive = <200>; /* milliseconds */
 560                         polling-delay = <1000>; /* milliseconds */
 561                         thermal-sensors = <&tsadc 2>;
 562                 };
 563         };
 564
 565         tsadc: tsadc@ff280000 {
 566                 compatible = "rockchip,rk3288-tsadc";
 567                 reg = <0x0 0xff280000 0x0 0x100>;
 568                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 569                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 570                 clock-names = "tsadc", "apb_pclk";
 571                 assigned-clocks = <&cru SCLK_TSADC>;
 572                 assigned-clock-rates = <5000>;
 573                 resets = <&cru SRST_TSADC>;
 574                 reset-names = "tsadc-apb";
 575                 pinctrl-names = "init", "default", "sleep";
 576                 pinctrl-0 = <&otp_gpio>;
 577                 pinctrl-1 = <&otp_out>;
 578                 pinctrl-2 = <&otp_gpio>;
 579                 #thermal-sensor-cells = <1>;
 580                 rockchip,hw-tshut-temp = <95000>;
 581                 status = "disabled";
 582         };
 583
 584         gmac: ethernet@ff290000 {
 585                 compatible = "rockchip,rk3288-gmac";
 586                 reg = <0x0 0xff290000 0x0 0x10000>;
 587                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 588                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 589                 interrupt-names = "macirq", "eth_wake_irq";
 590                 rockchip,grf = <&grf>;
 591                 clocks = <&cru SCLK_MAC>,
 592                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 593                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 594                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 595                 clock-names = "stmmaceth",
 596                         "mac_clk_rx", "mac_clk_tx",
 597                         "clk_mac_ref", "clk_mac_refout",
 598                         "aclk_mac", "pclk_mac";
 599                 resets = <&cru SRST_MAC>;
 600                 reset-names = "stmmaceth";
 601                 status = "disabled";
 602         };
 603
 604         usb_host0_ehci: usb@ff500000 {
 605                 compatible = "generic-ehci";
 606                 reg = <0x0 0xff500000 0x0 0x20000>;
 607                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 608                 clocks = <&cru HCLK_USBHOST0>;
 609                 clock-names = "usbhost";
 610                 phys = <&usbphy1>;
 611                 phy-names = "usb";
 612                 status = "disabled";
 613         };
 614
 615         /*
 616          * NOTE: ohci@ff520000 doesn't actually work on rk3288
 617          * hardware, but can work on rk3288w hardware.
 618          */
 619         usb_host0_ohci: usb@ff520000 {
 620                 compatible = "generic-ohci";
 621                 reg = <0x0 0xff520000 0x0 0x20000>;
 622                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&cru HCLK_USBHOST0>;
 624                 clock-names = "usbhost";
 625                 phys = <&usbphy1>;
 626                 phy-names = "usb";
 627                 status = "disabled";
 628         };
 629
 630         usb_host1: usb@ff540000 {
 631                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 632                                 "snps,dwc2";
 633                 reg = <0x0 0xff540000 0x0 0x40000>;
 634                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&cru HCLK_USBHOST1>;
 636                 clock-names = "otg";
 637                 dr_mode = "host";
 638                 phys = <&usbphy2>;
 639                 phy-names = "usb2-phy";
 640                 status = "disabled";
 641         };
 642
 643         usb_otg: usb@ff580000 {
 644                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 645                                 "snps,dwc2";
 646                 reg = <0x0 0xff580000 0x0 0x40000>;
 647                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&cru HCLK_OTG0>;
 649                 clock-names = "otg";
 650                 dr_mode = "otg";
 651                 g-np-tx-fifo-size = <16>;
 652                 g-rx-fifo-size = <275>;
 653                 g-tx-fifo-size = <256 128 128 64 64 32>;
 654                 g-use-dma;
 655                 phys = <&usbphy0>;
 656                 phy-names = "usb2-phy";
 657                 status = "disabled";
 658         };
 659
 660         usb_hsic: usb@ff5c0000 {
 661                 compatible = "generic-ehci";
 662                 reg = <0x0 0xff5c0000 0x0 0x100>;
 663                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 664                 clocks = <&cru HCLK_HSIC>;
 665                 clock-names = "usbhost";
 666                 status = "disabled";
 667         };
 668
 669         dmc: dmc@ff610000 {
 670                 compatible = "rockchip,rk3288-dmc", "syscon";
 671                 rockchip,cru = <&cru>;
 672                 rockchip,grf = <&grf>;
 673                 rockchip,pmu = <&pmu>;
 674                 rockchip,sgrf = <&sgrf>;
 675                 rockchip,noc = <&noc>;
 676                 reg = <0x0 0xff610000 0x0 0x3fc
 677                        0x0 0xff620000 0x0 0x294
 678                        0x0 0xff630000 0x0 0x3fc
 679                        0x0 0xff640000 0x0 0x294>;
 680                 rockchip,sram = <&ddr_sram>;
 681                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 682                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 683                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 684                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 685                               "pclk_ddrupctl1", "pclk_publ1",
 686                               "arm_clk", "aclk_dmac1";
 687         };
 688
 689         i2c2: i2c@ff660000 {
 690                 compatible = "rockchip,rk3288-i2c";
 691                 reg = <0x0 0xff660000 0x0 0x1000>;
 692                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 clock-names = "i2c";
 696                 clocks = <&cru PCLK_I2C2>;
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&i2c2_xfer>;
 699                 status = "disabled";
 700         };
 701
 702         pwm0: pwm@ff680000 {
 703                 compatible = "rockchip,rk3288-pwm";
 704                 reg = <0x0 0xff680000 0x0 0x10>;
 705                 #pwm-cells = <3>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&pwm0_pin>;
 708                 clocks = <&cru PCLK_PWM>;
 709                 clock-names = "pwm";
 710                 status = "disabled";
 711         };
 712
 713         pwm1: pwm@ff680010 {
 714                 compatible = "rockchip,rk3288-pwm";
 715                 reg = <0x0 0xff680010 0x0 0x10>;
 716                 #pwm-cells = <3>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&pwm1_pin>;
 719                 clocks = <&cru PCLK_PWM>;
 720                 clock-names = "pwm";
 721                 status = "disabled";
 722         };
 723
 724         pwm2: pwm@ff680020 {
 725                 compatible = "rockchip,rk3288-pwm";
 726                 reg = <0x0 0xff680020 0x0 0x10>;
 727                 #pwm-cells = <3>;
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&pwm2_pin>;
 730                 clocks = <&cru PCLK_PWM>;
 731                 clock-names = "pwm";
 732                 status = "disabled";
 733         };
 734
 735         pwm3: pwm@ff680030 {
 736                 compatible = "rockchip,rk3288-pwm";
 737                 reg = <0x0 0xff680030 0x0 0x10>;
 738                 #pwm-cells = <2>;
 739                 pinctrl-names = "default";
 740                 pinctrl-0 = <&pwm3_pin>;
 741                 clocks = <&cru PCLK_PWM>;
 742                 clock-names = "pwm";
 743                 status = "disabled";
 744         };
 745
 746         timer: timer@ff6b0000 {
 747                 compatible = "rockchip,rk3288-timer";
 748                 reg = <0x0 0xff6b0000 0x0 0x20>;
 749                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 750                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 751                 clock-names = "timer", "pclk";
 752         };
 753
 754         bus_intmem@ff700000 {
 755                 compatible = "mmio-sram";
 756                 reg = <0x0 0xff700000 0x0 0x18000>;
 757                 #address-cells = <1>;
 758                 #size-cells = <1>;
 759                 ranges = <0 0x0 0xff700000 0x18000>;
 760                 smp-sram@0 {
 761                         compatible = "rockchip,rk3066-smp-sram";
 762                         reg = <0x00 0x10>;
 763                 };
 764                 ddr_sram: ddr-sram@1000 {
 765                         compatible = "rockchip,rk3288-ddr-sram";
 766                         reg = <0x1000 0x4000>;
 767                 };
 768         };
 769
 770         sram@ff720000 {
 771                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 772                 reg = <0x0 0xff720000 0x0 0x1000>;
 773         };
 774
 775         qos_gpu_r: qos@ffaa0000 {
 776                 compatible = "syscon";
 777                 reg = <0x0 0xffaa0000 0x0 0x20>;
 778         };
 779
 780         qos_gpu_w: qos@ffaa0080 {
 781                 compatible = "syscon";
 782                 reg = <0x0 0xffaa0080 0x0 0x20>;
 783         };
 784
 785         qos_vio1_vop: qos@ffad0000 {
 786                 compatible = "syscon";
 787                 reg = <0x0 0xffad0000 0x0 0x20>;
 788         };
 789
 790         qos_vio1_isp_w0: qos@ffad0100 {
 791                 compatible = "syscon";
 792                 reg = <0x0 0xffad0100 0x0 0x20>;
 793         };
 794
 795         qos_vio1_isp_w1: qos@ffad0180 {
 796                 compatible = "syscon";
 797                 reg = <0x0 0xffad0180 0x0 0x20>;
 798         };
 799
 800         qos_vio0_vop: qos@ffad0400 {
 801                 compatible = "syscon";
 802                 reg = <0x0 0xffad0400 0x0 0x20>;
 803         };
 804
 805         qos_vio0_vip: qos@ffad0480 {
 806                 compatible = "syscon";
 807                 reg = <0x0 0xffad0480 0x0 0x20>;
 808         };
 809
 810         qos_vio0_iep: qos@ffad0500 {
 811                 compatible = "syscon";
 812                 reg = <0x0 0xffad0500 0x0 0x20>;
 813         };
 814
 815         qos_vio2_rga_r: qos@ffad0800 {
 816                 compatible = "syscon";
 817                 reg = <0x0 0xffad0800 0x0 0x20>;
 818         };
 819
 820         qos_vio2_rga_w: qos@ffad0880 {
 821                 compatible = "syscon";
 822                 reg = <0x0 0xffad0880 0x0 0x20>;
 823         };
 824
 825         qos_vio1_isp_r: qos@ffad0900 {
 826                 compatible = "syscon";
 827                 reg = <0x0 0xffad0900 0x0 0x20>;
 828         };
 829
 830         qos_video: qos@ffae0000 {
 831                 compatible = "syscon";
 832                 reg = <0x0 0xffae0000 0x0 0x20>;
 833         };
 834
 835         qos_hevc_r: qos@ffaf0000 {
 836                 compatible = "syscon";
 837                 reg = <0x0 0xffaf0000 0x0 0x20>;
 838         };
 839
 840         qos_hevc_w: qos@ffaf0080 {
 841                 compatible = "syscon";
 842                 reg = <0x0 0xffaf0080 0x0 0x20>;
 843         };
 844
 845         pmu: power-management@ff730000 {
 846                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 847                 reg = <0x0 0xff730000 0x0 0x100>;
 848
 849                 power: power-controller {
 850                         compatible = "rockchip,rk3288-power-controller";
 851                         #power-domain-cells = <1>;
 852                         #address-cells = <1>;
 853                         #size-cells = <0>;
 854
 855                         /*
 856                          * Note: Although SCLK_* are the working clocks
 857                          * of device without including on the NOC, needed for
 858                          * synchronous reset.
 859                          *
 860                          * The clocks on the which NOC:
 861                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 862                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 863                          * ACLK_RGA is on ACLK_RGA_NIU.
 864                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 865                          *
 866                          * Which clock are device clocks:
 867                          *      clocks          devices
 868                          *      *_IEP           IEP:Image Enhancement Processor
 869                          *      *_ISP           ISP:Image Signal Processing
 870                          *      *_VIP           VIP:Video Input Processor
 871                          *      *_VOP*          VOP:Visual Output Processor
 872                          *      *_RGA           RGA
 873                          *      *_EDP*          EDP
 874                          *      *_LVDS_*        LVDS
 875                          *      *_HDMI          HDMI
 876                          *      *_MIPI_*        MIPI
 877                          */
 878                         pd_vio@RK3288_PD_VIO {
 879                                 reg = <RK3288_PD_VIO>;
 880                                 clocks = <&cru ACLK_IEP>,
 881                                          <&cru ACLK_ISP>,
 882                                          <&cru ACLK_RGA>,
 883                                          <&cru ACLK_VIP>,
 884                                          <&cru ACLK_VOP0>,
 885                                          <&cru ACLK_VOP1>,
 886                                          <&cru DCLK_VOP0>,
 887                                          <&cru DCLK_VOP1>,
 888                                          <&cru HCLK_IEP>,
 889                                          <&cru HCLK_ISP>,
 890                                          <&cru HCLK_RGA>,
 891                                          <&cru HCLK_VIP>,
 892                                          <&cru HCLK_VOP0>,
 893                                          <&cru HCLK_VOP1>,
 894                                          <&cru PCLK_EDP_CTRL>,
 895                                          <&cru PCLK_HDMI_CTRL>,
 896                                          <&cru PCLK_LVDS_PHY>,
 897                                          <&cru PCLK_MIPI_CSI>,
 898                                          <&cru PCLK_MIPI_DSI0>,
 899                                          <&cru PCLK_MIPI_DSI1>,
 900                                          <&cru SCLK_EDP_24M>,
 901                                          <&cru SCLK_EDP>,
 902                                          <&cru SCLK_ISP_JPE>,
 903                                          <&cru SCLK_ISP>,
 904                                          <&cru SCLK_RGA>;
 905                                 pm_qos = <&qos_vio0_iep>,
 906                                          <&qos_vio1_vop>,
 907                                          <&qos_vio1_isp_w0>,
 908                                          <&qos_vio1_isp_w1>,
 909                                          <&qos_vio0_vop>,
 910                                          <&qos_vio0_vip>,
 911                                          <&qos_vio2_rga_r>,
 912                                          <&qos_vio2_rga_w>,
 913                                          <&qos_vio1_isp_r>;
 914                         };
 915
 916                         /*
 917                          * Note: The following 3 are HEVC(H.265) clocks,
 918                          * and on the ACLK_HEVC_NIU (NOC).
 919                          */
 920                         pd_hevc@RK3288_PD_HEVC {
 921                                 reg = <RK3288_PD_HEVC>;
 922                                 clocks = <&cru ACLK_HEVC>,
 923                                          <&cru SCLK_HEVC_CABAC>,
 924                                          <&cru SCLK_HEVC_CORE>;
 925                                 pm_qos = <&qos_hevc_r>,
 926                                          <&qos_hevc_w>;
 927                         };
 928
 929                         /*
 930                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 931                          * (video endecoder & decoder) clocks that on the
 932                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 933                          */
 934                         pd_video@RK3288_PD_VIDEO {
 935                                 reg = <RK3288_PD_VIDEO>;
 936                                 clocks = <&cru ACLK_VCODEC>,
 937                                          <&cru HCLK_VCODEC>;
 938                                 pm_qos = <&qos_video>;
 939                         };
 940
 941                         /*
 942                          * Note: ACLK_GPU is the GPU clock,
 943                          * and on the ACLK_GPU_NIU (NOC).
 944                          */
 945                         pd_gpu@RK3288_PD_GPU {
 946                                 reg = <RK3288_PD_GPU>;
 947                                 clocks = <&cru ACLK_GPU>;
 948                                 pm_qos = <&qos_gpu_r>,
 949                                          <&qos_gpu_w>;
 950                         };
 951                 };
 952
 953                 reboot-mode {
 954                         compatible = "syscon-reboot-mode";
 955                         offset = <0x94>;
 956                         mode-normal = <BOOT_NORMAL>;
 957                         mode-recovery = <BOOT_RECOVERY>;
 958                         mode-bootloader = <BOOT_FASTBOOT>;
 959                         mode-loader = <BOOT_BL_DOWNLOAD>;
 960                         mode-ums = <BOOT_UMS>;
 961                 };
 962         };
 963
 964         sgrf: syscon@ff740000 {
 965                 compatible = "rockchip,rk3288-sgrf", "syscon";
 966                 reg = <0x0 0xff740000 0x0 0x1000>;
 967         };
 968
 969         cru: clock-controller@ff760000 {
 970                 compatible = "rockchip,rk3288-cru";
 971                 reg = <0x0 0xff760000 0x0 0x1000>;
 972                 rockchip,grf = <&grf>;
 973                 #clock-cells = <1>;
 974                 #reset-cells = <1>;
 975                 assigned-clocks = <&cru PLL_GPLL>,
 976                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 977                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 978                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 979                                   <&cru PCLK_PERI>;
 980                 assigned-clock-rates = <594000000>,
 981                                        <500000000>, <300000000>,
 982                                        <150000000>, <75000000>,
 983                                        <300000000>, <150000000>,
 984                                        <75000000>;
 985         };
 986
 987         grf: syscon@ff770000 {
 988                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 989                 reg = <0x0 0xff770000 0x0 0x1000>;
 990
 991                 edp_phy: edp-phy {
 992                         compatible = "rockchip,rk3288-dp-phy";
 993                         clocks = <&cru SCLK_EDP_24M>;
 994                         clock-names = "24m";
 995                         #phy-cells = <0>;
 996                         status = "disabled";
 997                 };
 998
 999                 io_domains: io-domains {
1000                         compatible = "rockchip,rk3288-io-voltage-domain";
1001                         status = "disabled";
1002                 };
1003
1004                 usbphy: usbphy {
1005                         compatible = "rockchip,rk3288-usb-phy";
1006                         #address-cells = <1>;
1007                         #size-cells = <0>;
1008                         status = "disabled";
1009
1010                         usbphy0: usb-phy@320 {
1011                                 #phy-cells = <0>;
1012                                 reg = <0x320>;
1013                                 clocks = <&cru SCLK_OTGPHY0>;
1014                                 clock-names = "phyclk";
1015                                 #clock-cells = <0>;
1016                                 resets = <&cru SRST_USBOTG_PHY>;
1017                                 reset-names = "phy-reset";
1018                         };
1019
1020                         usbphy1: usb-phy@334 {
1021                                 #phy-cells = <0>;
1022                                 reg = <0x334>;
1023                                 clocks = <&cru SCLK_OTGPHY1>;
1024                                 clock-names = "phyclk";
1025                                 #clock-cells = <0>;
1026                         };
1027
1028                         usbphy2: usb-phy@348 {
1029                                 #phy-cells = <0>;
1030                                 reg = <0x348>;
1031                                 clocks = <&cru SCLK_OTGPHY2>;
1032                                 clock-names = "phyclk";
1033                                 #clock-cells = <0>;
1034                                 resets = <&cru SRST_USBHOST1_PHY>;
1035                                 reset-names = "phy-reset";
1036                         };
1037                 };
1038         };
1039
1040         wdt: watchdog@ff800000 {
1041                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1042                 reg = <0x0 0xff800000 0x0 0x100>;
1043                 clocks = <&cru PCLK_WDT>;
1044                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1045                 status = "disabled";
1046         };
1047
1048         spdif: sound@ff8b0000 {
1049                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1050                 reg = <0x0 0xff8b0000 0x0 0x10000>;
1051                 #sound-dai-cells = <0>;
1052                 clock-names = "hclk", "mclk";
1053                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1054                 dmas = <&dmac_bus_s 3>;
1055                 dma-names = "tx";
1056                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1057                 pinctrl-names = "default";
1058                 pinctrl-0 = <&spdif_tx>;
1059                 rockchip,grf = <&grf>;
1060                 status = "disabled";
1061         };
1062
1063         i2s: i2s@ff890000 {
1064                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1065                 reg = <0x0 0xff890000 0x0 0x10000>;
1066                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1067                 #address-cells = <1>;
1068                 #size-cells = <0>;
1069                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1070                 dma-names = "tx", "rx";
1071                 clock-names = "i2s_hclk", "i2s_clk";
1072                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1073                 pinctrl-names = "default";
1074                 pinctrl-0 = <&i2s0_bus>;
1075                 rockchip,playback-channels = <8>;
1076                 rockchip,capture-channels = <2>;
1077                 status = "disabled";
1078         };
1079
1080         iep: iep@ff90000 {
1081                 compatible = "rockchip,iep";
1082                 iommu_enabled = <1>;
1083                 iommus = <&iep_mmu>;
1084                 reg = <0x0 0xff900000 0x0 0x800>;
1085                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1086                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1087                 clock-names = "aclk_iep", "hclk_iep";
1088                 power-domains = <&power RK3288_PD_VIO>;
1089                 allocator = <1>;
1090                 version = <1>;
1091                 status = "disabled";
1092         };
1093
1094         iep_mmu: iommu@ff900800 {
1095                 compatible = "rockchip,iommu";
1096                 reg = <0x0 0xff900800 0x0 0x40>;
1097                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1098                 interrupt-names = "iep_mmu";
1099                 #iommu-cells = <0>;
1100                 status = "disabled";
1101         };
1102
1103         cif_isp0: cif_isp@ff910000 {
1104                 compatible = "rockchip,rk3288-cif-isp";
1105                 rockchip,grf = <&grf>;
1106                 reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1107                 reg-names = "register", "csihost-register";
1108                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1109                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1110                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1111                         <&cru SCLK_MIPIDSI_24M>;
1112                 clock-names = "aclk_isp", "hclk_isp",
1113                         "sclk_isp", "sclk_isp_jpe",
1114                         "pclk_mipi_csi", "pclk_isp_in",
1115                         "sclk_mipidsi_24m";
1116                 resets = <&cru SRST_ISP>;
1117                 reset-names = "rst_isp";
1118                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1119                 interrupt-names = "cif_isp10_irq";
1120                 power-domains = <&power RK3288_PD_VIO>;
1121                 rockchip,isp,iommu-enable = <1>;
1122                 iommus = <&isp_mmu>;
1123                 status = "disabled";
1124         };
1125
1126         isp: isp@ff910000 {
1127                 compatible = "rockchip,rk3288-isp", "rockchip,isp";
1128                 reg = <0x0 0xff910000 0x0 0x4000>;
1129                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1130                 power-domains = <&power RK3288_PD_VIO>;
1131                 clocks =
1132                         <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1133                         <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
1134                         <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
1135                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
1136                 clock-names =
1137                         "aclk_isp", "hclk_isp", "clk_isp",
1138                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1139                         "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
1140                 pinctrl-names =
1141                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1142                         "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
1143                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
1144                         "isp_flash_as_trigger_out";
1145                 pinctrl-0 = <&isp_mipi>;
1146                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1147                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1148                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1149                                         &isp_dvp_d10d11>;
1150                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1151                 pinctrl-5 = <&isp_mipi>;
1152                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1153                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1154                 pinctrl-8 = <&isp_flash_trigger>;
1155                 rockchip,isp,mipiphy = <2>;
1156                 rockchip,isp,cifphy = <1>;
1157                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1158                 rockchip,grf = <&grf>;
1159                 rockchip,cru = <&cru>;
1160                 rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
1161                 rockchip,isp,iommu_enable = <1>;
1162                 iommus = <&isp_mmu>;
1163                 status = "disabled";
1164         };
1165
1166         isp_mmu: iommu@ff914000 {
1167                 compatible = "rockchip,iommu";
1168                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1169                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1170                 interrupt-names = "isp_mmu";
1171                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1172                 clock-names = "aclk", "hclk";
1173                 rk_iommu,disable_reset_quirk;
1174                 #iommu-cells = <0>;
1175                 power-domains = <&power RK3288_PD_VIO>;
1176                 status = "disabled";
1177         };
1178
1179         rga: rga@ff920000 {
1180                 compatible = "rockchip,rk3288-rga";
1181                 reg = <0x0 0xff920000 0x0 0x180>;
1182                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1183                 interrupt-names = "rga";
1184                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1185                 clock-names = "aclk", "hclk", "sclk";
1186                 power-domains = <&power RK3288_PD_VIO>;
1187                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1188                 reset-names = "core", "axi", "ahb";
1189                 dma-coherent;
1190                 status = "disabled";
1191         };
1192
1193         vopb: vop@ff930000 {
1194                 compatible = "rockchip,rk3288-vop";
1195                 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1196                 reg-names = "regs", "gamma_lut";
1197                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1198                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1199                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1200                 power-domains = <&power RK3288_PD_VIO>;
1201                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1202                 reset-names = "axi", "ahb", "dclk";
1203                 iommus = <&vopb_mmu>;
1204                 status = "disabled";
1205
1206                 vopb_out: port {
1207                         #address-cells = <1>;
1208                         #size-cells = <0>;
1209
1210                         vopb_out_hdmi: endpoint@0 {
1211                                 reg = <0>;
1212                                 remote-endpoint = <&hdmi_in_vopb>;
1213                         };
1214
1215                         vopb_out_edp: endpoint@1 {
1216                                 reg = <1>;
1217                                 remote-endpoint = <&edp_in_vopb>;
1218                         };
1219
1220                         vopb_out_dsi0: endpoint@2 {
1221                                 reg = <2>;
1222                                 remote-endpoint = <&dsi0_in_vopb>;
1223                         };
1224
1225                         vopb_out_lvds: endpoint@3 {
1226                                 reg = <3>;
1227                                 remote-endpoint = <&lvds_in_vopb>;
1228                         };
1229
1230                         vopb_out_dsi1: endpoint@4 {
1231                                 reg = <4>;
1232                                 remote-endpoint = <&dsi1_in_vopb>;
1233                         };
1234                 };
1235         };
1236
1237         vopb_mmu: iommu@ff930300 {
1238                 compatible = "rockchip,iommu";
1239                 reg = <0x0 0xff930300 0x0 0x100>;
1240                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1241                 interrupt-names = "vopb_mmu";
1242                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1243                 clock-names = "aclk", "hclk";
1244                 power-domains = <&power RK3288_PD_VIO>;
1245                 #iommu-cells = <0>;
1246                 status = "disabled";
1247         };
1248
1249         vopl: vop@ff940000 {
1250                 compatible = "rockchip,rk3288-vop";
1251                 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1252                 reg-names = "regs", "gamma_lut";
1253                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1254                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1255                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1256                 power-domains = <&power RK3288_PD_VIO>;
1257                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1258                 reset-names = "axi", "ahb", "dclk";
1259                 iommus = <&vopl_mmu>;
1260                 status = "disabled";
1261
1262                 vopl_out: port {
1263                         #address-cells = <1>;
1264                         #size-cells = <0>;
1265
1266                         vopl_out_hdmi: endpoint@0 {
1267                                 reg = <0>;
1268                                 remote-endpoint = <&hdmi_in_vopl>;
1269                         };
1270
1271                         vopl_out_edp: endpoint@1 {
1272                                 reg = <1>;
1273                                 remote-endpoint = <&edp_in_vopl>;
1274                         };
1275
1276                         vopl_out_dsi0: endpoint@2 {
1277                                 reg = <2>;
1278                                 remote-endpoint = <&dsi0_in_vopl>;
1279                         };
1280
1281                         vopl_out_lvds: endpoint@3 {
1282                                 reg = <3>;
1283                                 remote-endpoint = <&lvds_in_vopl>;
1284                         };
1285
1286                         vopl_out_dsi1: endpoint@4 {
1287                                 reg = <4>;
1288                                 remote-endpoint = <&dsi1_in_vopl>;
1289                         };
1290                 };
1291         };
1292
1293         vopl_mmu: iommu@ff940300 {
1294                 compatible = "rockchip,iommu";
1295                 reg = <0x0 0xff940300 0x0 0x100>;
1296                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1297                 interrupt-names = "vopl_mmu";
1298                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1299                 clock-names = "aclk", "hclk";
1300                 power-domains = <&power RK3288_PD_VIO>;
1301                 #iommu-cells = <0>;
1302                 status = "disabled";
1303         };
1304
1305         dsi0: dsi@ff960000 {
1306                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1307                 reg = <0x0 0xff960000 0x0 0x4000>;
1308                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1309                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1310                 clock-names = "ref", "pclk";
1311                 power-domains = <&power RK3288_PD_VIO>;
1312                 rockchip,grf = <&grf>;
1313                 #address-cells = <1>;
1314                 #size-cells = <0>;
1315                 status = "disabled";
1316
1317                 ports {
1318                         #address-cells = <1>;
1319                         #size-cells = <0>;
1320
1321                         dsi0_in: port {
1322                                 #address-cells = <1>;
1323                                 #size-cells = <0>;
1324
1325                                 dsi0_in_vopb: endpoint@0 {
1326                                         reg = <0>;
1327                                         remote-endpoint = <&vopb_out_dsi0>;
1328                                 };
1329                                 dsi0_in_vopl: endpoint@1 {
1330                                         reg = <1>;
1331                                         remote-endpoint = <&vopl_out_dsi0>;
1332                                 };
1333                         };
1334                 };
1335         };
1336
1337         dsi1: dsi@ff964000 {
1338                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1339                 reg = <0x0 0xff964000 0x0 0x4000>;
1340                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1341                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>;
1342                 clock-names = "ref", "pclk";
1343                 power-domains = <&power RK3288_PD_VIO>;
1344                 rockchip,grf = <&grf>;
1345                 #address-cells = <1>;
1346                 #size-cells = <0>;
1347                 status = "disabled";
1348
1349                 ports {
1350                         #address-cells = <1>;
1351                         #size-cells = <0>;
1352
1353                         dsi1_in: port {
1354                                 #address-cells = <1>;
1355                                 #size-cells = <0>;
1356
1357                                 dsi1_in_vopb: endpoint@0 {
1358                                         reg = <0>;
1359                                         remote-endpoint = <&vopb_out_dsi1>;
1360                                 };
1361                                 dsi1_in_vopl: endpoint@1 {
1362                                         reg = <1>;
1363                                         remote-endpoint = <&vopl_out_dsi1>;
1364                                 };
1365                         };
1366                 };
1367         };
1368
1369         edp: dp@ff970000 {
1370                 compatible = "rockchip,rk3288-dp";
1371                 reg = <0x0 0xff970000 0x0 0x4000>;
1372                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1373                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1374                 clock-names = "dp", "pclk";
1375                 power-domains = <&power RK3288_PD_VIO>;
1376                 phys = <&edp_phy>;
1377                 phy-names = "dp";
1378                 resets = <&cru SRST_EDP>;
1379                 reset-names = "dp";
1380                 rockchip,grf = <&grf>;
1381                 status = "disabled";
1382
1383                 ports {
1384                         #address-cells = <1>;
1385                         #size-cells = <0>;
1386                         edp_in: port@0 {
1387                                 reg = <0>;
1388                                 #address-cells = <1>;
1389                                 #size-cells = <0>;
1390                                 edp_in_vopb: endpoint@0 {
1391                                         reg = <0>;
1392                                         remote-endpoint = <&vopb_out_edp>;
1393                                 };
1394                                 edp_in_vopl: endpoint@1 {
1395                                         reg = <1>;
1396                                         remote-endpoint = <&vopl_out_edp>;
1397                                 };
1398                         };
1399                 };
1400         };
1401
1402         lvds: lvds@ff96c000 {
1403                 compatible = "rockchip,rk3288-lvds";
1404                 reg = <0x0 0xff96c000 0x0 0x4000>;
1405                 clocks = <&cru PCLK_LVDS_PHY>;
1406                 clock-names = "pclk_lvds";
1407                 pinctrl-names = "default";
1408                 pinctrl-0 = <&lcdc0_ctl>;
1409                 power-domains = <&power RK3288_PD_VIO>;
1410                 rockchip,grf = <&grf>;
1411                 status = "disabled";
1412
1413                 ports {
1414                         #address-cells = <1>;
1415                         #size-cells = <0>;
1416
1417                         lvds_in: port@0 {
1418                                 reg = <0>;
1419
1420                                 #address-cells = <1>;
1421                                 #size-cells = <0>;
1422
1423                                 lvds_in_vopb: endpoint@0 {
1424                                         reg = <0>;
1425                                         remote-endpoint = <&vopb_out_lvds>;
1426                                 };
1427                                 lvds_in_vopl: endpoint@1 {
1428                                         reg = <1>;
1429                                         remote-endpoint = <&vopl_out_lvds>;
1430                                 };
1431                         };
1432                 };
1433         };
1434
1435         hdmi: hdmi@ff980000 {
1436                 compatible = "rockchip,rk3288-dw-hdmi";
1437                 reg = <0x0 0xff980000 0x0 0x20000>;
1438                 reg-io-width = <4>;
1439                 rockchip,grf = <&grf>;
1440                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1441                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1442                 clock-names = "iahb", "isfr";
1443                 pinctrl-names = "default";
1444                 pinctrl-0 = <&hdmi_ddc>;
1445                 power-domains = <&power RK3288_PD_VIO>;
1446                 status = "disabled";
1447
1448                 ports {
1449                         hdmi_in: port {
1450                                 #address-cells = <1>;
1451                                 #size-cells = <0>;
1452                                 hdmi_in_vopb: endpoint@0 {
1453                                         reg = <0>;
1454                                         remote-endpoint = <&vopb_out_hdmi>;
1455                                 };
1456                                 hdmi_in_vopl: endpoint@1 {
1457                                         reg = <1>;
1458                                         remote-endpoint = <&vopl_out_hdmi>;
1459                                 };
1460                         };
1461                 };
1462         };
1463
1464         vpu: video-codec@ff9a0000 {
1465                 compatible = "rockchip,rk3288-vpu";
1466                 reg = <0x0 0xff9a0000 0x0 0x800>;
1467                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1468                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1469                 interrupt-names = "vepu", "vdpu";
1470                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1471                 clock-names = "aclk", "hclk";
1472                 power-domains = <&power RK3288_PD_VIDEO>;
1473                 iommus = <&vpu_mmu>;
1474                 assigned-clocks = <&cru ACLK_VCODEC>;
1475                 assigned-clock-rates = <400000000>;
1476                 status = "disabled";
1477         };
1478
1479         vpu_service: vpu-service@ff9a0000 {
1480                 compatible = "rockchip,vpu_service";
1481                 reg = <0x0 0xff9a0000 0x0 0x800>;
1482                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1483                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1484                 interrupt-names = "irq_enc", "irq_dec";
1485                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1486                 clock-names = "aclk_vcodec", "hclk_vcodec";
1487                 power-domains = <&power RK3288_PD_VIDEO>;
1488                 rockchip,grf = <&grf>;
1489                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1490                 reset-names = "video_a", "video_h";
1491                 iommus = <&vpu_mmu>;
1492                 iommu_enabled = <1>;
1493                 status = "disabled";
1494                 /* 0 means ion, 1 means drm */
1495                 allocator = <1>;
1496         };
1497
1498         vpu_mmu: iommu@ff9a0800 {
1499                 compatible = "rockchip,iommu";
1500                 reg = <0x0 0xff9a0800 0x0 0x100>;
1501                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1502                 interrupt-names = "vpu_mmu";
1503                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1504                 clock-names = "aclk", "hclk";
1505                 power-domains = <&power RK3288_PD_VIDEO>;
1506                 #iommu-cells = <0>;
1507         };
1508
1509         hevc_service: hevc-service@ff9c0000 {
1510                 compatible = "rockchip,hevc_service";
1511                 reg = <0x0 0xff9c0000 0x0 0x400>;
1512                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1513                 interrupt-names = "irq_dec";
1514                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1515                         <&cru SCLK_HEVC_CORE>,
1516                         <&cru SCLK_HEVC_CABAC>;
1517                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1518                         "clk_cabac";
1519                 /*
1520                  * The 4K hevc would also work well with 500/125/300/300,
1521                  * no more err irq and reset request.
1522                  */
1523                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1524                                   <&cru SCLK_HEVC_CORE>,
1525                                   <&cru SCLK_HEVC_CABAC>;
1526                 assigned-clock-rates = <400000000>, <100000000>,
1527                                        <300000000>, <300000000>;
1528
1529                 resets = <&cru SRST_HEVC>;
1530                 reset-names = "video";
1531                 power-domains = <&power RK3288_PD_HEVC>;
1532                 rockchip,grf = <&grf>;
1533                 iommus = <&hevc_mmu>;
1534                 iommu_enabled = <1>;
1535                 status = "disabled";
1536                 /* 0 means ion, 1 means drm */
1537                 allocator = <1>;
1538         };
1539
1540         hevc_mmu: iommu@ff9c0440 {
1541                 compatible = "rockchip,iommu";
1542                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1543                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1544                 interrupt-names = "hevc_mmu";
1545                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1546                         <&cru SCLK_HEVC_CORE>,
1547                         <&cru SCLK_HEVC_CABAC>;
1548                 clock-names = "aclk", "hclk", "clk_core",
1549                         "clk_cabac";
1550                 power-domains = <&power RK3288_PD_HEVC>;
1551                 #iommu-cells = <0>;
1552         };
1553
1554         gpu: gpu@ffa30000 {
1555                 compatible = "arm,malit764",
1556                              "arm,malit76x",
1557                              "arm,malit7xx",
1558                              "arm,mali-midgard";
1559                 reg = <0x0 0xffa30000 0x0 0x10000>;
1560                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1561                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1562                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1563                 interrupt-names = "JOB", "MMU", "GPU";
1564                 clocks = <&cru ACLK_GPU>;
1565                 clock-names = "clk_mali";
1566                 operating-points-v2 = <&gpu_opp_table>;
1567                 #cooling-cells = <2>; /* min followed by max */
1568                 power-domains = <&power RK3288_PD_GPU>;
1569                 status = "disabled";
1570
1571                 upthreshold = <75>;
1572                 downdifferential = <10>;
1573
1574                 gpu_power_model: power_model {
1575                         compatible = "arm,mali-simple-power-model";
1576                         voltage = <950>;
1577                         frequency = <500>;
1578                         static-power = <300>;
1579                         dynamic-power = <396>;
1580                         ts = <32000 4700 (-80) 2>;
1581                         thermal-zone = "gpu-thermal";
1582                 };
1583         };
1584
1585         gpu_opp_table: opp-table1 {
1586                 compatible = "operating-points-v2";
1587
1588                 opp-100000000 {
1589                         opp-hz = /bits/ 64 <100000000>;
1590                         opp-microvolt = <950000>;
1591                 };
1592                 opp-200000000 {
1593                         opp-hz = /bits/ 64 <200000000>;
1594                         opp-microvolt = <950000>;
1595                 };
1596                 opp-300000000 {
1597                         opp-hz = /bits/ 64 <300000000>;
1598                         opp-microvolt = <1000000>;
1599                 };
1600                 opp-400000000 {
1601                         opp-hz = /bits/ 64 <400000000>;
1602                         opp-microvolt = <1100000>;
1603                 };
1604                 opp-600000000 {
1605                         opp-hz = /bits/ 64 <600000000>;
1606                         opp-microvolt = <1250000>;
1607                 };
1608         };
1609
1610         noc: syscon@ffac0000 {
1611                 compatible = "rockchip,rk3288-noc", "syscon";
1612                 reg = <0x0 0xffac0000 0x0 0x2000>;
1613         };
1614
1615         efuse: efuse@ffb40000 {
1616                 compatible = "rockchip,rockchip-efuse";
1617                 reg = <0x0 0xffb40000 0x0 0x20>;
1618                 #address-cells = <1>;
1619                 #size-cells = <1>;
1620                 clocks = <&cru PCLK_EFUSE256>;
1621                 clock-names = "pclk_efuse";
1622
1623                 cpu_leakage: cpu_leakage@17 {
1624                         reg = <0x17 0x1>;
1625                 };
1626         };
1627
1628         gic: interrupt-controller@ffc01000 {
1629                 compatible = "arm,gic-400";
1630                 interrupt-controller;
1631                 #interrupt-cells = <3>;
1632                 #address-cells = <0>;
1633
1634                 reg = <0x0 0xffc01000 0x0 0x1000>,
1635                       <0x0 0xffc02000 0x0 0x2000>,
1636                       <0x0 0xffc04000 0x0 0x2000>,
1637                       <0x0 0xffc06000 0x0 0x2000>;
1638                 interrupts = <GIC_PPI 9 0xf04>;
1639         };
1640
1641         pinctrl: pinctrl {
1642                 compatible = "rockchip,rk3288-pinctrl";
1643                 rockchip,grf = <&grf>;
1644                 rockchip,pmu = <&pmu>;
1645                 #address-cells = <2>;
1646                 #size-cells = <2>;
1647                 ranges;
1648
1649                 gpio0: gpio0@ff750000 {
1650                         compatible = "rockchip,gpio-bank";
1651                         reg = <0x0 0xff750000 0x0 0x100>;
1652                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1653                         clocks = <&cru PCLK_GPIO0>;
1654
1655                         gpio-controller;
1656                         #gpio-cells = <2>;
1657
1658                         interrupt-controller;
1659                         #interrupt-cells = <2>;
1660                 };
1661
1662                 gpio1: gpio1@ff780000 {
1663                         compatible = "rockchip,gpio-bank";
1664                         reg = <0x0 0xff780000 0x0 0x100>;
1665                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1666                         clocks = <&cru PCLK_GPIO1>;
1667
1668                         gpio-controller;
1669                         #gpio-cells = <2>;
1670
1671                         interrupt-controller;
1672                         #interrupt-cells = <2>;
1673                 };
1674
1675                 gpio2: gpio2@ff790000 {
1676                         compatible = "rockchip,gpio-bank";
1677                         reg = <0x0 0xff790000 0x0 0x100>;
1678                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1679                         clocks = <&cru PCLK_GPIO2>;
1680
1681                         gpio-controller;
1682                         #gpio-cells = <2>;
1683
1684                         interrupt-controller;
1685                         #interrupt-cells = <2>;
1686                 };
1687
1688                 gpio3: gpio3@ff7a0000 {
1689                         compatible = "rockchip,gpio-bank";
1690                         reg = <0x0 0xff7a0000 0x0 0x100>;
1691                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1692                         clocks = <&cru PCLK_GPIO3>;
1693
1694                         gpio-controller;
1695                         #gpio-cells = <2>;
1696
1697                         interrupt-controller;
1698                         #interrupt-cells = <2>;
1699                 };
1700
1701                 gpio4: gpio4@ff7b0000 {
1702                         compatible = "rockchip,gpio-bank";
1703                         reg = <0x0 0xff7b0000 0x0 0x100>;
1704                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1705                         clocks = <&cru PCLK_GPIO4>;
1706
1707                         gpio-controller;
1708                         #gpio-cells = <2>;
1709
1710                         interrupt-controller;
1711                         #interrupt-cells = <2>;
1712                 };
1713
1714                 gpio5: gpio5@ff7c0000 {
1715                         compatible = "rockchip,gpio-bank";
1716                         reg = <0x0 0xff7c0000 0x0 0x100>;
1717                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1718                         clocks = <&cru PCLK_GPIO5>;
1719
1720                         gpio-controller;
1721                         #gpio-cells = <2>;
1722
1723                         interrupt-controller;
1724                         #interrupt-cells = <2>;
1725                 };
1726
1727                 gpio6: gpio6@ff7d0000 {
1728                         compatible = "rockchip,gpio-bank";
1729                         reg = <0x0 0xff7d0000 0x0 0x100>;
1730                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1731                         clocks = <&cru PCLK_GPIO6>;
1732
1733                         gpio-controller;
1734                         #gpio-cells = <2>;
1735
1736                         interrupt-controller;
1737                         #interrupt-cells = <2>;
1738                 };
1739
1740                 gpio7: gpio7@ff7e0000 {
1741                         compatible = "rockchip,gpio-bank";
1742                         reg = <0x0 0xff7e0000 0x0 0x100>;
1743                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1744                         clocks = <&cru PCLK_GPIO7>;
1745
1746                         gpio-controller;
1747                         #gpio-cells = <2>;
1748
1749                         interrupt-controller;
1750                         #interrupt-cells = <2>;
1751                 };
1752
1753                 gpio8: gpio8@ff7f0000 {
1754                         compatible = "rockchip,gpio-bank";
1755                         reg = <0x0 0xff7f0000 0x0 0x100>;
1756                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1757                         clocks = <&cru PCLK_GPIO8>;
1758
1759                         gpio-controller;
1760                         #gpio-cells = <2>;
1761
1762                         interrupt-controller;
1763                         #interrupt-cells = <2>;
1764                 };
1765
1766                 hdmi {
1767                         hdmi_ddc: hdmi-ddc {
1768                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1769                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1770                         };
1771                 };
1772
1773                 pcfg_pull_up: pcfg-pull-up {
1774                         bias-pull-up;
1775                 };
1776
1777                 pcfg_pull_down: pcfg-pull-down {
1778                         bias-pull-down;
1779                 };
1780
1781                 pcfg_pull_none: pcfg-pull-none {
1782                         bias-disable;
1783                 };
1784
1785                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1786                         bias-disable;
1787                         drive-strength = <12>;
1788                 };
1789
1790                 sleep {
1791                         global_pwroff: global-pwroff {
1792                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1793                         };
1794
1795                         ddrio_pwroff: ddrio-pwroff {
1796                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1797                         };
1798
1799                         ddr0_retention: ddr0-retention {
1800                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1801                         };
1802
1803                         ddr1_retention: ddr1-retention {
1804                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806                 };
1807
1808                 edp {
1809                         edp_hpd: edp-hpd {
1810                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1811                         };
1812                 };
1813
1814                 i2c0 {
1815                         i2c0_xfer: i2c0-xfer {
1816                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1817                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1818                         };
1819                 };
1820
1821                 i2c1 {
1822                         i2c1_xfer: i2c1-xfer {
1823                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1824                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1825                         };
1826                 };
1827
1828                 i2c2 {
1829                         i2c2_xfer: i2c2-xfer {
1830                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1831                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1832                         };
1833                 };
1834
1835                 i2c3 {
1836                         i2c3_xfer: i2c3-xfer {
1837                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1838                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1839                         };
1840                 };
1841
1842                 i2c4 {
1843                         i2c4_xfer: i2c4-xfer {
1844                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1845                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1846                         };
1847                 };
1848
1849                 i2c5 {
1850                         i2c5_xfer: i2c5-xfer {
1851                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1852                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1853                         };
1854                 };
1855
1856                 i2s0 {
1857                         i2s0_bus: i2s0-bus {
1858                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1859                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1860                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1861                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1862                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1863                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1864                         };
1865                 };
1866
1867                 lcdc0 {
1868                         lcdc0_ctl: lcdc0-ctl {
1869                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1870                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1871                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1872                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1873                         };
1874                 };
1875
1876                 sdmmc {
1877                         sdmmc_clk: sdmmc-clk {
1878                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1879                         };
1880
1881                         sdmmc_cmd: sdmmc-cmd {
1882                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1883                         };
1884
1885                         sdmmc_cd: sdmmc-cd {
1886                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1887                         };
1888
1889                         sdmmc_bus1: sdmmc-bus1 {
1890                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1891                         };
1892
1893                         sdmmc_bus4: sdmmc-bus4 {
1894                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1895                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1896                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1897                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1898                         };
1899                 };
1900
1901                 sdio0 {
1902                         sdio0_bus1: sdio0-bus1 {
1903                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1904                         };
1905
1906                         sdio0_bus4: sdio0-bus4 {
1907                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1908                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1909                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1910                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1911                         };
1912
1913                         sdio0_cmd: sdio0-cmd {
1914                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1915                         };
1916
1917                         sdio0_clk: sdio0-clk {
1918                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1919                         };
1920
1921                         sdio0_cd: sdio0-cd {
1922                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1923                         };
1924
1925                         sdio0_wp: sdio0-wp {
1926                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1927                         };
1928
1929                         sdio0_pwr: sdio0-pwr {
1930                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1931                         };
1932
1933                         sdio0_bkpwr: sdio0-bkpwr {
1934                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1935                         };
1936
1937                         sdio0_int: sdio0-int {
1938                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1939                         };
1940                 };
1941
1942                 sdio1 {
1943                         sdio1_bus1: sdio1-bus1 {
1944                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1945                         };
1946
1947                         sdio1_bus4: sdio1-bus4 {
1948                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1949                                                 <3 25 4 &pcfg_pull_up>,
1950                                                 <3 26 4 &pcfg_pull_up>,
1951                                                 <3 27 4 &pcfg_pull_up>;
1952                         };
1953
1954                         sdio1_cd: sdio1-cd {
1955                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1956                         };
1957
1958                         sdio1_wp: sdio1-wp {
1959                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1960                         };
1961
1962                         sdio1_bkpwr: sdio1-bkpwr {
1963                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1964                         };
1965
1966                         sdio1_int: sdio1-int {
1967                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1968                         };
1969
1970                         sdio1_cmd: sdio1-cmd {
1971                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1972                         };
1973
1974                         sdio1_clk: sdio1-clk {
1975                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1976                         };
1977
1978                         sdio1_pwr: sdio1-pwr {
1979                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1980                         };
1981                 };
1982
1983                 emmc {
1984                         emmc_clk: emmc-clk {
1985                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1986                         };
1987
1988                         emmc_cmd: emmc-cmd {
1989                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1990                         };
1991
1992                         emmc_pwr: emmc-pwr {
1993                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1994                         };
1995
1996                         emmc_bus1: emmc-bus1 {
1997                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1998                         };
1999
2000                         emmc_bus4: emmc-bus4 {
2001                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
2002                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
2003                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
2004                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2005                         };
2006
2007                         emmc_bus8: emmc-bus8 {
2008                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
2009                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
2010                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
2011                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
2012                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
2013                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
2014                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
2015                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2016                         };
2017                 };
2018
2019                 spi0 {
2020                         spi0_clk: spi0-clk {
2021                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
2022                         };
2023                         spi0_cs0: spi0-cs0 {
2024                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
2025                         };
2026                         spi0_tx: spi0-tx {
2027                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
2028                         };
2029                         spi0_rx: spi0-rx {
2030                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
2031                         };
2032                         spi0_cs1: spi0-cs1 {
2033                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
2034                         };
2035                 };
2036                 spi1 {
2037                         spi1_clk: spi1-clk {
2038                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
2039                         };
2040                         spi1_cs0: spi1-cs0 {
2041                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
2042                         };
2043                         spi1_rx: spi1-rx {
2044                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
2045                         };
2046                         spi1_tx: spi1-tx {
2047                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
2048                         };
2049                 };
2050
2051                 spi2 {
2052                         spi2_cs1: spi2-cs1 {
2053                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
2054                         };
2055                         spi2_clk: spi2-clk {
2056                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
2057                         };
2058                         spi2_cs0: spi2-cs0 {
2059                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
2060                         };
2061                         spi2_rx: spi2-rx {
2062                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
2063                         };
2064                         spi2_tx: spi2-tx {
2065                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
2066                         };
2067                 };
2068
2069                 uart0 {
2070                         uart0_xfer: uart0-xfer {
2071                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
2072                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
2073                         };
2074
2075                         uart0_cts: uart0-cts {
2076                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
2077                         };
2078
2079                         uart0_rts: uart0-rts {
2080                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
2081                         };
2082                 };
2083
2084                 uart1 {
2085                         uart1_xfer: uart1-xfer {
2086                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
2087                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
2088                         };
2089
2090                         uart1_cts: uart1-cts {
2091                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
2092                         };
2093
2094                         uart1_rts: uart1-rts {
2095                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
2096                         };
2097                 };
2098
2099                 uart2 {
2100                         uart2_xfer: uart2-xfer {
2101                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2102                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2103                         };
2104                         /* no rts / cts for uart2 */
2105                 };
2106
2107                 uart3 {
2108                         uart3_xfer: uart3-xfer {
2109                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2110                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2111                         };
2112
2113                         uart3_cts: uart3-cts {
2114                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2115                         };
2116
2117                         uart3_rts: uart3-rts {
2118                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2119                         };
2120                 };
2121
2122                 uart4 {
2123                         uart4_xfer: uart4-xfer {
2124                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2125                                                 <5 13 3 &pcfg_pull_none>;
2126                         };
2127
2128                         uart4_cts: uart4-cts {
2129                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2130                         };
2131
2132                         uart4_rts: uart4-rts {
2133                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2134                         };
2135                 };
2136
2137                 tsadc {
2138                         otp_gpio: otp-gpio {
2139                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2140                         };
2141
2142                         otp_out: otp-out {
2143                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2144                         };
2145                 };
2146
2147                 pwm0 {
2148                         pwm0_pin: pwm0-pin {
2149                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2150                         };
2151                 };
2152
2153                 pwm1 {
2154                         pwm1_pin: pwm1-pin {
2155                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2156                         };
2157                 };
2158
2159                 pwm2 {
2160                         pwm2_pin: pwm2-pin {
2161                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2162                         };
2163                 };
2164
2165                 pwm3 {
2166                         pwm3_pin: pwm3-pin {
2167                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2168                         };
2169                 };
2170
2171                 gmac {
2172                         rgmii_pins: rgmii-pins {
2173                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2174                                                 <3 31 3 &pcfg_pull_none>,
2175                                                 <3 26 3 &pcfg_pull_none>,
2176                                                 <3 27 3 &pcfg_pull_none>,
2177                                                 <3 28 3 &pcfg_pull_none_12ma>,
2178                                                 <3 29 3 &pcfg_pull_none_12ma>,
2179                                                 <3 24 3 &pcfg_pull_none_12ma>,
2180                                                 <3 25 3 &pcfg_pull_none_12ma>,
2181                                                 <4 0 3 &pcfg_pull_none>,
2182                                                 <4 5 3 &pcfg_pull_none>,
2183                                                 <4 6 3 &pcfg_pull_none>,
2184                                                 <4 9 3 &pcfg_pull_none_12ma>,
2185                                                 <4 4 3 &pcfg_pull_none_12ma>,
2186                                                 <4 1 3 &pcfg_pull_none>,
2187                                                 <4 3 3 &pcfg_pull_none>;
2188                         };
2189
2190                         rmii_pins: rmii-pins {
2191                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2192                                                 <3 31 3 &pcfg_pull_none>,
2193                                                 <3 28 3 &pcfg_pull_none>,
2194                                                 <3 29 3 &pcfg_pull_none>,
2195                                                 <4 0 3 &pcfg_pull_none>,
2196                                                 <4 5 3 &pcfg_pull_none>,
2197                                                 <4 4 3 &pcfg_pull_none>,
2198                                                 <4 1 3 &pcfg_pull_none>,
2199                                                 <4 2 3 &pcfg_pull_none>,
2200                                                 <4 3 3 &pcfg_pull_none>;
2201                         };
2202                 };
2203
2204                 spdif {
2205                         spdif_tx: spdif-tx {
2206                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2207                         };
2208                 };
2209
2210                 cif {
2211                         cif_dvp_d2d9: cif-dvp-d2d9 {
2212                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2213                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2214                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2215                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2216                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2217                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2218                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2219                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2220                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2221                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2222                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2223                         };
2224                 };
2225
2226                 isp_pin {
2227                         isp_mipi: isp-mipi {
2228                                 rockchip,pins =
2229                                         /* cif_clkout */
2230                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2231                         };
2232
2233                         isp_dvp_d2d9: isp-d2d9 {
2234                                 rockchip,pins =
2235                                         /* cif_data2 ... cif_data9 */
2236                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2237                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2238                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2239                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2240                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2241                                         <2 5 RK_FUNC_1 &pcfg_pull_none>,
2242                                         <2 6 RK_FUNC_1 &pcfg_pull_none>,
2243                                         <2 7 RK_FUNC_1 &pcfg_pull_none>,
2244                                         /* cif_sync, cif_href */
2245                                         <2 8 RK_FUNC_1 &pcfg_pull_none>,
2246                                         <2 9 RK_FUNC_1 &pcfg_pull_none>,
2247                                         /* cif_clkin, cif_clkout */
2248                                         <2 10 RK_FUNC_1 &pcfg_pull_none>,
2249                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2250                         };
2251
2252                         isp_dvp_d0d1: isp-d0d1 {
2253                                 rockchip,pins =
2254                                         /* cif_data0, cif_data1 */
2255                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2256                                         <2 13 RK_FUNC_1 &pcfg_pull_none>;
2257                         };
2258
2259                         isp_dvp_d10d11: isp-d10d11 {
2260                                 rockchip,pins =
2261                                         /* cif_data10, cif_data11 */
2262                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
2263                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
2264                         };
2265
2266                         isp_dvp_d0d7: isp-d0d7 {
2267                                 rockchip,pins =
2268                                         /* cif_data0 ... cif_data7 */
2269                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2270                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
2271                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2272                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2273                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2274                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2275                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2276                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
2277                         };
2278
2279                         isp_shutter: isp-shutter {
2280                                 rockchip,pins =
2281                                         /* SHUTTEREN, SHUTTERTRIG */
2282                                         <7 12 RK_FUNC_2 &pcfg_pull_none>,
2283                                         <7 15 RK_FUNC_2 &pcfg_pull_none>;
2284                         };
2285
2286                         isp_flash_trigger: isp-flash-trigger {
2287                                 rockchip,pins =
2288                                         /* ISP_FLASHTRIGOU */
2289                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2290                         };
2291
2292                         isp_prelight: isp-prelight {
2293                                 rockchip,pins =
2294                                         /* ISP_PRELIGHTTRIG */
2295                                         <7 14 RK_FUNC_2 &pcfg_pull_none>;
2296                         };
2297
2298                         isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
2299                                 rockchip,pins =
2300                                         /* ISP_FLASHTRIGOU */
2301                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2302                         };
2303                 };
2304
2305         };
2306         rockchip_suspend: rockchip-suspend {
2307                 compatible = "rockchip,pm-rk3288";
2308                 status = "disabled";
2309                 rockchip,sleep-mode-config = <
2310                         (0
2311                         |RKPM_CTR_PWR_DMNS
2312                         |RKPM_CTR_GTCLKS
2313                         |RKPM_CTR_PLLS
2314                         |RKPM_CTR_ARMOFF_LPMD
2315                         )
2316                 >;
2317                 rockchip,wakeup-config = <
2318                         (0
2319                         | RKPM_GPIO_WKUP_EN
2320                         )
2321                 >;
2322                 rockchip,pwm-regulator-config = <
2323                         (0
2324                         | PWM2_REGULATOR_EN
2325                         )
2326                 >;
2327         };
2328 };