1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include "skeleton.dtsi"
3 #include "rk3288-pinctrl.dtsi"
4 #include <dt-bindings/rkfb/rk_fb.h>
7 compatible = "rockchip,rk3288";
8 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a15";
33 compatible = "arm,cortex-a15";
38 compatible = "arm,cortex-a15";
43 compatible = "arm,cortex-a15";
48 gic: interrupt-controller@ffc01000 {
49 compatible = "arm,cortex-a15-gic";
51 #interrupt-cells = <3>;
53 reg = <0xffc01000 0x1000>,
58 compatible = "mmio-sram";
59 reg = <0xff710000 0x8000>; /* 32k */
64 compatible = "arm,armv7-timer";
65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
68 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
69 clock-frequency = <24000000>;
73 compatible = "rockchip,timer";
74 reg = <0xff810000 0x20>;
75 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
76 rockchip,broadcast = <1>;
80 compatible = "rockchip,timer";
81 reg = <0xff810020 0x20>;
82 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
83 rockchip,clocksource = <1>;
84 rockchip,count-up = <1>;
87 uart_dbg: serial@ff690000 {
88 compatible = "rockchip,serial";
89 reg = <0xff690000 0x100>;
90 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
91 clock-frequency = <24000000>;
98 compatible = "rockchip,fiq-debugger";
99 rockchip,serial-id = <2>;
100 rockchip,signal-irq = <106>;
101 rockchip,wake-irq = <0>;
106 compatible = "rockchip,rk30-i2c";
107 reg = <0xff650000 0x1000>;
108 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
109 #address-cells = <1>;
111 //pinctrl-names = "default", "gpio";
112 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
113 //pinctrl-1 = <&i2c0_gpio>;
114 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
115 //clocks = <&clk_gates8 4>;
116 rockchip,check-idle = <1>;
121 compatible = "rockchip,rk30-i2c";
122 reg = <0xff140000 0x1000>;
123 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
126 //pinctrl-names = "default", "gpio";
127 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
128 //pinctrl-1 = <&i2c1_gpio>;
129 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
130 //clocks = <&clk_gates8 5>;
131 rockchip,check-idle = <1>;
136 compatible = "rockchip,rk30-i2c";
137 reg = <0xff660000 0x1000>;
138 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
139 #address-cells = <1>;
141 //pinctrl-names = "default", "gpio";
142 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
143 //pinctrl-1 = <&i2c2_gpio>;
144 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
145 //clocks = <&clk_gates8 6>;
146 rockchip,check-idle = <1>;
151 compatible = "rockchip,rk30-i2c";
152 reg = <0xff150000 0x1000>;
153 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
154 #address-cells = <1>;
156 //pinctrl-names = "default", "gpio";
157 //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
158 //pinctrl-1 = <&i2c3_gpio>;
159 //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
160 //clocks = <&clk_gates8 7>;
161 rockchip,check-idle = <1>;
166 compatible = "rockchip,rk30-i2c";
167 reg = <0xff160000 0x1000>;
168 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>;
171 //pinctrl-names = "default", "gpio";
172 //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
173 //pinctrl-1 = <&i2c4_gpio>;
174 //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
175 //clocks = <&clk_gates8 8>;
176 rockchip,check-idle = <1>;
181 compatible = "rockchip,rk30-i2c";
182 reg = <0xff170000 0x1000>;
183 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
184 #address-cells = <1>;
186 //pinctrl-names = "default", "gpio";
187 //pinctrl-0 = <&i2c5_sda &i2c5_scl>;
188 //pinctrl-1 = <&i2c5_gpio>;
189 //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
190 //clocks = <&clk_gates8 8>;
191 rockchip,check-idle = <1>;
196 compatible = "rockchip,rk32-edp";
197 reg = <0xff970000 0x4000>;
198 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
202 hdmi: hdmi@ff980000 {
203 compatible = "rockchip,rk3288-hdmi";
204 reg = <0xff980000 0x20000>;
205 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
206 rockchip,hdmi_lcdc_source = <1>;
207 pinctrl-names = "default", "gpio";
208 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
209 pinctrl-1 = <&i2c5_gpio>;
213 compatible = "rockchip,rk-fb";
214 rockchip,disp-mode = <DUAL>;
217 lcdc0: lcdc@ff940000 {
218 compatible = "rockchip,rk3288-lcdc";
219 rockchip,prop = <PRMRY>;
220 rochchip,pwr18 = <0>;
221 reg = <0xff940000 0x10000>;
222 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
223 //pinctrl-names = "default", "gpio";
224 //pinctrl-0 = <&lcdc0_lcdc>;
225 //pinctrl-1 = <&lcdc0_gpio>;
229 lcdc1: lcdc@ff930000 {
230 compatible = "rockchip,rk3288-lcdc";
231 rockchip,prop = <EXTEND>;
232 rockchip,pwr18 = <0>;
233 reg = <0xff930000 0x10000>;
234 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
235 pinctrl-names = "default", "gpio";
236 pinctrl-0 = <&lcdc0_lcdc>;
237 pinctrl-1 = <&lcdc0_gpio>;
242 compatible = "rockchip,saradc";
243 reg = <0xff100000 0x100>;
244 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
245 #io-channel-cells = <1>;
247 rockchip,adc-vref = <1800>;
248 clock-frequency = <1000000>;
249 clock-names = "saradc", "pclk_saradc";
254 compatible = "rockchip,rga";
255 reg = <0xff920000 0x1000>;
256 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
257 clock-names = "hclk_rga", "aclk_rga";
260 i2s: rockchip-i2s@0xff890000 {
261 compatible = "rockchip-i2s";
262 reg = <0xff890000 0x10000>;
264 // clocks = <&clk_i2s>;
265 // clock-names = "i2s_clk","i2s_mclk";
266 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
267 // dmas = <&pdma0 0>,
270 // dma-names = "tx", "rx";
271 // pinctrl-names = "default", "sleep";
272 // pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
273 // pinctrl-1 = <&i2s0_gpio>;
276 spdif: rockchip-spdif@0xff8b0000 {
277 compatible = "rockchip-spdif";
278 reg = <0xff8b0000 0x10000>; //8channel
279 //reg = <ff880000 0x2000>;//2channel
280 // clocks = <&clk_spdif>;
281 // clock-names = "spdif_mclk";
282 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
283 // dmas = <&pdma0 8>;
286 // pinctrl-names = "default";
287 // pinctrl-0 = <&spdif_tx>;
291 compatible = "rockchip,ion";
292 #address-cells = <1>;
294 rockchip,ion-heap@1 { /* CMA HEAP */
297 rockchip,ion-heap@3 { /* SYSTEM HEAP */
303 compatible = "rockchip,rk_mmc";
304 reg = <0xff0c0000 0x4000>;
305 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
306 #address-cells = <1>;
308 //pinctrl-names = "default","suspend";
309 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>;
310 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
311 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
312 //clock-names = "hclk_mmc","mmc";
313 clock-frequency = <50000000>;
314 clock-freq-min-max = <400000 50000000>;
318 card-detect-delay = <200>;
319 pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
320 fifo-depth = <0x100>;
321 emmc-compatible = <0>;
325 sdio0: mshc@ff0d0000 {
326 compatible = "rockchip,rk_mmc";
327 reg = <0xff0d0000 0x4000>;
328 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
329 #address-cells = <1>;
331 //pinctrl-names = "default";
332 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
333 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
334 //clock-names = "hclk_sdio0","sdio0";
335 clock-frequency = <50000000>;
336 clock-freq-min-max = <400000 50000000>;
339 fifo-depth = <0x100>;
340 emmc-compatible = <0>;
344 sdio1: mshc@ff0e0000 {
345 compatible = "rockchip,rk_mmc";
346 reg = <0xff0e0000 0x4000>;
347 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
348 #address-cells = <1>;
350 //pinctrl-names = "default";
351 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
352 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
353 //clock-names = "hclk_sdio1","sdio1";
354 clock-frequency = <50000000>;
355 clock-freq-min-max = <400000 50000000>;
358 fifo-depth = <0x100>;
359 emmc-compatible = <0>;
363 emmc: mshc@ff0f0000 {
364 compatible = "rockchip,rk_mmc";
365 reg = <0xff0f0000 0x4000>;
366 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
367 #address-cells = <1>;
369 //pinctrl-names = "default";
370 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
371 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
372 //clock-names = "hclk_sdio1","sdio1";
373 clock-frequency = <50000000>;
374 clock-freq-min-max = <400000 50000000>;
377 fifo-depth = <0x100>;
378 emmc-compatible = <1>;
382 vpu: vpu_service@ff9a0000 {
383 compatible = "vpu_service";
384 reg = <0xff9a0000 0x800>;
385 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-names = "irq_enc", "irq_dec";
387 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
388 clock-names = "aclk_vcodec", "hclk_vcodec"; */
389 name = "vpu_service";
393 hevc: hevc_service@ff9c0000 {
394 compatible = "rockchip,hevc_service";
395 reg = <0xff9c0000 0x800>;
396 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "irq_dec";
398 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
399 clock-names = "aclk_vcodec", "hclk_vcodec";*/
400 name = "hevc_service";
405 compatible = "rockchip,iep";
406 reg = <0xff900000 0x800>;
407 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
408 /*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
409 clock_names = "aclk_iep", "hclk_iep";*/
413 dwc_control_usb: dwc-control-usb@ff770284 {
414 compatible = "rockchip,rk3288-dwc-control-usb";
415 reg = <0xff770284 0x04>, <0xff770288 0x04>,
416 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
417 <0xff770320 0x14>, <0xff770334 0x14>,
418 <0xff770348 0x10>, <0xff770358 0x08>,
420 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
421 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
422 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
423 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
425 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "otg_id", "bvalid",
429 "otg_linestate", "host0_linestate",
431 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
432 /* <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
433 /*clocks = <&clk_gates4 5>;*/
434 /*clock-names = "hclk_usb_peri";*/
438 compatible = "rockchip,rk3288_usb20_otg";
439 reg = <0xff580000 0x40000>;
440 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
441 /*clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;*/
442 /*clock-names = "otgphy0", "hclk_otg0";*/
446 compatible = "rockchip,rk3288_usb20_host";
447 reg = <0xff540000 0x40000>;
448 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
449 /*clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;*/
450 /*clock-names = "otgphy1", "hclk_otg1";*/
454 compatible = "rockchip,rk3288_rk_ohci_host";
455 reg = <0xff520000 0x20000>;
456 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
462 compatible = "rockchip,rk3288_rk_ehci_host";
463 reg = <0xff500000 0x20000>;
464 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
469 usb5: hsic@ff5c0000 {
470 compatible = "rockchip,rk3288_rk_hsic_host";
471 reg = <0xff5c0000 0x40000>;
472 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
473 /*clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,*/
474 /* <&clk_hsicphy12m>, <&clk_otgphy1_480m>;*/
475 /*clock-names = "hsicphy480m", "hclk_hsic",*/
476 /* "hsicphy12m", "hsic_otgphy1";*/