arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/rk_system_status.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a12-pmu";
  73                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78
  79         cpu_axi_bus: cpu_axi_bus {
  80                 compatible = "rockchip,cpu_axi_bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 qos {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         /* service core */
  90                         cpup {
  91                                 reg = <0xffa80000 0x20>;
  92                         };
  93                         cpum_r {
  94                                 reg = <0xffa80080 0x20>;
  95                         };
  96                         cpum_w {
  97                                 reg = <0xffa80100 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0xffa90000 0x20>;
 102                         };
 103                         host {
 104                                 reg = <0xffa90080 0x20>;
 105                         };
 106                         crypto {
 107                                 reg = <0xffa90100 0x20>;
 108                         };
 109                         ccp {
 110                                 reg = <0xffa90180 0x20>;
 111                         };
 112                         ccs {
 113                                 reg = <0xffa90200 0x20>;
 114                         };
 115                         /* service gpu */
 116                         gpu_r {
 117                                 reg = <0xffaa0000 0x20>;
 118                         };
 119                         gpu_w {
 120                                 reg = <0xffaa0080 0x20>;
 121                         };
 122                         /* service peri */
 123                         peri {
 124                                 reg = <0xffab0000 0x20>;
 125                         };
 126                         /* service vio */
 127                         vio1_vop {
 128                                 reg = <0xffad0000 0x20>;
 129                                 rockchip,priority = <2 2>;
 130                         };
 131                         vio1_isp_w0 {
 132                                 reg = <0xffad0100 0x20>;
 133                         };
 134                         vio1_isp_w1 {
 135                                 reg = <0xffad0180 0x20>;
 136                         };
 137                         vio0_vop {
 138                                 reg = <0xffad0400 0x20>;
 139                                 rockchip,priority = <2 2>;
 140                         };
 141                         vio0_vip {
 142                                 reg = <0xffad0480 0x20>;
 143                         };
 144                         vio0_iep {
 145                                 reg = <0xffad0500 0x20>;
 146                         };
 147                         vio2_rga_r {
 148                                 reg = <0xffad0800 0x20>;
 149                         };
 150                         vio2_rga_w {
 151                                 reg = <0xffad0880 0x20>;
 152                         };
 153                         vio1_isp_r {
 154                                 reg = <0xffad0900 0x20>;
 155                         };
 156                         /* service video */
 157                         video {
 158                                 reg = <0xffae0000 0x20>;
 159                         };
 160                         /* service hevc */
 161                         hevc_r {
 162                                 reg = <0xffaf0000 0x20>;
 163                         };
 164                         hevc_w {
 165                                 reg = <0xffaf0080 0x20>;
 166                         };
 167                 };
 168
 169                 msch {
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172                         ranges;
 173
 174                         msch@0 {
 175                                 reg = <0xffac0000 0x40>;
 176                                 rockchip,read-latency = <0x34>;
 177                         };
 178                         msch@1 {
 179                                 reg = <0xffac0080 0x40>;
 180                                 rockchip,read-latency = <0x34>;
 181                         };
 182                 };
 183         };
 184
 185         sram: sram@ff710000 {
 186                 compatible = "mmio-sram";
 187                 reg = <0xff710000 0x8000>; /* 32k */
 188                 map-exec;
 189         };
 190
 191         timer {
 192                 compatible = "arm,armv7-timer";
 193                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 194                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 195                 clock-frequency = <24000000>;
 196         };
 197
 198         timer@ff810000 {
 199                 compatible = "rockchip,timer";
 200                 reg = <0xff810000 0x20>;
 201                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 202                 rockchip,broadcast = <1>;
 203         };
 204
 205         watchdog: wdt@2004c000 {
 206                 compatible = "rockchip,watch dog";
 207                 reg = <0xff800000 0x100>;
 208                 clocks = <&pclk_pd_alive>;
 209                 clock-names = "pclk_wdt";
 210                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 211                 rockchip,irq = <1>;
 212                 rockchip,timeout = <60>;
 213                 rockchip,atboot = <1>;
 214                 rockchip,debug = <0>;
 215                 status = "disabled";
 216         };
 217
 218         amba {
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221                 compatible = "arm,amba-bus";
 222                 interrupt-parent = <&gic>;
 223                 ranges;
 224
 225                 pdma0: pdma@ffb20000 {
 226                         compatible = "arm,pl330", "arm,primecell";
 227                         reg = <0xffb20000 0x4000>;
 228                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 230                         #dma-cells = <1>;
 231                 };
 232
 233                 pdma1: pdma@ff250000 {
 234                         compatible = "arm,pl330", "arm,primecell";
 235                         reg = <0xff250000 0x4000>;
 236                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 238                         #dma-cells = <1>;
 239                 };
 240         };
 241
 242         reset: reset@ff7601b8{
 243                 compatible = "rockchip,reset";
 244                 reg = <0xff7601b8 0x30>;
 245                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 246                 #reset-cells = <1>;
 247         };
 248
 249         nandc0: nandc@0xff400000 {
 250                 compatible = "rockchip,rk-nandc";
 251                 reg = <0xff400000 0x4000>;
 252                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 253                 nandc_id = <0>;
 254                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 255                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 256         };
 257
 258         nandc1: nandc@0xff410000 {
 259             compatible = "rockchip,rk-nandc";
 260                 reg = <0xff410000 0x4000>;
 261                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 262                 nandc_id = <1>;
 263                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 264                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 265         };
 266
 267         nandc0reg: nandc0@0xff400000 {
 268                 compatible = "rockchip,rk-nandc";
 269                 reg = <0xff400000 0x4000>;
 270         };
 271
 272         emmc: rksdmmc@ff0f0000 {
 273                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 274                 reg = <0xff0f0000 0x4000>;
 275                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 //pinctrl-names = "default",,"suspend";
 279                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 280                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 281                 clock-names = "clk_mmc", "hclk_mmc";
 282                 num-slots = <1>;
 283                 fifo-depth = <0x100>;
 284                 bus-width = <8>;
 285         };
 286
 287         sdmmc: rksdmmc@ff0c0000 {
 288                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 289                 reg = <0xff0c0000 0x4000>;
 290                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 291                 #address-cells = <1>;
 292                 #size-cells = <0>;
 293                 pinctrl-names = "default", "idle";
 294                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 295                 pinctrl-1 = <&sdmmc0_gpio>;
 296                 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 297                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 298                 clock-names = "clk_mmc", "hclk_mmc";
 299                 num-slots = <1>;
 300                 fifo-depth = <0x100>;
 301                 bus-width = <4>;
 302         };
 303
 304         sdio: rksdmmc@ff0d0000 {
 305                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 306                 reg = <0xff0d0000 0x4000>;
 307                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 pinctrl-names = "default","idle";
 311                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 312                              &sdio0_intn &sdio0_bus4>;
 313                 pinctrl-1 = <&sdio0_gpio>;
 314                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 315                 clock-names = "clk_mmc", "hclk_mmc";
 316                 num-slots = <1>;
 317                 fifo-depth = <0x100>;
 318                 bus-width = <4>;
 319         };
 320
 321         sdio1: rksdmmc@ff0e0000 {
 322                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 323                 reg = <0xff0e0000 0x4000>;
 324                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 //pinctrl-names = "default","suspend";
 328                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 329                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 330                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 331                 clock-names = "clk_mmc", "hclk_mmc";
 332                 num-slots = <1>;
 333                 fifo-depth = <0x100>;
 334                 bus-width = <4>;
 335                 status = "disabled";
 336         };
 337
 338         spi0: spi@ff110000 {
 339                 compatible = "rockchip,rockchip-spi";
 340                 reg = <0xff110000 0x1000>;
 341                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 346                 rockchip,spi-src-clk = <0>;
 347                 num-cs = <2>;
 348                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 349                 clock-names = "spi","pclk_spi0";
 350                 //dmas = <&pdma1 11>, <&pdma1 12>;
 351                 //#dma-cells = <2>;
 352                 //dma-names = "tx", "rx";
 353                 status = "disabled";
 354         };
 355
 356         spi1: spi@ff120000 {
 357                 compatible = "rockchip,rockchip-spi";
 358                 reg = <0xff120000 0x1000>;
 359                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 pinctrl-names = "default";
 363                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 364                 rockchip,spi-src-clk = <1>;
 365                 num-cs = <1>;
 366                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 367                 clock-names = "spi","pclk_spi1";
 368                 //dmas = <&pdma1 13>, <&pdma1 14>;
 369                 //#dma-cells = <2>;
 370                 //dma-names = "tx", "rx";
 371                 status = "disabled";
 372         };
 373
 374         spi2: spi@ff130000 {
 375                 compatible = "rockchip,rockchip-spi";
 376                 reg = <0xff130000 0x1000>;
 377                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 382                 rockchip,spi-src-clk = <2>;
 383                 num-cs = <2>;
 384                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 385                 clock-names = "spi","pclk_spi2";
 386                 //dmas = <&pdma1 15>, <&pdma1 16>;
 387                 //#dma-cells = <2>;
 388                 //dma-names = "tx", "rx";
 389                 status = "disabled";
 390         };
 391
 392         uart_bt: serial@ff180000 {
 393                 compatible = "rockchip,serial";
 394                 reg = <0xff180000 0x100>;
 395                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 396                 clock-frequency = <24000000>;
 397                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 398                 clock-names = "sclk_uart", "pclk_uart";
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 dmas = <&pdma1 1>, <&pdma1 2>;
 402                 #dma-cells = <2>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 405                 status = "disabled";
 406         };
 407
 408         uart_bb: serial@ff190000 {
 409                 compatible = "rockchip,serial";
 410                 reg = <0xff190000 0x100>;
 411                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 412                 clock-frequency = <24000000>;
 413                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 414                 clock-names = "sclk_uart", "pclk_uart";
 415                 reg-shift = <2>;
 416                 reg-io-width = <4>;
 417                 dmas = <&pdma1 3>, <&pdma1 4>;
 418                 #dma-cells = <2>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 421                 status = "disabled";
 422         };
 423
 424         uart_dbg: serial@ff690000 {
 425                 compatible = "rockchip,serial";
 426                 reg = <0xff690000 0x100>;
 427                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 428                 clock-frequency = <24000000>;
 429                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 430                 clock-names = "sclk_uart", "pclk_uart";
 431                 reg-shift = <2>;
 432                 reg-io-width = <4>;
 433                 dmas = <&pdma0 4>, <&pdma0 5>;
 434                 #dma-cells = <2>;
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart2_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         uart_gps: serial@ff1b0000 {
 441                 compatible = "rockchip,serial";
 442                 reg = <0xff1b0000 0x100>;
 443                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 444                 clock-frequency = <24000000>;
 445                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 446                 clock-names = "sclk_uart", "pclk_uart";
 447                 current-speed = <115200>;
 448                 reg-shift = <2>;
 449                 reg-io-width = <4>;
 450                 dmas = <&pdma1 7>, <&pdma1 8>;
 451                 #dma-cells = <2>;
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 454                 status = "disabled";
 455         };
 456
 457         uart_exp: serial@ff1c0000 {
 458                 compatible = "rockchip,serial";
 459                 reg = <0xff1c0000 0x100>;
 460                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 461                 clock-frequency = <24000000>;
 462                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 463                 clock-names = "sclk_uart", "pclk_uart";
 464                 reg-shift = <2>;
 465                 reg-io-width = <4>;
 466                 dmas = <&pdma1 9>, <&pdma1 10>;
 467                 #dma-cells = <2>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 470                 status = "disabled";
 471         };
 472
 473         fiq-debugger {
 474                 compatible = "rockchip,fiq-debugger";
 475                 rockchip,serial-id = <2>;
 476                 rockchip,signal-irq = <106>;
 477                 rockchip,wake-irq = <0>;
 478                 status = "disabled";
 479         };
 480
 481         rockchip_clocks_init: clocks-init{
 482                 compatible = "rockchip,clocks-init";
 483                 rockchip,clocks-init-parent =
 484                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 485                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 486                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 487                         <&usbphy_480m &otgphy2_480m>;
 488                 rockchip,clocks-init-rate =
 489                         <&clk_core 792000000>,  <&clk_gpll 297000000>,
 490                         /*<&clk_cpll 47000000>,*/       <&clk_npll 1250000000>,
 491                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 492                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 493                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 494                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 495                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 496                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 497                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 498                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 499                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 500                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 501                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 502                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 503                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 504                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 505                 rockchip,clocks-uboot-has-init =
 506                         <&aclk_vio0>;
 507         };
 508
 509         clocks-enable {
 510                 compatible = "rockchip,clocks-enable";
 511                 clocks =
 512                                 /*PD_CORE*/
 513                                 <&clk_gates0 2>, <&clk_core0>,
 514                                 <&clk_core1>, <&clk_core2>,
 515                                 <&clk_core3>, <&clk_l2ram>,
 516                                 <&aclk_core_m0>, <&aclk_core_mp>,
 517                                 <&atclk_core>, <&pclk_dbg_src>,
 518                                 <&clk_gates12 9>, <&clk_gates12 10>,
 519                                 <&clk_gates12 11>,
 520
 521                                 /*PD_BUS*/
 522                                 <&aclk_bus>, <&clk_gates0 3>,
 523                                 <&hclk_bus>, <&pclk_bus>,
 524                                 <&clk_gates13 8>, <&clk_crypto>,
 525                                 <&clk_gates0 7>,
 526
 527                                 /*TIMER*/
 528                                 <&clk_gates1 0>, <&clk_gates1 1>,
 529                                 <&clk_gates1 2>, <&clk_gates1 3>,
 530                                 <&clk_gates1 4>, <&clk_gates1 5>,
 531
 532                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 533
 534                                 /*PD_PERI*/
 535                                 <&aclk_peri>, <&hclk_peri>,
 536                                 <&pclk_peri>,
 537
 538                                 /*JTAG*/
 539                                 /*<&clk_gates4 14>,*/
 540
 541                                 /*aclk_bus*/
 542                                 <&clk_gates10 5>,/*aclk_intmem0*/
 543                                 <&clk_gates10 6>,/*aclk_intmem1*/
 544                                 <&clk_gates10 7>,/*aclk_intmem2*/
 545                                 <&clk_gates10 12>,/*aclk_dma1*/
 546                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 547                                 <&clk_gates10 4>,/*aclk_intmem*/
 548                                 <&clk_gates11 6>,/*aclk_crypto*/
 549                                 <&clk_gates11 8>,/*aclk_ccp*/
 550
 551                                 /*hclk_bus*/
 552                                 <&clk_gates11 7>,/*hclk_crypto*/
 553                                 <&clk_gates10 9>,/*hclk_rom*/
 554
 555                                 /*pclk_bus*/
 556                                 <&clk_gates10 1>,/*pclk_timer*/
 557                                 <&clk_gates10 9>,/*rom*/
 558                                 <&clk_gates10 13>,/*aclk strc*/
 559
 560                                 <&clk_gates12 8>,/*aclk strc*/
 561
 562                                 /*aclk_peri*/
 563                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 564                                 <&clk_gates6 3>,/*aclk_dmac2*/
 565                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 566                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 567
 568                                 /*hclk_peri*/
 569                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 570                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 571                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 572                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 573
 574                                 /*pclk_peri*/
 575                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 576
 577                                 /*pclk_pd_alive*/
 578                                 <&clk_gates14 11>,/*pclk_grf*/
 579                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 580
 581                                 /*pclk_pd_pmu*/
 582                                 <&clk_gates17 0>,/*pclk_pmu*/
 583                                 <&clk_gates17 1>,/*pclk_intmem1*/
 584                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 585                                 <&clk_gates17 3>,/*pclk_sgrf*/
 586
 587                                 /*hclk_vio*/
 588                                 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
 589                                 <&clk_gates15 10>,/*hclk_vio_niu*/
 590                                 <&clk_gates16 10>,/*hclk_vio2_h2p*/
 591                                 <&clk_gates16 11>,/*pclk_vio2_h2p*/
 592
 593                                 /*aclk_vio0*/
 594                                 <&clk_gates15 11>,/*aclk_vio0_niu*/
 595
 596                                 /*aclk_vio1*/
 597                                 <&clk_gates15 12>,/*aclk_vio1_niu*/
 598
 599                                 /*HDMI*/
 600                                 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
 601
 602                                 /*UART*/
 603                                 <&clk_gates11 9>,/*pclk_uart2*/
 604
 605                                 /*480M*/
 606                                 <&usbphy_480m>;
 607         };
 608
 609         i2c0: i2c@ff650000 {
 610                 compatible = "rockchip,rk30-i2c";
 611                 reg = <0xff650000 0x1000>;
 612                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 pinctrl-names = "default", "gpio";
 616                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 617                 pinctrl-1 = <&i2c0_gpio>;
 618                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 619                 clocks = <&clk_gates10 2>;
 620                 rockchip,check-idle = <1>;
 621                 status = "disabled";
 622         };
 623
 624         i2c1: i2c@ff140000 {
 625                 compatible = "rockchip,rk30-i2c";
 626                 reg = <0xff140000 0x1000>;
 627                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 pinctrl-names = "default", "gpio";
 631                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 632                 pinctrl-1 = <&i2c1_gpio>;
 633                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 634                 clocks = <&clk_gates10 3>;
 635                 rockchip,check-idle = <1>;
 636                 status = "disabled";
 637         };
 638
 639         i2c2: i2c@ff660000 {
 640                 compatible = "rockchip,rk30-i2c";
 641                 reg = <0xff660000 0x1000>;
 642                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 pinctrl-names = "default", "gpio";
 646                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 647                 pinctrl-1 = <&i2c2_gpio>;
 648                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 649                 clocks = <&clk_gates6 13>;
 650                 rockchip,check-idle = <1>;
 651                 status = "disabled";
 652         };
 653
 654         i2c3: i2c@ff150000 {
 655                 compatible = "rockchip,rk30-i2c";
 656                 reg = <0xff150000 0x1000>;
 657                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 pinctrl-names = "default", "gpio";
 661                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 662                 pinctrl-1 = <&i2c3_gpio>;
 663                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 664                 clocks = <&clk_gates6 14>;
 665                 rockchip,check-idle = <1>;
 666                 status = "disabled";
 667         };
 668
 669         i2c4: i2c@ff160000 {
 670                 compatible = "rockchip,rk30-i2c";
 671                 reg = <0xff160000 0x1000>;
 672                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 pinctrl-names = "default", "gpio";
 676                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 677                 pinctrl-1 = <&i2c4_gpio>;
 678                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 679                 clocks = <&clk_gates6 15>;
 680                 rockchip,check-idle = <1>;
 681                 status = "disabled";
 682         };
 683
 684         i2c5: i2c@ff170000 {
 685                 compatible = "rockchip,rk30-i2c";
 686                 reg = <0xff170000 0x1000>;
 687                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 688                 #address-cells = <1>;
 689                 #size-cells = <0>;
 690                 pinctrl-names = "default", "gpio";
 691                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 692                 pinctrl-1 = <&i2c5_gpio>;
 693                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 694                 clocks = <&clk_gates7 0>;
 695                 rockchip,check-idle = <1>;
 696                 status = "disabled";
 697         };
 698
 699         fb: fb{
 700                 compatible = "rockchip,rk-fb";
 701                 rockchip,disp-mode = <DUAL>;
 702         };
 703
 704         rk_screen: rk_screen{
 705                         compatible = "rockchip,screen";
 706         };
 707
 708         dsihost0: mipi@ff960000{
 709                 compatible = "rockchip,rk32-dsi";
 710                 rockchip,prop = <0>;
 711                 reg = <0xff960000 0x4000>;
 712                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 713                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 714                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 715                 status = "disabled";
 716         };
 717
 718         dsihost1: mipi@ff964000{
 719                 compatible = "rockchip,rk32-dsi";
 720                 rockchip,prop = <1>;
 721                 reg = <0xff964000 0x4000>;
 722                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 723                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 724                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 725                 status = "disabled";
 726         };
 727
 728         lvds: lvds@ff96c000 {
 729                 compatible = "rockchip,rk32-lvds";
 730                 reg = <0xff96c000 0x4000>;
 731                 clocks = <&clk_gates16 7>;
 732                 clock-names = "pclk_lvds";
 733         };
 734
 735         edp: edp@ff970000 {
 736                 compatible = "rockchip,rk32-edp";
 737                 reg = <0xff970000 0x4000>;
 738                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 739                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 740                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 741         };
 742
 743         hdmi: hdmi@ff980000 {
 744                 compatible = "rockchip,rk3288-hdmi";
 745                 reg = <0xff980000 0x20000>;
 746                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 747                 pinctrl-names = "default", "sleep";
 748                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 749                 pinctrl-1 = <&i2c5_gpio>;
 750                 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
 751                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
 752                 status = "disabled";
 753         };
 754
 755         lcdc0: lcdc@ff930000 {
 756                 compatible = "rockchip,rk3288-lcdc";
 757                 rockchip,prop = <PRMRY>;
 758                 rockchip,pwr18 = <0>;
 759                 rockchip,iommu-enabled = <1>;
 760                 reg = <0xff930000 0x10000>;
 761                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 762                 pinctrl-names = "default", "gpio";
 763                 pinctrl-0 = <&lcdc0_lcdc>;
 764                 pinctrl-1 = <&lcdc0_gpio>;
 765                 status = "disabled";
 766                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
 767                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 768         };
 769
 770         lcdc1: lcdc@ff940000 {
 771                 compatible = "rockchip,rk3288-lcdc";
 772                 rockchip,prop = <EXTEND>;
 773                 rochchip,pwr18 = <0>;
 774                 rockchip,iommu-enabled = <1>;
 775                 reg = <0xff940000 0x10000>;
 776                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 777                 status = "disabled";
 778                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
 779                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 780         };
 781
 782         adc: adc@ff100000 {
 783                 compatible = "rockchip,saradc";
 784                 reg = <0xff100000 0x100>;
 785                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 786                 #io-channel-cells = <1>;
 787                 io-channel-ranges;
 788                 rockchip,adc-vref = <1800>;
 789                 clock-frequency = <1000000>;
 790                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 791                 clock-names = "saradc", "pclk_saradc";
 792                 status = "disabled";
 793         };
 794
 795         rga@ff920000 {
 796                 compatible = "rockchip,rga";
 797                 reg = <0xff920000 0x1000>;
 798                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 799                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 800                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 801         };
 802
 803         i2s: rockchip-i2s@0xff890000 {
 804                 compatible = "rockchip-i2s";
 805                 reg = <0xff890000 0x10000>;
 806                 i2s-id = <0>;
 807                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 808                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 809                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 810                 dmas = <&pdma0 0>, <&pdma0 1>;
 811                 //#dma-cells = <2>;
 812                 dma-names = "tx", "rx";
 813                 pinctrl-names = "default", "sleep";
 814                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 815                 pinctrl-1 = <&i2s_gpio>;
 816         };
 817
 818         spdif: rockchip-spdif@0xff8b0000 {
 819                 compatible = "rockchip-spdif";
 820                 reg = <0xff8b0000 0x10000>;     //8channel
 821                 //reg = <ff880000 0x10000>;//2channel
 822                 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
 823                 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
 824                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 825                 dmas = <&pdma0 3>;
 826                 //dmas = <&pdma0 2>; //2channel
 827                 //#dma-cells = <1>;
 828                 dma-names = "tx";
 829                 pinctrl-names = "default";
 830                 pinctrl-0 = <&spdif_tx>;
 831         };
 832
 833         vop1pwm: pwm@ff9401a0 {
 834                 compatible = "rockchip,vop-pwm";
 835                 reg = <0xff9401a0 0x10>;
 836                 #pwm-cells = <2>;
 837                 pinctrl-names = "default";
 838                 pinctrl-0 = <&vop1_pwm_pin>;
 839                 clocks = <&clk_gates13 11>;
 840                 clock-names = "pclk_pwm";
 841                 status = "disabled";
 842         };
 843
 844         vop0pwm: pwm@ff9301a0 {
 845                 compatible = "rockchip,vop-pwm";
 846                 reg = <0xff9301a0 0x10>;
 847                 #pwm-cells = <2>;
 848                 pinctrl-names = "default";
 849                 pinctrl-0 = <&vop0_pwm_pin>;
 850                 clocks = <&clk_gates13 10>;
 851                 clock-names = "pclk_pwm";
 852                 status = "disabled";
 853         };
 854
 855         pwm0: pwm@ff680000 {
 856                 compatible = "rockchip,rk-pwm";
 857                 reg = <0xff680000 0x10>;
 858                 #pwm-cells = <2>;
 859                 pinctrl-names = "default";
 860                 pinctrl-0 = <&pwm0_pin>;
 861                 clocks = <&clk_gates11 11>;
 862                 clock-names = "pclk_pwm";
 863                 status = "disabled";
 864         };
 865
 866         pwm1: pwm@ff680010 {
 867                 compatible = "rockchip,rk-pwm";
 868                 reg = <0xff680010 0x10>;
 869                 #pwm-cells = <2>;
 870                 pinctrl-names = "default";
 871                 pinctrl-0 = <&pwm1_pin>;
 872                 clocks = <&clk_gates11 11>;
 873                 clock-names = "pclk_pwm";
 874                 status = "disabled";
 875         };
 876
 877         pwm2: pwm@ff680020 {
 878                 compatible = "rockchip,rk-pwm";
 879                 reg = <0xff680020 0x10>;
 880                 #pwm-cells = <2>;
 881                 pinctrl-names = "default";
 882                 pinctrl-0 = <&pwm2_pin>;
 883                 clocks = <&clk_gates11 11>;
 884                 clock-names = "pclk_pwm";
 885                 status = "disabled";
 886         };
 887
 888         pwm3: pwm@ff680030 {
 889                 compatible = "rockchip,rk-pwm";
 890                 reg = <0xff680030 0x10>;
 891                 #pwm-cells = <2>;
 892                 pinctrl-names = "default";
 893                 pinctrl-0 = <&pwm3_pin>;
 894                 clocks = <&clk_gates11 11>;
 895                 clock-names = "pclk_pwm";
 896                 status = "disabled";
 897         };
 898
 899         dvfs {
 900                 temp-limit-enable = <1>;
 901                 target-temp = <80>;
 902
 903                 vd_arm: vd_arm {
 904                         regulator_name = "vdd_arm";
 905                         suspend_volt = <1000>; //mV
 906                         pd_core {
 907                                 clk_core_dvfs_table: clk_core {
 908                                         operating-points = <
 909                                                 /* KHz    uV */
 910                                                 312000 1100000
 911                                                 504000 1100000
 912                                                 816000 1100000
 913                                                 1008000 1100000
 914                                                 >;
 915                                         temp-channel = <1>;
 916                                         normal-temp-limit = <
 917                                         /*delta-temp    delta-freq*/
 918                                                 3       96000
 919                                                 6       144000
 920                                                 9       192000
 921                                                 15      384000
 922                                                 >;
 923                                         performance-temp-limit = <
 924                                                 /*temp    freq*/
 925                                                 110     816000
 926                                                 >;
 927                                         status = "okay";
 928                                 };
 929                         };
 930                 };
 931
 932                 vd_logic: vd_logic {
 933                         regulator_name = "vdd_logic";
 934                         suspend_volt = <1000>; //mV
 935                         pd_ddr {
 936                                 clk_ddr_dvfs_table: clk_ddr {
 937                                         operating-points = <
 938                                                 /* KHz    uV */
 939                                                 200000 1200000
 940                                                 300000 1200000
 941                                                 400000 1200000
 942                                                 >;
 943                                         status = "disabled";
 944                                 };
 945                         };
 946
 947                         pd_vio {
 948                                 aclk_vio1_dvfs_table: aclk_vio1 {
 949                                         operating-points = <
 950                                                 /* KHz    uV */
 951                                                 100000 1100000
 952                                                 500000 1100000
 953                                                 >;
 954                                         status = "okay";
 955                                 };
 956                         };
 957                 };
 958
 959                 vd_gpu: vd_gpu {
 960                         regulator_name = "vdd_gpu";
 961                         suspend_volt = <1000>; //mV
 962                         pd_gpu {
 963                                 clk_gpu_dvfs_table: clk_gpu {
 964                                         operating-points = <
 965                                                 /* KHz    uV */
 966                                                 200000 1200000
 967                                                 300000 1200000
 968                                                 400000 1200000
 969                                                 >;
 970                                         status = "okay";
 971                                 };
 972                         };
 973                 };
 974         };
 975
 976         ion {
 977                 compatible = "rockchip,ion";
 978                 #address-cells = <1>;
 979                 #size-cells = <0>;
 980
 981                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 982                         compatible = "rockchip,ion-reserve";
 983                         rockchip,ion_heap = <1>;
 984                         reg = <0x00000000 0x20000000>; /* 512MB */
 985                 };
 986                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 987                         rockchip,ion_heap = <3>;
 988                 };
 989         };
 990
 991         vpu: vpu_service@ff9a0000 {
 992                 compatible = "vpu_service";
 993                 reg = <0xff9a0000 0x800>;
 994                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 995                 interrupt-names = "irq_enc", "irq_dec";
 996                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 997                 clock-names = "aclk_vcodec", "hclk_vcodec";
 998                 name = "vpu_service";
 999                 //status = "disabled";
1000         };
1001
1002         hevc: hevc_service@ff9c0000 {
1003                 compatible = "rockchip,hevc_service";
1004                 reg = <0xff9c0000 0x800>;
1005                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1006                 interrupt-names = "irq_dec";
1007                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1008                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1009                 name = "hevc_service";
1010                 //status = "disabled";
1011         };
1012
1013         iep: iep@ff900000 {
1014                 compatible = "rockchip,iep";
1015                 reg = <0xff900000 0x800>;
1016                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1017                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1018                 clock-names = "aclk_iep", "hclk_iep";
1019                 status = "okay";
1020         };
1021
1022         dwc_control_usb: dwc-control-usb@ff770284 {
1023                 compatible = "rockchip,rk3288-dwc-control-usb";
1024                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1025                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1026                       <0xff770320 0x14>, <0xff770334 0x14>,
1027                       <0xff770348 0x10>, <0xff770358 0x08>,
1028                       <0xff770360 0x08>;
1029                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1030                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1031                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1032                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1033                             "GRF_UOC4_BASE";
1034                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1035                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1036                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1037                 interrupt-names = "otg_id", "otg_bvalid",
1038                                   "otg_linestate", "host0_linestate",
1039                                   "host1_linestate";
1040                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1041                          <&otgphy1_480m>, <&otgphy2_480m>;
1042                 clock-names = "hclk_usb_peri", "usbphy_480m",
1043                               "usbphy1_480m", "usbphy2_480m";
1044
1045                 usb_bc {
1046                         compatible = "synopsys,phy";
1047                                         /* offset bit mask */
1048                         rk_usb,bvalid     = <0x288 14 1>;
1049                         rk_usb,iddig      = <0x288 17 1>;
1050                         rk_usb,dcdenb     = <0x328 14 1>;
1051                         rk_usb,vdatsrcenb = <0x328  7 1>;
1052                         rk_usb,vdatdetenb = <0x328  6 1>;
1053                         rk_usb,chrgsel    = <0x328  5 1>;
1054                         rk_usb,chgdet     = <0x2cc 23 1>;
1055                         rk_usb,fsvminus   = <0x2cc 25 1>;
1056                         rk_usb,fsvplus    = <0x2cc 24 1>;
1057                 };
1058         };
1059
1060         usb0: usb@ff580000 {
1061                 compatible = "rockchip,rk3288_usb20_otg";
1062                 reg = <0xff580000 0x40000>;
1063                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1064                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1065                 clock-names = "clk_usbphy0", "hclk_usb0";
1066                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1067                 rockchip,usb-mode = <0>;
1068         };
1069
1070         usb1: usb@ff540000 {
1071                 compatible = "rockchip,rk3288_usb20_host";
1072                 reg = <0xff540000 0x40000>;
1073                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1074                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1075                          <&usbphy_480m>;
1076                 clock-names = "clk_usbphy1", "hclk_usb1",
1077                               "usbphy_480m";
1078         };
1079
1080         usb2: usb@ff500000 {
1081                 compatible = "rockchip,rk3288_rk_ehci_host";
1082                 reg = <0xff500000 0x20000>;
1083                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1084                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1085                 clock-names = "clk_usbphy2", "hclk_usb2";
1086         };
1087
1088         usb3: usb@ff520000 {
1089                 compatible = "rockchip,rk3288_rk_ohci_host";
1090                 reg = <0xff520000 0x20000>;
1091                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1092                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1093                 clock-names = "clk_usbphy3", "hclk_usb3";
1094         };
1095
1096         hsic: hsic@ff5c0000 {
1097                 compatible = "rockchip,rk3288_rk_hsic_host";
1098                 reg = <0xff5c0000 0x40000>;
1099                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1100                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1101                          <&hsicphy_12m>, <&usbphy_480m>,
1102                          <&otgphy1_480m>, <&otgphy2_480m>;
1103                 clock-names = "hsicphy_480m", "hclk_hsic",
1104                               "hsicphy_12m", "usbphy_480m",
1105                               "hsic_usbphy1", "hsic_usbphy2";
1106         };
1107
1108         gmac: eth@ff290000 {
1109                 compatible = "rockchip,gmac";
1110                 reg = <0xff290000 0x10000>;
1111                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1112                 interrupt-names = "macirq";
1113                 clocks = <&clk_mac>, <&clk_gates5 0>,
1114                          <&clk_gates5 1>, <&clk_gates5 2>,
1115                          <&clk_gates5 3>, <&clk_gates8 0>,
1116                          <&clk_gates8 1>;
1117                 clock-names = "clk_mac", "mac_clk_rx",
1118                               "mac_clk_tx", "clk_mac_ref",
1119                               "clk_mac_refout", "aclk_mac",
1120                               "pclk_mac";
1121                 //phy-mode = "rmii";
1122                 phy-mode = "rgmii";
1123                 pinctrl-names = "default";
1124                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1125         };
1126
1127         gpu {
1128                 compatible = "arm,malit764",
1129                              "arm,malit76x",
1130                              "arm,malit7xx",
1131                              "arm,mali-midgard";
1132                 reg = <0xffa30000 0x10000>;
1133                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1134                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1135                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1136                 interrupt-names = "JOB", "MMU", "GPU";
1137         };
1138
1139         iep_mmu {
1140                 dbgname = "iep";
1141                 compatible = "iommu,iep_mmu";
1142                 reg = <0xff900800 0x100>;
1143                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1144                 interrupt-names = "iep_mmu";
1145         };
1146
1147         vip_mmu {
1148                 dbgname = "vip";
1149                 compatible = "iommu,vip_mmu";
1150                 reg = <0xff950800 0x100>;
1151                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1152                 interrupt-names = "vip_mmu";
1153         };
1154
1155         vopb_mmu {
1156                 dbgname = "vopb";
1157                 compatible = "iommu,vopb_mmu";
1158                 reg = <0xff930300 0x100>;
1159                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1160                 interrupt-names = "vopb_mmu";
1161         };
1162
1163         vopl_mmu {
1164                 dbgname = "vopl";
1165                 compatible = "iommu,vopl_mmu";
1166                 reg = <0xff940300 0x100>;
1167                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1168                 interrupt-names = "vopl_mmu";
1169         };
1170
1171         hevc_mmu {
1172                 dbgname = "hevc";
1173                 compatible = "iommu,hevc_mmu";
1174                 reg = <0xff9c0440 0x100>,
1175                       <0xff9c0480 0x100>;
1176                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1177                 interrupt-names = "hevc_mmu";
1178         };
1179
1180         vpu_mmu {
1181                 dbgname = "vpu";
1182                 compatible = "iommu,vpu_mmu";
1183                 reg = <0xff9a0800 0x100>;
1184                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1185                 interrupt-names = "vpu_mmu";
1186         };
1187
1188         isp_mmu {
1189                 dbgname = "isp_mmu";
1190                 compatible = "iommu,isp_mmu";
1191                 reg = <0xff914000 0x100>,
1192                       <0xff915000 0x100>;
1193                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1194                 interrupt-names = "isp_mmu";
1195         };
1196
1197         rockchip_suspend {
1198                 rockchip,ctrbits = <
1199                         (0
1200                          |RKPM_CTR_PWR_DMNS
1201                          |RKPM_CTR_GTCLKS
1202                          |RKPM_CTR_PLLS
1203                  //      |RKPM_CTR_GPIOS
1204                 //       |RKPM_CTR_SYSCLK_DIV
1205                 //       |RKPM_CTR_IDLEAUTO_MD
1206                 //       |RKPM_CTR_ARMOFF_LPMD
1207                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1208                         )
1209                         >;
1210                 rockchip,pmic-suspend_gpios = <
1211                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1212                         >;
1213                 rockchip,pmic-resume_gpios = <
1214                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1215                         >;
1216
1217         };
1218
1219         isp: isp@ff910000{
1220                 compatible = "rockchip,isp";
1221                 reg = <0xff910000 0x10000>;
1222                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1223                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1224                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1225                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1226                 pinctrl-0 = <&isp_mipi>;
1227                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1228                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1229                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1230                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1231                 pinctrl-5 = <&isp_mipi>;
1232                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1233                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1234                 pinctrl-8 = <&isp_flash_trigger>;
1235                 rockchip,isp,mipiphy = <2>;
1236                 rockchip,isp,cifphy = <1>;
1237                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1238                 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1239                 status = "okay";
1240         };
1241
1242         tsadc: tsadc@ff280000 {
1243                 compatible = "rockchip,tsadc";
1244                 reg = <0xff280000 0x100>;
1245                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1246                 #io-channel-cells = <1>;
1247                 io-channel-ranges;
1248                 clock-frequency = <10000>;
1249                 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1250                 clock-names = "tsadc", "pclk_tsadc";
1251                 pinctrl-names = "default", "tsadc_int";
1252                 pinctrl-0 = <&tsadc_gpio>;
1253                 pinctrl-1 = <&tsadc_int>;
1254                 tsadc-ht-temp = <120>;
1255                 tsadc-ht-reset-cru = <1>;
1256                 tsadc-ht-pull-gpio = <0>;
1257                 status = "okay";
1258         };
1259
1260         lcdc_vdd_domain: lcdc-vdd-domain {
1261                 compatible = "rockchip,io_vol_domain";
1262                 pinctrl-names = "default", "1.8V", "3.3V";
1263                 pinctrl-0 = <&lcdc_vcc>;
1264                 pinctrl-1 = <&lcdc_vcc_18>;
1265                 pinctrl-2 = <&lcdc_vcc_33>;
1266         };
1267
1268         dpio_vdd_domain: dpio-vdd-domain {
1269                 compatible = "rockchip,io_vol_domain";
1270                 pinctrl-names = "default", "1.8V", "3.3V";
1271                 pinctrl-0 = <&dvp_vcc>;
1272                 pinctrl-1 = <&dvp_vcc_18>;
1273                 pinctrl-2 = <&dvp_vcc_33>;
1274         };
1275
1276         flash0_vdd_domain: flash0-vdd-domain {
1277                 compatible = "rockchip,io_vol_domain";
1278                 pinctrl-names = "default", "1.8V", "3.3V";
1279                 pinctrl-0 = <&flash0_vcc>;
1280                 pinctrl-1 = <&flash0_vcc_18>;
1281                 pinctrl-2 = <&flash0_vcc_33>;
1282         };
1283
1284         flash1_vdd_domain: flash1-vdd-domain {
1285                 compatible = "rockchip,io_vol_domain";
1286                 pinctrl-names = "default", "1.8V", "3.3V";
1287                 pinctrl-0 = <&flash1_vcc>;
1288                 pinctrl-1 = <&flash1_vcc_18>;
1289                 pinctrl-2 = <&flash1_vcc_33>;
1290         };
1291
1292         apio3_vdd_domain: apio3-vdd-domain {
1293                 compatible = "rockchip,io_vol_domain";
1294                 pinctrl-names = "default", "1.8V", "3.3V";
1295                 pinctrl-0 = <&wifi_vcc>;
1296                 pinctrl-1 = <&wifi_vcc_18>;
1297                 pinctrl-2 = <&wifi_vcc_33>;
1298         };
1299
1300         apio5_vdd_domain: apio5-vdd-domain {
1301                 compatible = "rockchip,io_vol_domain";
1302                 pinctrl-names = "default", "1.8V", "3.3V";
1303                 pinctrl-0 = <&bb_vcc>;
1304                 pinctrl-1 = <&bb_vcc_18>;
1305                 pinctrl-2 = <&bb_vcc_33>;
1306         };
1307
1308         apio4_vdd_domain: apio4-vdd-domain {
1309                 compatible = "rockchip,io_vol_domain";
1310                 pinctrl-names = "default", "1.8V", "3.3V";
1311                 pinctrl-0 = <&audio_vcc>;
1312                 pinctrl-1 = <&audio_vcc_18>;
1313                 pinctrl-2 = <&audio_vcc_33>;
1314         };
1315
1316         apio1_vdd_domain: apio0-vdd-domain {
1317                 compatible = "rockchip,io_vol_domain";
1318                 pinctrl-names = "default", "1.8V", "3.3V";
1319                 pinctrl-0 = <&gpio30_vcc>;
1320                 pinctrl-1 = <&gpio30_vcc_18>;
1321                 pinctrl-2 = <&gpio30_vcc_33>;
1322         };
1323
1324         apio2_vdd_domain: apio2-vdd-domain {
1325                 compatible = "rockchip,io_vol_domain";
1326                 pinctrl-names = "default", "1.8V", "3.3V";
1327                 pinctrl-0 = <&gpio1830_vcc>;
1328                 pinctrl-1 = <&gpio1830_vcc_18>;
1329                 pinctrl-2 = <&gpio1830_vcc_33>;
1330         };
1331
1332         sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1333                 compatible = "rockchip,io_vol_domain";
1334                 pinctrl-names = "default", "1.8V", "3.3V";
1335                 pinctrl-0 = <&sdcard_vcc>;
1336                 pinctrl-1 = <&sdcard_vcc_18>;
1337                 pinctrl-2 = <&sdcard_vcc_33>;
1338         };
1339 };