arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include "skeleton.dtsi"
   3 #include "rk3288-pinctrl.dtsi"
   4
   5 / {
   6         compatible = "rockchip,rk3288";
   7         interrupt-parent = <&gic>;
   8
   9         aliases {
  10                 serial2 = &uart_dbg;
  11                 i2c0 = &i2c0;
  12                 i2c1 = &i2c1;
  13                 i2c2 = &i2c2;
  14                 i2c3 = &i2c3;
  15                 i2c4 = &i2c4;
  16         };
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a15";
  25                         reg = <0x500>;
  26                 };
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a15";
  30                         reg = <0x501>;
  31                 };
  32                 cpu@2 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a15";
  35                         reg = <0x502>;
  36                 };
  37                 cpu@3 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a15";
  40                         reg = <0x503>;
  41                 };
  42         };
  43
  44         gic: interrupt-controller@ffc01000 {
  45                 compatible = "arm,cortex-a15-gic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <3>;
  48                 #address-cells = <0>;
  49                 reg = <0xffc01000 0x1000>,
  50                       <0xffc02000 0x1000>;
  51         };
  52
  53         timer {
  54                 compatible = "arm,armv7-timer";
  55                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  56                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  57                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  58                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  59                 clock-frequency = <24000000>;
  60         };
  61
  62         timer@ff810000 {
  63                 compatible = "rockchip,timer";
  64                 reg = <0xff810000 0x20>;
  65                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  66                 rockchip,broadcast = <1>;
  67         };
  68
  69         timer@ff810020 {
  70                 compatible = "rockchip,timer";
  71                 reg = <0xff810020 0x20>;
  72                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  73                 rockchip,clocksource = <1>;
  74                 rockchip,count-up = <1>;
  75         };
  76
  77         uart_dbg: serial@ff690000 {
  78                 compatible = "rockchip,serial";
  79                 reg = <0xff690000 0x100>;
  80                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  81                 clock-frequency = <24000000>;
  82                 reg-shift = <2>;
  83                 reg-io-width = <4>;
  84                 status = "disabled";
  85         };
  86
  87         fiq-debugger {
  88                 compatible = "rockchip,fiq-debugger";
  89                 rockchip,serial-id = <2>;
  90                 rockchip,signal-irq = <106>;
  91                 rockchip,wake-irq = <0>;
  92                 status = "disabled";
  93         };
  94
  95
  96
  97         i2c0: i2c@ff650000 {
  98                 compatible = "rockchip,rk30-i2c";
  99                 reg = <0xff650000 0x1000>;
 100                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 //pinctrl-names = "default", "gpio";
 104                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 105                 //pinctrl-1 = <&i2c0_gpio>;
 106                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 107                 //clocks = <&clk_gates8 4>;
 108                 rockchip,check-idle = <1>;
 109                 status = "disabled";
 110         };
 111
 112         i2c1: i2c@ff140000 {
 113                 compatible = "rockchip,rk30-i2c";
 114                 reg = <0xff140000 0x1000>;
 115                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 //pinctrl-names = "default", "gpio";
 119                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 120                 //pinctrl-1 = <&i2c1_gpio>;
 121                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 122                 //clocks = <&clk_gates8 5>;
 123            rockchip,check-idle = <1>;
 124       status = "disabled";
 125
 126
 127         };
 128
 129         i2c2: i2c@ff660000 {
 130                 compatible = "rockchip,rk30-i2c";
 131                 reg = <0xff660000 0x1000>;
 132                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135                 //pinctrl-names = "default", "gpio";
 136                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 137                 //pinctrl-1 = <&i2c2_gpio>;
 138                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 139                 //clocks = <&clk_gates8 6>;
 140                 rockchip,check-idle = <1>;
 141                 status = "disabled";
 142         };
 143
 144         i2c3: i2c@ff150000 {
 145                 compatible = "rockchip,rk30-i2c";
 146                 reg = <0xff150000 0x1000>;
 147                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150                 //pinctrl-names = "default", "gpio";
 151                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 152                 //pinctrl-1 = <&i2c2_gpio>;
 153                 //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 154                 //clocks = <&clk_gates8 6>;
 155                 rockchip,check-idle = <1>;
 156                 status = "disabled";
 157         };
 158
 159         i2c4: i2c@ff160000 {
 160                 compatible = "rockchip,rk30-i2c";
 161                 reg = <0xff160000 0x1000>;
 162                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165                 //pinctrl-names = "default", "gpio";
 166                 //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 167                 //pinctrl-1 = <&i2c3_gpio>;
 168                 //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 169                 //clocks = <&clk_gates8 7>;
 170                 rockchip,check-idle = <1>;
 171                 status = "disabled";
 172         };
 173
 174
 175    i2c5: i2c@ff170000 {
 176        compatible = "rockchip,rk30-i2c";
 177        reg = <0xff170000 0x1000>;
 178        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 179        #address-cells = <1>;
 180        #size-cells = <0>;
 181                 //pinctrl-names = "default", "gpio";
 182                 //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 183                 //pinctrl-1 = <&i2c4_gpio>;
 184                 //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 185                 //clocks = <&clk_gates8 8>;
 186        rockchip,check-idle = <1>;
 187        status = "disabled";
 188     };
 189
 190         edp: edp@ff970000 {
 191                 compatible = "rockchip,rk32-edp";
 192                 reg = <0xff970000 0x4000>;
 193                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 194                 status = "disabled";
 195         };
 196
 197         hdmi:hdmi@ff980000 {
 198                 compatible = "rockchip,rk3288-hdmi";
 199                 reg = <0xff980000 0x20000>;
 200                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,hdmi_lcdc_source = <1>;
 202                 pinctrl-names = "default", "gpio";
 203                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 204                 pinctrl-1 = <&i2c5_gpio>;
 205                 status = "disabled";
 206          };
 207
 208     adc: adc@ff100000 {
 209         compatible = "rockchip,saradc";
 210         reg = <0xff100000 0x100>;
 211         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 212         #io-channel-cells = <1>;
 213         io-channel-ranges;
 214         rockchip,adc-vref = <1800>;
 215         clock-frequency = <1000000>;
 216         clock-names = "saradc", "pclk_saradc";
 217         status = "disabled";
 218     };
 219
 220         rga@ff920000 {
 221                 compatible = "rockchip,rga";
 222                 reg = <0xff920000 0x1000>;
 223                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 224                 clock-names = "hclk_rga", "aclk_rga";
 225   };
 226
 227         i2s: rockchip-i2s@0xff890000 {
 228                 compatible = "rockchip-i2s";
 229                 reg = <0xff890000 0x10000>;
 230                 i2s-id = <0>;
 231         //      clocks = <&clk_i2s>;
 232         //      clock-names = "i2s_clk","i2s_mclk";
 233                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 234         //      dmas = <&pdma0 0>,
 235         //              <&pdma0 1>;
 236                 //#dma-cells = <2>;
 237         //      dma-names = "tx", "rx";
 238         //      pinctrl-names = "default", "sleep";
 239         //      pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
 240         //      pinctrl-1 = <&i2s0_gpio>;
 241         };
 242
 243         spdif: rockchip-spdif@0xff8b0000 {
 244                 compatible = "rockchip-spdif";
 245                 reg = <0xff8b0000 0x10000>;     //8channel
 246                 //reg = <ff880000 0x2000>;//2channel
 247         //      clocks = <&clk_spdif>;
 248         //      clock-names = "spdif_mclk";
 249                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 250         //      dmas = <&pdma0 8>;
 251                 //#dma-cells = <1>;
 252         //      dma-names = "tx";
 253         //      pinctrl-names = "default";
 254         //      pinctrl-0 = <&spdif_tx>;
 255         };
 256         ion: ion{
 257                 compatible = "rockchip,ion";
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 rockchip,ion-heap@1 { /* CMA HEAP */
 261                         reg = <1>;
 262                 };
 263                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 264                         reg = <3>;
 265                 };
 266         };
 267
 268         mmc: mshc@ff0c0000 {
 269            compatible = "rockchip,rk_mmc";
 270            reg = <0xff0c0000 0x4000>;
 271            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 272            #address-cells = <1>;
 273            #size-cells = <0>;
 274            //pinctrl-names = "default","suspend";
 275            //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>;
 276            //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 277            //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 278            //clock-names = "hclk_mmc","mmc";
 279            clock-frequency = <50000000>;
 280            clock-freq-min-max = <400000 50000000>;
 281            num-slots = <1>;
 282            supports-highspeed;
 283            broken-cd;
 284            card-detect-delay = <200>;
 285            pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
 286            fifo-depth = <0x100>;
 287            emmc-compatible = <0>;
 288            status = "okay";
 289         };
 290
 291         sdio0: mshc@ff0d0000 {
 292                 compatible = "rockchip,rk_mmc";
 293             reg = <0xff0d0000 0x4000>;
 294             interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
 295             #address-cells = <1>;
 296             #size-cells = <0>;
 297             //pinctrl-names = "default";
 298             //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 299             //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 300             //clock-names = "hclk_sdio0","sdio0";
 301         clock-frequency = <50000000>;
 302         clock-freq-min-max = <400000 50000000>;
 303         num-slots = <1>;
 304             supports-highspeed;
 305             fifo-depth = <0x100>;
 306             emmc-compatible = <0>;
 307             status = "disabled";
 308         };
 309
 310         sdio1: mshc@ff0e0000 {
 311                 compatible = "rockchip,rk_mmc";
 312             reg = <0xff0e0000 0x4000>;
 313             interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
 314             #address-cells = <1>;
 315             #size-cells = <0>;
 316             //pinctrl-names = "default";
 317             //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 318             //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 319             //clock-names = "hclk_sdio1","sdio1";
 320         clock-frequency = <50000000>;
 321         clock-freq-min-max = <400000 50000000>;
 322         num-slots = <1>;
 323             supports-highspeed;
 324             fifo-depth = <0x100>;
 325             emmc-compatible = <0>;
 326             status = "disabled";
 327         };
 328
 329         emmc: mshc@ff0f0000 {
 330                 compatible = "rockchip,rk_mmc";
 331             reg = <0xff0f0000 0x4000>;
 332             interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
 333             #address-cells = <1>;
 334             #size-cells = <0>;
 335             //pinctrl-names = "default";
 336             //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 337             //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 338             //clock-names = "hclk_sdio1","sdio1";
 339         clock-frequency = <50000000>;
 340         clock-freq-min-max = <400000 50000000>;
 341         num-slots = <1>;
 342             supports-highspeed;
 343             fifo-depth = <0x100>;
 344             emmc-compatible = <1>;
 345             status = "disabled";
 346         };
 347
 348 };