arch/arm/boot/dts/rk3288-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3288.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x0 0xFF760000 0x01b0>;
  22
  23                 fixed_rate_cons {
  24                         compatible = "rockchip,rk-fixed-rate-cons";
  25
  26                         xin24m: xin24m {
  27                                 compatible = "rockchip,rk-fixed-clock";
  28                                 clock-output-names = "xin24m";
  29                                 clock-frequency = <24000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         xin12m: xin12m {
  34                                 compatible = "rockchip,rk-fixed-clock";
  35                                 clocks = <&xin24m>;
  36                                 clock-output-names = "xin12m";
  37                                 clock-frequency = <12000000>;
  38                                 #clock-cells = <0>;
  39                         };
  40
  41                         xin32k: xin32k {
  42                                 compatible = "rockchip,rk-fixed-clock";
  43                                 clock-output-names = "xin32k";
  44                                 clock-frequency = <32000>;
  45                                 #clock-cells = <0>;
  46                         };
  47
  48                         io_27m_in: io_27m_in {
  49                                 compatible = "rockchip,rk-fixed-clock";
  50                                 clock-output-names = "io_27m_in";
  51                                 clock-frequency = <27000000>;
  52                                 #clock-cells = <0>;
  53                         };
  54
  55                         dummy: dummy {
  56                                 compatible = "rockchip,rk-fixed-clock";
  57                                 clock-output-names = "dummy";
  58                                 clock-frequency = <0>;
  59                                 #clock-cells = <0>;
  60                         };
  61
  62                         dummy_cpll: dummy_cpll {
  63                                 compatible = "rockchip,rk-fixed-clock";
  64                                 clock-output-names = "dummy_cpll";
  65                                 clock-frequency = <0>;
  66                                 #clock-cells = <0>;
  67                         };
  68
  69                         i2s_clkin: i2s_clkin {
  70                                 compatible = "rockchip,rk-fixed-clock";
  71                                 clock-output-names = "i2s_clkin";
  72                                 clock-frequency = <0>;
  73                                 #clock-cells = <0>;
  74                         };
  75
  76                         edp_24m_clkin: edp_24m_clkin {
  77                                 compatible = "rockchip,rk-fixed-clock";
  78                                 #clock-cells = <0>;
  79                                 clock-output-names = "edp_24m_clkin";
  80                                 clock-frequency = <0>;
  81                         };
  82
  83                         gmac_clkin: gmac_clkin {
  84                                 compatible = "rockchip,rk-fixed-clock";
  85                                 #clock-cells = <0>;
  86                                 clock-output-names = "gmac_clkin";
  87                                 clock-frequency = <125000000>;
  88                         };
  89
  90                         clk_hsadc_ext: clk_hsadc_ext {
  91                                 compatible = "rockchip,rk-fixed-clock";
  92                                 #clock-cells = <0>;
  93                                 clock-output-names = "clk_hsadc_ext";
  94                                 clock-frequency = <0>;
  95                         };
  96
  97                         jtag_clkin: jtag_clkin {
  98                                 compatible = "rockchip,rk-fixed-clock";
  99                                 #clock-cells = <0>;
 100                                 clock-output-names = "jtag_clkin";
 101                                 clock-frequency = <0>;
 102                         };
 103
 104                         pclkin_cif: pclkin_cif {
 105                                 compatible = "rockchip,rk-fixed-clock";
 106                                 #clock-cells = <0>;
 107                                 clock-output-names = "pclkin_cif";
 108                                 clock-frequency = <0>;
 109                         };
 110
 111                         pclkin_isp: pclkin_isp {
 112                                 compatible = "rockchip,rk-fixed-clock";
 113                                 #clock-cells = <0>;
 114                                 clock-output-names = "pclkin_isp";
 115                                 clock-frequency = <0>;
 116                         };
 117
 118                         hsadc_0_tsp: hsadc_0_tsp {
 119                                 compatible = "rockchip,rk-fixed-clock";
 120                                 #clock-cells = <0>;
 121                                 clock-output-names = "hsadc_0_tsp";
 122                                 clock-frequency = <0>;
 123                         };
 124
 125                         hsadc_1_tsp: hsadc_1_tsp {
 126                                 compatible = "rockchip,rk-fixed-clock";
 127                                 #clock-cells = <0>;
 128                                 clock-output-names = "hsadc_1_tsp";
 129                                 clock-frequency = <0>;
 130                         };
 131
 132                 };
 133
 134                 fixed_factor_cons {
 135                                 compatible = "rockchip,rk-fixed-factor-cons";
 136
 137                         otgphy0_480m: otgphy0_480m {
 138                                 compatible = "rockchip,rk-fixed-factor-clock";
 139                                 clocks = <&clk_gates13 4>;
 140                                 clock-output-names = "otgphy0_480m";
 141                                 clock-div = <1>;
 142                                 clock-mult = <20>;
 143                                 #clock-cells = <0>;
 144                         };
 145
 146                         otgphy1_480m: otgphy1_480m {
 147                                 compatible = "rockchip,rk-fixed-factor-clock";
 148                                 clocks = <&clk_gates13 5>;
 149                                 clock-output-names = "otgphy1_480m";
 150                                 clock-div = <1>;
 151                                 clock-mult = <20>;
 152                                 #clock-cells = <0>;
 153                         };
 154
 155                         otgphy2_480m: otgphy2_480m {
 156                                 compatible = "rockchip,rk-fixed-factor-clock";
 157                                 clocks = <&clk_gates13 6>;
 158                                 clock-output-names = "otgphy2_480m";
 159                                 clock-div = <1>;
 160                                 clock-mult = <20>;
 161                                 #clock-cells = <0>;
 162                         };
 163
 164                         clk_hsadc_inv: clk_hsadc_inv {
 165                                 compatible = "rockchip,rk-fixed-factor-clock";
 166                                 clocks = <&clk_hsadc_out>;
 167                                 clock-output-names = "clk_hsadc_inv";
 168                                 clock-div = <1>;
 169                                 clock-mult = <1>;
 170                                 #clock-cells = <0>;
 171                         };
 172
 173                         pclkin_cif_inv: pclkin_cif_inv {
 174                                 compatible = "rockchip,rk-fixed-factor-clock";
 175                                 clocks = <&clk_gates16 0>;
 176                                 clock-output-names = "pclkin_cif_inv";
 177                                 clock-div = <1>;
 178                                 clock-mult = <1>;
 179                                 #clock-cells = <0>;
 180                         };
 181
 182                         pclkin_isp_inv: pclkin_isp_inv {
 183                                 compatible = "rockchip,rk-fixed-factor-clock";
 184                                 clocks = <&clk_gates16 3>;
 185                                 clock-output-names = "pclkin_isp_inv";
 186                                 clock-div = <1>;
 187                                 clock-mult = <1>;
 188                                 #clock-cells = <0>;
 189                         };
 190
 191                         hclk_vepu: hclk_vepu {
 192                                 compatible = "rockchip,rk-fixed-factor-clock";
 193                                 clocks = <&clk_vepu>;
 194                                 clock-output-names = "hclk_vepu";
 195                                 clock-div = <4>;
 196                                 clock-mult = <1>;
 197                                 #clock-cells = <0>;
 198                         };
 199
 200                         hclk_vdpu: hclk_vdpu {
 201                                 compatible = "rockchip,rk-fixed-factor-clock";
 202                                 clocks = <&clk_vdpu>;
 203                                 clock-output-names = "hclk_vdpu";
 204                                 clock-div = <4>;
 205                                 clock-mult = <1>;
 206                                 #clock-cells = <0>;
 207                         };
 208                 };
 209
 210                 pd_cons {
 211                         compatible = "rockchip,rk-pd-cons";
 212
 213                         pd_gpu: pd_gpu {
 214                                 compatible = "rockchip,rk-pd-clock";
 215                                 clock-output-names = "pd_gpu";
 216                                 rockchip,pd-id = <CLK_PD_GPU>;
 217                                 #clock-cells = <0>;
 218                         };
 219
 220                         pd_video: pd_video {
 221                                 compatible = "rockchip,rk-pd-clock";
 222                                 clock-output-names = "pd_video";
 223                                 rockchip,pd-id = <CLK_PD_VIDEO>;
 224                                 #clock-cells = <0>;
 225                         };
 226
 227                         pd_vio: pd_vio {
 228                                 compatible = "rockchip,rk-pd-clock";
 229                                 clock-output-names = "pd_vio";
 230                                 rockchip,pd-id = <CLK_PD_VIO>;
 231                                 #clock-cells = <0>;
 232                         };
 233
 234                         pd_hevc: pd_hevc {
 235                                 compatible = "rockchip,rk-pd-clock";
 236                                 clock-output-names = "pd_hevc";
 237                                 rockchip,pd-id = <CLK_PD_HEVC>;
 238                                 #clock-cells = <0>;
 239                         };
 240
 241                         pd_edp: pd_edp {
 242                                 compatible = "rockchip,rk-pd-clock";
 243                                 clocks = <&pd_vio>;
 244                                 clock-output-names = "pd_edp";
 245                                 rockchip,pd-id = <CLK_PD_VIRT>;
 246                                 #clock-cells = <0>;
 247                         };
 248
 249                         pd_vop0: pd_vop0 {
 250                                 compatible = "rockchip,rk-pd-clock";
 251                                 clocks = <&pd_vio>;
 252                                 clock-output-names = "pd_vop0";
 253                                 rockchip,pd-id = <CLK_PD_VIRT>;
 254                                 #clock-cells = <0>;
 255                         };
 256
 257                         pd_vop1: pd_vop1 {
 258                                 compatible = "rockchip,rk-pd-clock";
 259                                 clocks = <&pd_vio>;
 260                                 clock-output-names = "pd_vop1";
 261                                 rockchip,pd-id = <CLK_PD_VIRT>;
 262                                 #clock-cells = <0>;
 263                         };
 264
 265                         pd_isp: pd_isp {
 266                                 compatible = "rockchip,rk-pd-clock";
 267                                 clocks = <&pd_vio>;
 268                                 clock-output-names = "pd_isp";
 269                                 rockchip,pd-id = <CLK_PD_VIRT>;
 270                                 #clock-cells = <0>;
 271                         };
 272
 273                         pd_iep: pd_iep {
 274                                 compatible = "rockchip,rk-pd-clock";
 275                                 clocks = <&pd_vio>;
 276                                 clock-output-names = "pd_iep";
 277                                 rockchip,pd-id = <CLK_PD_VIRT>;
 278                                 #clock-cells = <0>;
 279                         };
 280
 281                         pd_rga: pd_rga {
 282                                 compatible = "rockchip,rk-pd-clock";
 283                                 clocks = <&pd_vio>;
 284                                 clock-output-names = "pd_rga";
 285                                 rockchip,pd-id = <CLK_PD_VIRT>;
 286                                 #clock-cells = <0>;
 287                         };
 288
 289                         pd_mipicsi: pd_mipicsi {
 290                                 compatible = "rockchip,rk-pd-clock";
 291                                 clocks = <&pd_vio>;
 292                                 clock-output-names = "pd_mipicsi";
 293                                 rockchip,pd-id = <CLK_PD_VIRT>;
 294                                 #clock-cells = <0>;
 295                         };
 296
 297                         pd_mipidsi: pd_mipidsi {
 298                                 compatible = "rockchip,rk-pd-clock";
 299                                 clocks = <&pd_vio>;
 300                                 clock-output-names = "pd_mipidsi";
 301                                 rockchip,pd-id = <CLK_PD_VIRT>;
 302                                 #clock-cells = <0>;
 303                         };
 304
 305                         pd_lvds: pd_lvds {
 306                                 compatible = "rockchip,rk-pd-clock";
 307                                 clocks = <&pd_vio>;
 308                                 clock-output-names = "pd_lvds";
 309                                 rockchip,pd-id = <CLK_PD_VIRT>;
 310                                 #clock-cells = <0>;
 311                         };
 312
 313                         pd_hdmi: pd_hdmi {
 314                                 compatible = "rockchip,rk-pd-clock";
 315                                 clocks = <&pd_vio>;
 316                                 clock-output-names = "pd_hdmi";
 317                                 rockchip,pd-id = <CLK_PD_VIRT>;
 318                                 #clock-cells = <0>;
 319                         };
 320
 321                 };
 322
 323
 324                 clock_regs {
 325                         compatible = "rockchip,rk-clock-regs";
 326                         #address-cells = <1>;
 327                         #size-cells = <1>;
 328                         reg = <0x0000 0x3ff>;
 329                         ranges;
 330
 331                         /* PLL control regs */
 332                         pll_cons {
 333                                 compatible = "rockchip,rk-pll-cons";
 334                                 #address-cells = <1>;
 335                                 #size-cells = <1>;
 336                                 ranges ;
 337
 338                                 clk_apll: pll-clk@0000 {
 339                                         compatible = "rockchip,rk3188-pll-clk";
 340                                         reg = <0x0000 0x10>;
 341                                         mode-reg = <0x0050 0>;
 342                                         status-reg = <0x0284 6>;
 343                                         clocks = <&xin24m>;
 344                                         clock-output-names = "clk_apll";
 345                                         rockchip,pll-type = <CLK_PLL_3288_APLL>;
 346                                         #clock-cells = <0>;
 347                                 };
 348
 349                                 clk_dpll: pll-clk@0010 {
 350                                         compatible = "rockchip,rk3188-pll-clk";
 351                                         reg = <0x0010 0x10>;
 352                                         mode-reg = <0x0050 4>;
 353                                         status-reg = <0x0284 5>;
 354                                         clocks = <&xin24m>;
 355                                         clock-output-names = "clk_dpll";
 356                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 357                                         #clock-cells = <0>;
 358                                 };
 359
 360                                 clk_cpll: pll-clk@0020 {
 361                                         compatible = "rockchip,rk3188-pll-clk";
 362                                         reg = <0x0020 0x10>;
 363                                         mode-reg = <0x0050 8>;
 364                                         status-reg = <0x0284 7>;
 365                                         clocks = <&xin24m>;
 366                                         clock-output-names = "clk_cpll";
 367                                         rockchip,pll-type = <CLK_PLL_3188PLUS_AUTO>;
 368                                         #clock-cells = <0>;
 369                                         #clock-init-cells = <1>;
 370                                 };
 371
 372                                 clk_gpll: pll-clk@0030 {
 373                                         compatible = "rockchip,rk3188-pll-clk";
 374                                         reg = <0x0030 0x10>;
 375                                         mode-reg = <0x0050 12>;
 376                                         status-reg = <0x0284 8>;
 377                                         clocks = <&xin24m>;
 378                                         clock-output-names = "clk_gpll";
 379                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 380                                         #clock-cells = <0>;
 381                                         #clock-init-cells = <1>;
 382                                 };
 383
 384                                 clk_npll: pll-clk@0040 {
 385                                         compatible = "rockchip,rk3188-pll-clk";
 386                                         reg = <0x0040 0x10>;
 387                                         mode-reg = <0x0050 14>;
 388                                         status-reg = <0x0284 9>;
 389                                         clocks = <&xin24m>;
 390                                         clock-output-names = "clk_npll";
 391                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 392                                         #clock-cells = <0>;
 393                                         #clock-init-cells = <1>;
 394                                 };
 395
 396                         };
 397
 398                         /* Select control regs */
 399                         clk_sel_cons {
 400                                 compatible = "rockchip,rk-sel-cons";
 401                                 #address-cells = <1>;
 402                                 #size-cells = <1>;
 403                                 ranges;
 404
 405                                 clk_sel_con0: sel-con@0060 {
 406                                         compatible = "rockchip,rk3188-selcon";
 407                                         reg = <0x0060 0x4>;
 408                                         #address-cells = <1>;
 409                                         #size-cells = <1>;
 410
 411                                         aclk_core_m0: aclk_core_m0_div {
 412                                                 compatible = "rockchip,rk3188-div-con";
 413                                                 rockchip,bits = <0 4>;
 414                                                 clocks = <&clk_core>;
 415                                                 clock-output-names = "aclk_core_m0";
 416                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 417                                                 #clock-cells = <0>;
 418                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 419                                         };
 420
 421                                         aclk_core_mp: aclk_core_mp_div {
 422                                                 compatible = "rockchip,rk3188-div-con";
 423                                                 rockchip,bits = <4 4>;
 424                                                 clocks = <&clk_core>;
 425                                                 clock-output-names = "aclk_core_mp";
 426                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 427                                                 #clock-cells = <0>;
 428                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 429                                         };
 430
 431                                         clk_core_div: clk_core_div {
 432                                                 compatible = "rockchip,rk3188-div-con";
 433                                                 rockchip,bits = <8 5>;
 434                                                 clocks = <&clk_core>;
 435                                                 clock-output-names = "clk_core";
 436                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 437                                                 #clock-cells = <0>;
 438                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 439                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 440                                                                         CLK_SET_RATE_NO_REPARENT)>;
 441                                         };
 442
 443                                         /* reg[14:13]: reserved */
 444
 445                                         clk_core: clk_core_mux {
 446                                                 compatible = "rockchip,rk3188-mux-con";
 447                                                 rockchip,bits = <15 1>;
 448                                                 clocks = <&clk_apll>, <&clk_gates0 2>;
 449                                                 clock-output-names = "clk_core";
 450                                                 #clock-cells = <0>;
 451                                                 #clock-init-cells = <1>;
 452                                         };
 453
 454                                 };
 455
 456                                 clk_sel_con1: sel-con@0064 {
 457                                         compatible = "rockchip,rk3188-selcon";
 458                                         reg = <0x0064 0x4>;
 459                                         #address-cells = <1>;
 460                                         #size-cells = <1>;
 461
 462                                         aclk_bus: aclk_bus_div {
 463                                                 compatible = "rockchip,rk3188-div-con";
 464                                                 rockchip,bits = <0 3>;
 465                                                 clocks = <&aclk_bus_src_div>;
 466                                                 clock-output-names = "aclk_bus";
 467                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 468                                                 #clock-cells = <0>;
 469                                                 #clock-init-cells = <1>;
 470                                         };
 471
 472                                         aclk_bus_src_div: aclk_bus_src_div {
 473                                                 compatible = "rockchip,rk3188-div-con";
 474                                                 rockchip,bits = <3 5>;
 475                                                 clocks = <&aclk_bus_src>;
 476                                                 clock-output-names = "aclk_bus_src";
 477                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 478                                                 #clock-cells = <0>;
 479                                                 rockchip,clkops-idx =
 480                                                         <CLKOPS_RATE_MUX_DIV>;
 481                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 482                                         };
 483
 484                                         hclk_bus: hclk_bus_div {
 485                                                 compatible = "rockchip,rk3188-div-con";
 486                                                 rockchip,bits = <8 2>;
 487                                                 clocks = <&aclk_bus>;
 488                                                 clock-output-names = "hclk_bus";
 489                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 490                                                 rockchip,div-relations =
 491                                                                 <0x0 1
 492                                                                  0x1 2
 493                                                                  0x3 4>;
 494                                                 #clock-cells = <0>;
 495                                                 #clock-init-cells = <1>;
 496                                         };
 497
 498                                         /* reg[11:10]: reserved */
 499
 500                                         pclk_bus: pclk_bus_div {
 501                                                 compatible = "rockchip,rk3188-div-con";
 502                                                 rockchip,bits = <12 3>;
 503                                                 clocks = <&aclk_bus>;
 504                                                 clock-output-names = "pclk_bus";
 505                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 506                                                 #clock-cells = <0>;
 507                                                 #clock-init-cells = <1>;
 508                                         };
 509
 510                                         aclk_bus_src: aclk_bus_src_mux {
 511                                                 compatible = "rockchip,rk3188-mux-con";
 512                                                 rockchip,bits = <15 1>;
 513                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
 514                                                 /*clocks = <&clk_gates0 11>, <&clk_gates0 10>; FIXME*/
 515                                                 clock-output-names = "aclk_bus_src";
 516                                                 #clock-cells = <0>;
 517                                                 #clock-init-cells = <1>;
 518                                         };
 519
 520                                 };
 521
 522                                 clk_sel_con2: sel-con@0068 {
 523                                         compatible = "rockchip,rk3188-selcon";
 524                                         reg = <0x0068 0x4>;
 525                                         #address-cells = <1>;
 526                                         #size-cells = <1>;
 527
 528                                         clk_tsadc: clk_tsadc_div {
 529                                                 compatible = "rockchip,rk3188-div-con";
 530                                                 rockchip,bits = <0 6>;
 531                                                 clocks = <&xin32k>;
 532                                                 clock-output-names = "clk_tsadc";
 533                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 534                                                 #clock-cells = <0>;
 535                                         };
 536
 537                                         /* reg[7:6]: reserved */
 538
 539                                         testout_div: testout_div {
 540                                                 compatible = "rockchip,rk3188-div-con";
 541                                                 rockchip,bits = <8 5>;
 542                                                 clocks = <&dummy>;
 543                                                 clock-output-names = "testout_div";
 544                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 545                                                 #clock-cells = <0>;
 546                                         };
 547
 548                                         /* reg[15:13]: reserved */
 549                                 };
 550
 551                                 clk_sel_con3: sel-con@006c {
 552                                         compatible = "rockchip,rk3188-selcon";
 553                                         reg = <0x006c 0x4>;
 554                                         #address-cells = <1>;
 555                                         #size-cells = <1>;
 556
 557                                         clk_uart4_div: clk_uart4_div {
 558                                                 compatible = "rockchip,rk3188-div-con";
 559                                                 rockchip,bits = <0 7>;
 560                                                 clocks = <&uart_pll_mux>;
 561                                                 clock-output-names = "clk_uart4_div";
 562                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 563                                                 #clock-cells = <0>;
 564                                         };
 565
 566                                         /* reg[7]: reserved */
 567
 568                                         clk_uart4: uart4_mux {
 569                                                 compatible = "rockchip,rk3188-mux-con";
 570                                                 rockchip,bits = <8 2>;
 571                                                 clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>, <&dummy>;
 572                                                 clock-output-names = "clk_uart4";
 573                                                 #clock-cells = <0>;
 574                                                 rockchip,clkops-idx =
 575                                                         <CLKOPS_RATE_RK3288_I2S>;
 576                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 577                                         };
 578
 579                                         /* reg[15:10]: reserved */
 580
 581                                 };
 582
 583                                 clk_sel_con4: sel-con@0070 {
 584                                         compatible = "rockchip,rk3188-selcon";
 585                                         reg = <0x0070 0x4>;
 586                                         #address-cells = <1>;
 587                                         #size-cells = <1>;
 588
 589                                         i2s_pll_div: i2s_pll_div {
 590                                                 compatible = "rockchip,rk3188-div-con";
 591                                                 rockchip,bits = <0 7>;
 592                                                 clocks = <&clk_i2s_pll>;
 593                                                 clock-output-names = "clk_i2s_pll";
 594                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 595                                                 #clock-cells = <0>;
 596                                                 rockchip,clkops-idx =
 597                                                         <CLKOPS_RATE_MUX_DIV>;
 598                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 599                                         };
 600
 601                                         /* reg[7]: reserved */
 602
 603                                         clk_i2s: i2s_mux {
 604                                                 compatible = "rockchip,rk3188-mux-con";
 605                                                 rockchip,bits = <8 2>;
 606                                                 clocks = <&clk_i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
 607                                                 clock-output-names = "clk_i2s";
 608                                                 #clock-cells = <0>;
 609                                                 rockchip,clkops-idx =
 610                                                         <CLKOPS_RATE_RK3288_I2S>;
 611                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 612                                         };
 613
 614                                         /* reg[11:10]: reserved */
 615
 616                                         clk_i2s_out: i2s_outclk_mux {
 617                                                 compatible = "rockchip,rk3188-mux-con";
 618                                                 rockchip,bits = <12 1>;
 619                                                 clocks = <&clk_i2s>, <&xin12m>;
 620                                                 clock-output-names = "clk_i2s_out";
 621                                                 #clock-cells = <0>;
 622                                         };
 623
 624                                         /* reg[14:13]: reserved */
 625
 626                                         clk_i2s_pll: i2s_pll_mux {
 627                                                 compatible = "rockchip,rk3188-mux-con";
 628                                                 rockchip,bits = <15 1>;
 629                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
 630                                                 clock-output-names = "clk_i2s_pll";
 631                                                 #clock-cells = <0>;
 632                                                 #clock-init-cells = <1>;
 633                                         };
 634                                 };
 635
 636                                 clk_sel_con5: sel-con@0074 {
 637                                         compatible = "rockchip,rk3188-selcon";
 638                                         reg = <0x0074 0x4>;
 639                                         #address-cells = <1>;
 640                                         #size-cells = <1>;
 641
 642                                         spdif_div: spdif_div {
 643                                                 compatible = "rockchip,rk3188-div-con";
 644                                                 rockchip,bits = <0 7>;
 645                                                 clocks = <&clk_spdif_pll>;
 646                                                 clock-output-names = "spdif_div";
 647                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 648                                                 #clock-cells = <0>;
 649                                         };
 650
 651                                         /* reg[7]: reserved */
 652
 653                                         clk_spdif: spdif_mux {
 654                                                 compatible = "rockchip,rk3188-mux-con";
 655                                                 rockchip,bits = <8 2>;
 656                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>, <&dummy>;
 657                                                 clock-output-names = "clk_spdif";
 658                                                 #clock-cells = <0>;
 659                                                 rockchip,clkops-idx =
 660                                                         <CLKOPS_RATE_RK3288_I2S>;
 661                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 662                                         };
 663
 664                                         /* reg[14:10]: reserved */
 665
 666                                         clk_spdif_pll: spdif_pll_mux {
 667                                                 compatible = "rockchip,rk3188-mux-con";
 668                                                 rockchip,bits = <15 1>;
 669                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
 670                                                 clock-output-names = "clk_spdif_pll";
 671                                                 #clock-cells = <0>;
 672                                                 #clock-init-cells = <1>;
 673                                         };
 674                                 };
 675
 676                                 clk_sel_con6: sel-con@0078 {
 677                                         compatible = "rockchip,rk3188-selcon";
 678                                         reg = <0x0078 0x4>;
 679                                         #address-cells = <1>;
 680                                         #size-cells = <1>;
 681
 682                                         clk_isp_div: clk_isp_div {
 683                                                 compatible = "rockchip,rk3188-div-con";
 684                                                 rockchip,bits = <0 6>;
 685                                                 clocks = <&clk_isp>;
 686                                                 clock-output-names = "clk_isp";
 687                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 688                                                 #clock-cells = <0>;
 689                                                 rockchip,clkops-idx =
 690                                                         <CLKOPS_RATE_MUX_DIV>;
 691                                         };
 692
 693                                         clk_isp: clk_isp_mux {
 694                                                 compatible = "rockchip,rk3188-mux-con";
 695                                                 rockchip,bits = <6 2>;
 696                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
 697                                                 clock-output-names = "clk_isp";
 698                                                 #clock-cells = <0>;
 699                                                 #clock-init-cells = <1>;
 700                                         };
 701
 702                                         clk_isp_jpe_div: clk_isp_jpe_div {
 703                                                 compatible = "rockchip,rk3188-div-con";
 704                                                 rockchip,bits = <8 6>;
 705                                                 clocks = <&clk_isp_jpe>;
 706                                                 clock-output-names = "clk_isp_jpe";
 707                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 708                                                 #clock-cells = <0>;
 709                                                 rockchip,clkops-idx =
 710                                                         <CLKOPS_RATE_MUX_DIV>;
 711                                         };
 712
 713                                         clk_isp_jpe: clk_isp_jpe_mux {
 714                                                 compatible = "rockchip,rk3188-mux-con";
 715                                                 rockchip,bits = <14 2>;
 716                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
 717                                                 clock-output-names = "clk_isp_jpe";
 718                                                 #clock-cells = <0>;
 719                                                 #clock-init-cells = <1>;
 720                                         };
 721                                 };
 722
 723                                 clk_sel_con7: sel-con@007c {
 724                                         compatible = "rockchip,rk3188-selcon";
 725                                         reg = <0x007c 0x4>;
 726                                         #address-cells = <1>;
 727                                         #size-cells = <1>;
 728
 729                                         uart4_frac: uart4_frac {
 730                                                 compatible = "rockchip,rk3188-frac-con";
 731                                                 clocks = <&clk_uart4_div>;
 732                                                 clock-output-names = "uart4_frac";
 733                                                 /* numerator    denominator */
 734                                                 rockchip,bits = <0 32>;
 735                                                 rockchip,clkops-idx =
 736                                                         <CLKOPS_RATE_FRAC>;
 737                                                 #clock-cells = <0>;
 738                                         };
 739                                 };
 740
 741                                 clk_sel_con8: sel-con@0080 {
 742                                         compatible = "rockchip,rk3188-selcon";
 743                                         reg = <0x0080 0x4>;
 744                                         #address-cells = <1>;
 745                                         #size-cells = <1>;
 746
 747                                         i2s_frac: i2s_frac {
 748                                                 compatible = "rockchip,rk3188-frac-con";
 749                                                 clocks = <&clk_i2s_pll>;
 750                                                 clock-output-names = "i2s_frac";
 751                                                 /* numerator    denominator */
 752                                                 rockchip,bits = <0 32>;
 753                                                 rockchip,clkops-idx =
 754                                                         <CLKOPS_RATE_FRAC>;
 755                                                 #clock-cells = <0>;
 756                                         };
 757                                 };
 758
 759                                 clk_sel_con9: sel-con@0084 {
 760                                         compatible = "rockchip,rk3188-selcon";
 761                                         reg = <0x0084 0x4>;
 762                                         #address-cells = <1>;
 763                                         #size-cells = <1>;
 764
 765                                         spdif_frac: spdif_frac {
 766                                                 compatible = "rockchip,rk3188-frac-con";
 767                                                 clocks = <&spdif_div>;
 768                                                 clock-output-names = "spdif_frac";
 769                                                 /* numerator    denominator */
 770                                                 rockchip,bits = <0 32>;
 771                                                 rockchip,clkops-idx =
 772                                                         <CLKOPS_RATE_FRAC>;
 773                                                 #clock-cells = <0>;
 774                                         };
 775                                 };
 776
 777                                 clk_sel_con10: sel-con@0088 {
 778                                         compatible = "rockchip,rk3188-selcon";
 779                                         reg = <0x0088 0x4>;
 780                                         #address-cells = <1>;
 781                                         #size-cells = <1>;
 782
 783                                         aclk_peri_div: aclk_peri_div {
 784                                                 compatible = "rockchip,rk3188-div-con";
 785                                                 rockchip,bits = <0 5>;
 786                                                 clocks = <&aclk_peri>;
 787                                                 clock-output-names = "aclk_peri";
 788                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 789                                                 #clock-cells = <0>;
 790                                                 rockchip,clkops-idx =
 791                                                         <CLKOPS_RATE_MUX_DIV>;
 792                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 793                                         };
 794
 795                                         /* reg[7:5]: reserved */
 796
 797                                         hclk_peri: hclk_peri_div {
 798                                                 compatible = "rockchip,rk3188-div-con";
 799                                                 rockchip,bits = <8 2>;
 800                                                 clocks = <&aclk_peri>;
 801                                                 clock-output-names = "hclk_peri";
 802                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 803                                                 rockchip,div-relations =
 804                                                                 <0x0 1
 805                                                                  0x1 2
 806                                                                  0x2 4>;
 807                                                 #clock-cells = <0>;
 808                                                 #clock-init-cells = <1>;
 809                                         };
 810
 811                                         /* reg[11:10]: reserved */
 812
 813                                         pclk_peri: pclk_peri_div {
 814                                                 compatible = "rockchip,rk3188-div-con";
 815                                                 rockchip,bits = <12 2>;
 816                                                 clocks = <&aclk_peri>;
 817                                                 clock-output-names = "pclk_peri";
 818                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 819                                                 rockchip,div-relations =
 820                                                                 <0x0 1
 821                                                                  0x1 2
 822                                                                  0x2 4
 823                                                                  0x3 8>;
 824                                                 #clock-cells = <0>;
 825                                                 #clock-init-cells = <1>;
 826                                         };
 827
 828                                         /* reg[14]: reserved */
 829
 830                                         aclk_peri: aclk_peri_mux {
 831                                                 compatible = "rockchip,rk3188-mux-con";
 832                                                 rockchip,bits = <15 1>;
 833                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
 834                                                 clock-output-names = "aclk_peri";
 835                                                 #clock-cells = <0>;
 836                                                 #clock-init-cells = <1>;
 837                                         };
 838                                 };
 839
 840                                 clk_sel_con11: sel-con@008c {
 841                                         compatible = "rockchip,rk3188-selcon";
 842                                         reg = <0x008c 0x4>;
 843                                         #address-cells = <1>;
 844                                         #size-cells = <1>;
 845
 846                                         clk_sdmmc_div: clk_sdmmc_div {
 847                                                 compatible = "rockchip,rk3188-div-con";
 848                                                 rockchip,bits = <0 6>;
 849                                                 clocks = <&clk_sdmmc>;
 850                                                 clock-output-names = "clk_sdmmc";
 851                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 852                                                 #clock-cells = <0>;
 853                                                 rockchip,clkops-idx =
 854                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 855                                         };
 856
 857                                         clk_sdmmc: clk_sdmmc_mux {
 858                                                 compatible = "rockchip,rk3188-mux-con";
 859                                                 rockchip,bits = <6 2>;
 860                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
 861                                                 clock-output-names = "clk_sdmmc";
 862                                                 #clock-cells = <0>;
 863                                         };
 864
 865                                         ehci1phy_12m_div: ehci1phy_12m_div {
 866                                                 compatible = "rockchip,rk3188-div-con";
 867                                                 rockchip,bits = <8 6>;
 868                                                 clocks = <&ehci1phy_480m>;
 869                                                 clock-output-names = "ehci1phy_12m_div";
 870                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 871                                                 #clock-cells = <0>;
 872                                         };
 873
 874                                 };
 875
 876                                 clk_sel_con12: sel-con@0090 {
 877                                         compatible = "rockchip,rk3188-selcon";
 878                                         reg = <0x0090 0x4>;
 879                                         #address-cells = <1>;
 880                                         #size-cells = <1>;
 881
 882                                         clk_sdio0_div: clk_sdio0_div {
 883                                                 compatible = "rockchip,rk3188-div-con";
 884                                                 rockchip,bits = <0 6>;
 885                                                 clocks = <&clk_sdio0>;
 886                                                 clock-output-names = "clk_sdio0";
 887                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 888                                                 #clock-cells = <0>;
 889                                                 rockchip,clkops-idx =
 890                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 891                                         };
 892
 893                                         clk_sdio0: clk_sdio0_mux {
 894                                                 compatible = "rockchip,rk3188-mux-con";
 895                                                 rockchip,bits = <6 2>;
 896                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
 897                                                 clock-output-names = "clk_sdio0";
 898                                                 #clock-cells = <0>;
 899                                         };
 900
 901                                         clk_emmc_div: clk_emmc_div {
 902                                                 compatible = "rockchip,rk3188-div-con";
 903                                                 rockchip,bits = <8 6>;
 904                                                 clocks = <&clk_emmc>;
 905                                                 clock-output-names = "clk_emmc";
 906                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 907                                                 #clock-cells = <0>;
 908                                                 rockchip,clkops-idx =
 909                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 910                                         };
 911
 912                                         clk_emmc: clk_emmc_mux {
 913                                                 compatible = "rockchip,rk3188-mux-con";
 914                                                 rockchip,bits = <14 2>;
 915                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
 916                                                 clock-output-names = "clk_emmc";
 917                                                 #clock-cells = <0>;
 918                                         };
 919                                 };
 920
 921                                 clk_sel_con13: sel-con@0094 {
 922                                         compatible = "rockchip,rk3188-selcon";
 923                                         reg = <0x0094 0x4>;
 924                                         #address-cells = <1>;
 925                                         #size-cells = <1>;
 926
 927                                         clk_uart0_pll_div: clk_uart0_pll_div {
 928                                                 compatible = "rockchip,rk3188-div-con";
 929                                                 rockchip,bits = <0 7>;
 930                                                 clocks = <&clk_uart0_pll>;
 931                                                 clock-output-names = "clk_uart0_pll";
 932                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 933                                                 #clock-cells = <0>;
 934                                                 rockchip,clkops-idx =
 935                                                         <CLKOPS_RATE_MUX_DIV>;
 936                                         };
 937
 938                                         /* reg[7]: reserved */
 939
 940                                         clk_uart0: uart0_mux {
 941                                                 compatible = "rockchip,rk3188-mux-con";
 942                                                 rockchip,bits = <8 2>;
 943                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>;
 944                                                 clock-output-names = "clk_uart0";
 945                                                 #clock-cells = <0>;
 946                                                 rockchip,clkops-idx =
 947                                                         <CLKOPS_RATE_RK3288_I2S>;
 948                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 949                                         };
 950
 951                                         /* reg[10]: reserved */
 952
 953                                         usbphy_480m: usbphy_480m_mux {
 954                                                 compatible = "rockchip,rk3188-mux-con";
 955                                                 rockchip,bits = <11 2>;
 956                                                 clocks = <&otgphy1_480m>, <&otgphy2_480m>, <&otgphy0_480m>;
 957                                                 clock-output-names = "usbphy_480m";
 958                                                 #clock-cells = <0>;
 959                                                 rockchip,clkops-idx =
 960                                                         <CLKOPS_RATE_RK3288_USB480M>;
 961                                                 #clock-init-cells = <1>;
 962                                         };
 963
 964                                         clk_uart0_pll: clk_uart0_pll_mux {
 965                                                 compatible = "rockchip,rk3188-mux-con";
 966                                                 rockchip,bits = <13 2>;
 967                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 968                                                 clock-output-names = "clk_uart0_pll";
 969                                                 #clock-cells = <0>;
 970                                         };
 971
 972                                         uart_pll_mux: uart_pll_mux {
 973                                                 compatible = "rockchip,rk3188-mux-con";
 974                                                 rockchip,bits = <15 1>;
 975                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
 976                                                 clock-output-names = "uart_pll_mux";
 977                                                 #clock-cells = <0>;
 978                                                 #clock-init-cells = <1>;
 979                                         };
 980                                 };
 981
 982                                 clk_sel_con14: sel-con@0098 {
 983                                         compatible = "rockchip,rk3188-selcon";
 984                                         reg = <0x0098 0x4>;
 985                                         #address-cells = <1>;
 986                                         #size-cells = <1>;
 987
 988                                         clk_uart1_div: clk_uart1_div {
 989                                                 compatible = "rockchip,rk3188-div-con";
 990                                                 rockchip,bits = <0 7>;
 991                                                 clocks = <&uart_pll_mux>;
 992                                                 clock-output-names = "clk_uart1_div";
 993                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 994                                                 #clock-cells = <0>;
 995                                         };
 996
 997                                         /* reg[7]: reserved */
 998
 999                                         clk_uart1: uart1_mux {
1000                                                 compatible = "rockchip,rk3188-mux-con";
1001                                                 rockchip,bits = <8 2>;
1002                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>;
1003                                                 clock-output-names = "clk_uart1";
1004                                                 #clock-cells = <0>;
1005                                                 rockchip,clkops-idx =
1006                                                         <CLKOPS_RATE_RK3288_I2S>;
1007                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1008                                         };
1009
1010                                         /* reg[15:10]: reserved */
1011                                 };
1012
1013                                 clk_sel_con15: sel-con@009c {
1014                                         compatible = "rockchip,rk3188-selcon";
1015                                         reg = <0x009c 0x4>;
1016                                         #address-cells = <1>;
1017                                         #size-cells = <1>;
1018
1019                                         clk_uart2_div: clk_uart2_div {
1020                                                 compatible = "rockchip,rk3188-div-con";
1021                                                 rockchip,bits = <0 7>;
1022                                                 clocks = <&uart_pll_mux>;
1023                                                 clock-output-names = "clk_uart2_div";
1024                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1025                                                 #clock-cells = <0>;
1026                                         };
1027
1028                                         /* reg[7]: reserved */
1029
1030                                         clk_uart2: uart2_mux {
1031                                                 compatible = "rockchip,rk3188-mux-con";
1032                                                 rockchip,bits = <8 2>;
1033                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>;
1034                                                 clock-output-names = "clk_uart2";
1035                                                 #clock-cells = <0>;
1036                                                 rockchip,clkops-idx =
1037                                                         <CLKOPS_RATE_RK3288_I2S>;
1038                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1039                                         };
1040
1041                                         /* reg[15:10]: reserved */
1042                                 };
1043
1044                                 clk_sel_con16: sel-con@00a0 {
1045                                         compatible = "rockchip,rk3188-selcon";
1046                                         reg = <0x00a0 0x4>;
1047                                         #address-cells = <1>;
1048                                         #size-cells = <1>;
1049
1050                                         clk_uart3_div: clk_uart3_div {
1051                                                 compatible = "rockchip,rk3188-div-con";
1052                                                 rockchip,bits = <0 7>;
1053                                                 clocks = <&uart_pll_mux>;
1054                                                 clock-output-names = "clk_uart3_div";
1055                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1056                                                 #clock-cells = <0>;
1057                                         };
1058
1059                                         /* reg[7]: reserved */
1060
1061                                         clk_uart3: uart3_mux {
1062                                                 compatible = "rockchip,rk3188-mux-con";
1063                                                 rockchip,bits = <8 2>;
1064                                                 clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>;
1065                                                 clock-output-names = "clk_uart3";
1066                                                 #clock-cells = <0>;
1067                                                 rockchip,clkops-idx =
1068                                                         <CLKOPS_RATE_RK3288_I2S>;
1069                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1070                                         };
1071
1072                                         /* reg[15:10]: reserved */
1073                                 };
1074
1075                                 clk_sel_con17: sel-con@00a4 {
1076                                         compatible = "rockchip,rk3188-selcon";
1077                                         reg = <0x00a4 0x4>;
1078                                         #address-cells = <1>;
1079                                         #size-cells = <1>;
1080
1081                                         uart0_frac: uart0_frac {
1082                                                 compatible = "rockchip,rk3188-frac-con";
1083                                                 clocks = <&clk_uart0_pll>;
1084                                                 clock-output-names = "uart0_frac";
1085                                                 /* numerator    denominator */
1086                                                 rockchip,bits = <0 32>;
1087                                                 rockchip,clkops-idx =
1088                                                         <CLKOPS_RATE_FRAC>;
1089                                                 #clock-cells = <0>;
1090                                         };
1091                                 };
1092
1093                                 clk_sel_con18: sel-con@00a8 {
1094                                         compatible = "rockchip,rk3188-selcon";
1095                                         reg = <0x00a8 0x4>;
1096                                         #address-cells = <1>;
1097                                         #size-cells = <1>;
1098
1099                                         uart1_frac: uart1_frac {
1100                                                 compatible = "rockchip,rk3188-frac-con";
1101                                                 clocks = <&clk_uart1_div>;
1102                                                 clock-output-names = "uart1_frac";
1103                                                 /* numerator    denominator */
1104                                                 rockchip,bits = <0 32>;
1105                                                 rockchip,clkops-idx =
1106                                                         <CLKOPS_RATE_FRAC>;
1107                                                 #clock-cells = <0>;
1108                                         };
1109                                 };
1110
1111                                 clk_sel_con19: sel-con@00ac {
1112                                         compatible = "rockchip,rk3188-selcon";
1113                                         reg = <0x00ac 0x4>;
1114                                         #address-cells = <1>;
1115                                         #size-cells = <1>;
1116
1117                                         uart2_frac: uart2_frac {
1118                                                 compatible = "rockchip,rk3188-frac-con";
1119                                                 clocks = <&clk_uart2_div>;
1120                                                 clock-output-names = "uart2_frac";
1121                                                 /* numerator    denominator */
1122                                                 rockchip,bits = <0 32>;
1123                                                 rockchip,clkops-idx =
1124                                                         <CLKOPS_RATE_FRAC>;
1125                                                 #clock-cells = <0>;
1126                                         };
1127
1128                                 };
1129
1130                                 clk_sel_con20: sel-con@00b0 {
1131                                         compatible = "rockchip,rk3188-selcon";
1132                                         reg = <0x00b0 0x4>;
1133                                         #address-cells = <1>;
1134                                         #size-cells = <1>;
1135
1136                                         uart3_frac: uart3_frac {
1137                                                 compatible = "rockchip,rk3188-frac-con";
1138                                                 clocks = <&clk_uart3_div>;
1139                                                 clock-output-names = "uart3_frac";
1140                                                 /* numerator    denominator */
1141                                                 rockchip,bits = <0 32>;
1142                                                 rockchip,clkops-idx =
1143                                                         <CLKOPS_RATE_FRAC>;
1144                                                 #clock-cells = <0>;
1145                                         };
1146                                 };
1147
1148                                 clk_sel_con21: sel-con@00b4 {
1149                                         compatible = "rockchip,rk3188-selcon";
1150                                         reg = <0x00b4 0x4>;
1151                                         #address-cells = <1>;
1152                                         #size-cells = <1>;
1153
1154                                         clk_mac_pll: clk_mac_pll_mux {
1155                                                 compatible = "rockchip,rk3188-mux-con";
1156                                                 rockchip,bits = <0 2>;
1157                                                 clocks = <&clk_npll>, <&dummy_cpll>, <&clk_gpll>;
1158                                                 clock-output-names = "clk_mac_pll";
1159                                                 #clock-cells = <0>;
1160                                         };
1161
1162                                         /* reg[3:2]: reserved */
1163
1164                                         clk_mac: clk_mac_mux {
1165                                                 compatible = "rockchip,rk3188-mux-con";
1166                                                 rockchip,bits = <4 1>;
1167                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1168                                                 clock-output-names = "clk_mac";
1169                                                 #clock-cells = <0>;
1170                                                 rockchip,clkops-idx =
1171                                                         <CLKOPS_RATE_MAC_REF>;
1172                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1173                                                 #clock-init-cells = <1>;
1174                                         };
1175
1176                                         /* reg[7:5]: reserved */
1177
1178                                         clk_mac_pll_div: clk_mac_pll_div {
1179                                                 compatible = "rockchip,rk3188-div-con";
1180                                                 rockchip,bits = <8 5>;
1181                                                 clocks = <&clk_mac_pll>;
1182                                                 clock-output-names = "clk_mac_pll";
1183                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1184                                                 #clock-cells = <0>;
1185                                                 rockchip,clkops-idx =
1186                                                         <CLKOPS_RATE_MUX_DIV>;
1187                                         };
1188
1189                                         /* reg[15:13]: reserved */
1190                                 };
1191
1192                                 clk_sel_con22: sel-con@00b8 {
1193                                         compatible = "rockchip,rk3188-selcon";
1194                                         reg = <0x00b8 0x4>;
1195                                         #address-cells = <1>;
1196                                         #size-cells = <1>;
1197
1198                                         clk_hsadc_pll: clk_hsadc_pll_mux {
1199                                                 compatible = "rockchip,rk3188-mux-con";
1200                                                 rockchip,bits = <0 1>;
1201                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
1202                                                 clock-output-names = "clk_hsadc_pll";
1203                                                 #clock-cells = <0>;
1204                                         };
1205 /*
1206                                         wifi_pll_mux: wifi_pll_mux {
1207                                                 compatible = "rockchip,rk3188-mux-con";
1208                                                 rockchip,bits = <1 1>;
1209                                                 clocks = <&>, <&>;
1210                                                 clock-output-names = "wifi_pll_mux";
1211                                                 #clock-cells = <0>;
1212                                         };
1213 */
1214
1215                                         /* reg[3:2]: reserved */
1216
1217                                         clk_hsadc_out: clk_hsadc_out {
1218                                                 compatible = "rockchip,rk3188-mux-con";
1219                                                 rockchip,bits = <4 1>;
1220                                                 clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
1221                                                 clock-output-names = "clk_hsadc_out";
1222                                                 #clock-cells = <0>;
1223                                                 rockchip,clkops-idx =
1224                                                         <CLKOPS_RATE_HSADC>;
1225                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1226                                         };
1227
1228                                         /* reg[6:5]: reserved */
1229
1230                                         clk_hsadc: clk_hsadc {
1231                                                 compatible = "rockchip,rk3188-mux-con";
1232                                                 rockchip,bits = <7 1>;
1233                                                 clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
1234                                                 clock-output-names = "clk_hsadc";
1235                                                 #clock-cells = <0>;
1236                                         };
1237
1238                                         clk_hsadc_pll_div: clk_hsadc_pll_div {
1239                                                 compatible = "rockchip,rk3188-div-con";
1240                                                 rockchip,bits = <8 8>;
1241                                                 clocks = <&clk_hsadc_pll>;
1242                                                 clock-output-names = "clk_hsadc_pll";
1243                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1244                                                 #clock-cells = <0>;
1245                                                 rockchip,clkops-idx =
1246                                                         <CLKOPS_RATE_MUX_DIV>;
1247                                         };
1248                                 };
1249 /*
1250                                 clk_sel_con23: sel-con@00bc {
1251                                         compatible = "rockchip,rk3188-selcon";
1252                                         reg = <0x00bc 0x4>;
1253                                         #address-cells = <1>;
1254                                         #size-cells = <1>;
1255
1256                                         wifi_frac: wifi_frac {
1257                                                 compatible = "rockchip,rk3188-frac-con";
1258                                                 clocks = <&>;
1259                                                 clock-output-names = "wifi_frac";
1260                                                 / numerator     denominator /
1261                                                 rockchip,bits = <0 32>;
1262                                                 rockchip,clkops-idx =
1263                                                         <>;
1264                                                 #clock-cells = <0>;
1265                                         };
1266                                 };
1267 */
1268
1269                                 clk_sel_con24: sel-con@00c0 {
1270                                         compatible = "rockchip,rk3188-selcon";
1271                                         reg = <0x00c0 0x4>;
1272                                         #address-cells = <1>;
1273                                         #size-cells = <1>;
1274
1275                                         /* reg[7:0]: reserved */
1276
1277                                         clk_saradc: clk_saradc_div {
1278                                                 compatible = "rockchip,rk3188-div-con";
1279                                                 rockchip,bits = <8 8>;
1280                                                 clocks = <&xin24m>;
1281                                                 clock-output-names = "clk_saradc";
1282                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1283                                                 #clock-cells = <0>;
1284                                         };
1285                                 };
1286
1287                                 clk_sel_con25: sel-con@00c4 {
1288                                         compatible = "rockchip,rk3188-selcon";
1289                                         reg = <0x00c4 0x4>;
1290                                         #address-cells = <1>;
1291                                         #size-cells = <1>;
1292
1293                                         clk_spi0_div: clk_spi0_div {
1294                                                 compatible = "rockchip,rk3188-div-con";
1295                                                 rockchip,bits = <0 7>;
1296                                                 clocks = <&clk_spi0>;
1297                                                 clock-output-names = "clk_spi0";
1298                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1299                                                 #clock-cells = <0>;
1300                                                 rockchip,clkops-idx =
1301                                                         <CLKOPS_RATE_MUX_DIV>;
1302                                         };
1303
1304                                         clk_spi0: clk_spi0_mux {
1305                                                 compatible = "rockchip,rk3188-mux-con";
1306                                                 rockchip,bits = <7 1>;
1307                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
1308                                                 clock-output-names = "clk_spi0";
1309                                                 #clock-cells = <0>;
1310                                         };
1311
1312                                         clk_spi1_div: clk_spi1_div {
1313                                                 compatible = "rockchip,rk3188-div-con";
1314                                                 rockchip,bits = <8 7>;
1315                                                 clocks = <&clk_spi1>;
1316                                                 clock-output-names = "clk_spi1";
1317                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1318                                                 #clock-cells = <0>;
1319                                                 rockchip,clkops-idx =
1320                                                         <CLKOPS_RATE_MUX_DIV>;
1321                                         };
1322
1323                                         clk_spi1: clk_spi1_mux {
1324                                                 compatible = "rockchip,rk3188-mux-con";
1325                                                 rockchip,bits = <15 1>;
1326                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
1327                                                 clock-output-names = "clk_spi1";
1328                                                 #clock-cells = <0>;
1329                                         };
1330                                 };
1331
1332                                 clk_sel_con26: sel-con@00c8 {
1333                                         compatible = "rockchip,rk3188-selcon";
1334                                         reg = <0x00c8 0x4>;
1335                                         #address-cells = <1>;
1336                                         #size-cells = <1>;
1337
1338                                         ddr_div: ddr_div {
1339                                                 compatible = "rockchip,rk3188-div-con";
1340                                                 rockchip,bits = <0 2>;
1341                                                 clocks = <&clk_ddr>;
1342                                                 clock-output-names = "clk_ddr";
1343                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1344                                                 rockchip,div-relations =
1345                                                                 <0x0 1
1346                                                                  0x1 2
1347                                                                  0x3 4>;
1348                                                 #clock-cells = <0>;
1349                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1350                                                                         CLK_SET_RATE_NO_REPARENT)>;
1351                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1352                                         };
1353
1354                                         clk_ddr: ddr_clk_pll_mux {
1355                                                 compatible = "rockchip,rk3188-mux-con";
1356                                                 rockchip,bits = <2 1>;
1357                                                 clocks = <&clk_dpll>, <&clk_gpll>;
1358                                                 clock-output-names = "clk_ddr";
1359                                                 #clock-cells = <0>;
1360                                         };
1361
1362                                         /* reg[5:3]: reserved */
1363
1364                                         clk_crypto: crypto_div {
1365                                                 compatible = "rockchip,rk3188-div-con";
1366                                                 rockchip,bits = <6 2>;
1367                                                 clocks = <&aclk_bus>;
1368                                                 clock-output-names = "clk_crypto";
1369                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1370                                                 #clock-cells = <0>;
1371                                                 #clock-init-cells = <1>;
1372                                         };
1373
1374                                         clk_cif_pll: clk_cif_pll_mux {
1375                                                 compatible = "rockchip,rk3188-mux-con";
1376                                                 rockchip,bits = <8 1>;
1377                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
1378                                                 clock-output-names = "clk_cif_pll";
1379                                                 #clock-cells = <0>;
1380                                         };
1381
1382                                         clk_cif_out_div: clk_cif_out_div {
1383                                                 compatible = "rockchip,rk3188-div-con";
1384                                                 rockchip,bits = <9 5>;
1385                                                 clocks = <&clk_cif_out>;
1386                                                 clock-output-names = "clk_cif_out";
1387                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1388                                                 #clock-cells = <0>;
1389                                                 rockchip,clkops-idx =
1390                                                         <CLKOPS_RATE_MUX_DIV>;
1391                                         };
1392
1393                                         /* reg[14]: reserved */
1394
1395                                         clk_cif_out: clk_cif_out_mux {
1396                                                 compatible = "rockchip,rk3188-mux-con";
1397                                                 rockchip,bits = <15 1>;
1398                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1399                                                 clock-output-names = "clk_cif_out";
1400                                                 #clock-cells = <0>;
1401                                         };
1402                                 };
1403
1404                                 clk_sel_con27: sel-con@00cc {
1405                                         compatible = "rockchip,rk3188-selcon";
1406                                         reg = <0x00cc 0x4>;
1407                                         #address-cells = <1>;
1408                                         #size-cells = <1>;
1409
1410                                         dclk_lcdc0: dclk_lcdc0_mux {
1411                                                 compatible = "rockchip,rk3188-mux-con";
1412                                                 rockchip,bits = <0 2>;
1413                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1414                                                 clock-output-names = "dclk_lcdc0";
1415                                                 #clock-cells = <0>;
1416                                         };
1417
1418                                         /* reg[7:2]: reserved */
1419
1420                                         dclk_lcdc0_div: dclk_lcdc0_div {
1421                                                 compatible = "rockchip,rk3188-div-con";
1422                                                 rockchip,bits = <8 8>;
1423                                                 clocks = <&dclk_lcdc0>;
1424                                                 clock-output-names = "dclk_lcdc0";
1425                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1426                                                 #clock-cells = <0>;
1427                                                 rockchip,clkops-idx =
1428                                                         <CLKOPS_RATE_RK3288_DCLK_LCDC0>;
1429                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1430                                         };
1431                                 };
1432
1433                                 clk_sel_con28: sel-con@00d0 {
1434                                         compatible = "rockchip,rk3188-selcon";
1435                                         reg = <0x00d0 0x4>;
1436                                         #address-cells = <1>;
1437                                         #size-cells = <1>;
1438
1439                                         clk_edp_div: clk_edp_div {
1440                                                 compatible = "rockchip,rk3188-div-con";
1441                                                 rockchip,bits = <0 6>;
1442                                                 clocks = <&clk_edp>;
1443                                                 clock-output-names = "clk_edp";
1444                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1445                                                 #clock-cells = <0>;
1446                                                 rockchip,clkops-idx =
1447                                                         <CLKOPS_RATE_MUX_DIV>;
1448                                         };
1449
1450                                         clk_edp: clk_edp_mux {
1451                                                 compatible = "rockchip,rk3188-mux-con";
1452                                                 rockchip,bits = <6 2>;
1453                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
1454                                                 clock-output-names = "clk_edp";
1455                                                 #clock-cells = <0>;
1456                                                 #clock-init-cells = <1>;
1457                                         };
1458
1459                                         hclk_vio: hclk_vio_div {
1460                                                 compatible = "rockchip,rk3188-div-con";
1461                                                 rockchip,bits = <8 5>;
1462                                                 clocks = <&clk_gates15 11>;
1463                                                 clock-output-names = "hclk_vio";
1464                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1465                                                 #clock-cells = <0>;
1466                                                 #clock-init-cells = <1>;
1467                                         };
1468
1469                                         /* reg[14:13]: reserved */
1470
1471                                         clk_edp_24m: edp_24m_mux {
1472                                                 compatible = "rockchip,rk3188-mux-con";
1473                                                 rockchip,bits = <15 1>;
1474                                                 clocks = <&edp_24m_clkin>, <&xin24m>;
1475                                                 clock-output-names = "clk_edp_24m";
1476                                                 #clock-cells = <0>;
1477                                         };
1478                                 };
1479
1480                                 clk_sel_con29: sel-con@00d4 {
1481                                         compatible = "rockchip,rk3188-selcon";
1482                                         reg = <0x00d4 0x4>;
1483                                         #address-cells = <1>;
1484                                         #size-cells = <1>;
1485
1486                                         ehci1phy_480m: ehci1phy_480m_mux {
1487                                                 compatible = "rockchip,rk3188-mux-con";
1488                                                 rockchip,bits = <0 2>;
1489                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1490                                                 clock-output-names = "ehci1phy_480m";
1491                                                 #clock-cells = <0>;
1492                                         };
1493
1494                                         ehci1phy_12m: ehci1phy_12m_mux {
1495                                                 compatible = "rockchip,rk3188-mux-con";
1496                                                 rockchip,bits = <2 1>;
1497                                                 clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>;
1498                                                 clock-output-names = "ehci1phy_12m";
1499                                                 #clock-cells = <0>;
1500                                         };
1501
1502                                         clkin_isp: clkin_isp {
1503                                                 compatible = "rockchip,rk3188-mux-con";
1504                                                 rockchip,bits = <3 1>;
1505                                                 clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
1506                                                 clock-output-names = "clkin_isp";
1507                                                 #clock-cells = <0>;
1508                                         };
1509
1510                                         clkin_cif: clkin_cif {
1511                                                 compatible = "rockchip,rk3188-mux-con";
1512                                                 rockchip,bits = <4 1>;
1513                                                 clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
1514                                                 clock-output-names = "clkin_cif";
1515                                                 #clock-cells = <0>;
1516                                         };
1517
1518                                         /* reg[5]: reserved */
1519
1520                                         dclk_lcdc1: dclk_lcdc1_mux {
1521                                                 compatible = "rockchip,rk3188-mux-con";
1522                                                 rockchip,bits = <6 2>;
1523                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1524                                                 clock-output-names = "dclk_lcdc1";
1525                                                 #clock-cells = <0>;
1526                                         };
1527
1528                                         dclk_lcdc1_div: dclk_lcdc1_div {
1529                                                 compatible = "rockchip,rk3188-div-con";
1530                                                 rockchip,bits = <8 8>;
1531                                                 clocks = <&dclk_lcdc1>;
1532                                                 clock-output-names = "dclk_lcdc1";
1533                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1534                                                 #clock-cells = <0>;
1535                                                 rockchip,clkops-idx =
1536                                                         <CLKOPS_RATE_RK3288_DCLK_LCDC1>;
1537                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1538                                         };
1539                                 };
1540
1541                                 clk_sel_con30: sel-con@00d8 {
1542                                         compatible = "rockchip,rk3188-selcon";
1543                                         reg = <0x00d8 0x4>;
1544                                         #address-cells = <1>;
1545                                         #size-cells = <1>;
1546
1547                                         aclk_rga_div: aclk_rga_div {
1548                                                 compatible = "rockchip,rk3188-div-con";
1549                                                 rockchip,bits = <0 5>;
1550                                                 clocks = <&aclk_rga>;
1551                                                 clock-output-names = "aclk_rga";
1552                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1553                                                 #clock-cells = <0>;
1554                                                 rockchip,clkops-idx =
1555                                                         <CLKOPS_RATE_MUX_DIV>;
1556                                         };
1557
1558                                         /* reg[5]: reserved */
1559
1560                                         aclk_rga: aclk_rga_mux {
1561                                                 compatible = "rockchip,rk3188-mux-con";
1562                                                 rockchip,bits = <6 2>;
1563                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1564                                                 clock-output-names = "aclk_rga";
1565                                                 #clock-cells = <0>;
1566                                                 #clock-init-cells = <1>;
1567                                         };
1568
1569                                         clk_rga_div: clk_rga_div {
1570                                                 compatible = "rockchip,rk3188-div-con";
1571                                                 rockchip,bits = <8 5>;
1572                                                 clocks = <&clk_rga>;
1573                                                 clock-output-names = "clk_rga";
1574                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1575                                                 #clock-cells = <0>;
1576                                                 rockchip,clkops-idx =
1577                                                         <CLKOPS_RATE_MUX_DIV>;
1578                                         };
1579
1580                                         /* reg[13]: reserved */
1581
1582                                         clk_rga: clk_rga_mux {
1583                                                 compatible = "rockchip,rk3188-mux-con";
1584                                                 rockchip,bits = <14 2>;
1585                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1586                                                 clock-output-names = "clk_rga";
1587                                                 #clock-cells = <0>;
1588                                                 #clock-init-cells = <1>;
1589                                         };
1590                                 };
1591
1592                                 clk_sel_con31: sel-con@00dc {
1593                                         compatible = "rockchip,rk3188-selcon";
1594                                         reg = <0x00dc 0x4>;
1595                                         #address-cells = <1>;
1596                                         #size-cells = <1>;
1597
1598                                         aclk_vio0_div: aclk_vio0_div {
1599                                                 compatible = "rockchip,rk3188-div-con";
1600                                                 rockchip,bits = <0 5>;
1601                                                 clocks = <&aclk_vio0>;
1602                                                 clock-output-names = "aclk_vio0";
1603                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1604                                                 #clock-cells = <0>;
1605                                                 rockchip,clkops-idx =
1606                                                         <CLKOPS_RATE_MUX_DIV>;
1607                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1608                                         };
1609
1610                                         /* reg[5]: reserved */
1611
1612                                         aclk_vio0: aclk_vio0_mux {
1613                                                 compatible = "rockchip,rk3188-mux-con";
1614                                                 rockchip,bits = <6 2>;
1615                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1616                                                 clock-output-names = "aclk_vio0";
1617                                                 #clock-cells = <0>;
1618                                                 #clock-init-cells = <1>;
1619                                         };
1620
1621                                         aclk_vio1_div: aclk_vio1_div {
1622                                                 compatible = "rockchip,rk3188-div-con";
1623                                                 rockchip,bits = <8 5>;
1624                                                 clocks = <&aclk_vio1>;
1625                                                 clock-output-names = "aclk_vio1";
1626                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1627                                                 #clock-cells = <0>;
1628                                                 rockchip,clkops-idx =
1629                                                         <CLKOPS_RATE_MUX_DIV>;
1630                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1631                                         };
1632
1633                                         /* reg[13]: reserved */
1634
1635                                         aclk_vio1: aclk_vio1_mux {
1636                                                 compatible = "rockchip,rk3188-mux-con";
1637                                                 rockchip,bits = <14 2>;
1638                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1639                                                 clock-output-names = "aclk_vio1";
1640                                                 #clock-cells = <0>;
1641                                                 #clock-init-cells = <1>;
1642                                         };
1643                                 };
1644
1645                                 clk_sel_con32: sel-con@00e0 {
1646                                         compatible = "rockchip,rk3188-selcon";
1647                                         reg = <0x00e0 0x4>;
1648                                         #address-cells = <1>;
1649                                         #size-cells = <1>;
1650
1651                                         clk_vepu_div: clk_vepu_div {
1652                                                 compatible = "rockchip,rk3188-div-con";
1653                                                 rockchip,bits = <0 5>;
1654                                                 clocks = <&clk_vepu>;
1655                                                 clock-output-names = "clk_vepu";
1656                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1657                                                 #clock-cells = <0>;
1658                                                 rockchip,clkops-idx =
1659                                                         <CLKOPS_RATE_MUX_DIV>;
1660                                         };
1661
1662                                         /* reg[5]: reserved */
1663
1664                                         clk_vepu: clk_vepu_mux {
1665                                                 compatible = "rockchip,rk3188-mux-con";
1666                                                 rockchip,bits = <6 2>;
1667                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1668                                                 clock-output-names = "clk_vepu";
1669                                                 #clock-cells = <0>;
1670                                                 #clock-init-cells = <1>;
1671                                         };
1672
1673                                         clk_vdpu_div: clk_vdpu_div {
1674                                                 compatible = "rockchip,rk3188-div-con";
1675                                                 rockchip,bits = <8 5>;
1676                                                 clocks = <&clk_vdpu>;
1677                                                 clock-output-names = "clk_vdpu";
1678                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1679                                                 #clock-cells = <0>;
1680                                                 rockchip,clkops-idx =
1681                                                         <CLKOPS_RATE_MUX_DIV>;
1682                                         };
1683
1684                                         /* reg[13]: reserved */
1685
1686                                         clk_vdpu: clk_vdpu_mux {
1687                                                 compatible = "rockchip,rk3188-mux-con";
1688                                                 rockchip,bits = <14 2>;
1689                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1690                                                 clock-output-names = "clk_vdpu";
1691                                                 #clock-cells = <0>;
1692                                                 #clock-init-cells = <1>;
1693                                         };
1694                                 };
1695
1696                                 clk_sel_con33: sel-con@00e4 {
1697                                         compatible = "rockchip,rk3188-selcon";
1698                                         reg = <0x00e4 0x4>;
1699                                         #address-cells = <1>;
1700                                         #size-cells = <1>;
1701
1702                                         pclk_pd_pmu: pclk_pd_pmu_div {
1703                                                 compatible = "rockchip,rk3188-div-con";
1704                                                 rockchip,bits = <0 5>;
1705                                                 clocks = <&clk_gpll>;
1706                                                 clock-output-names = "pclk_pd_pmu";
1707                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1708                                                 #clock-cells = <0>;
1709                                                 #clock-init-cells = <1>;
1710                                         };
1711
1712                                         /* reg[7:5]: reserved */
1713
1714                                         pclk_pd_alive: pclk_pd_alive {
1715                                                 compatible = "rockchip,rk3188-div-con";
1716                                                 rockchip,bits = <8 5>;
1717                                                 clocks = <&clk_gpll>;
1718                                                 clock-output-names = "pclk_pd_alive";
1719                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1720                                                 #clock-cells = <0>;
1721                                                 #clock-init-cells = <1>;
1722                                         };
1723
1724                                         /* reg[15:13]: reserved */
1725                                 };
1726
1727                                 clk_sel_con34: sel-con@00e8 {
1728                                         compatible = "rockchip,rk3188-selcon";
1729                                         reg = <0x00e8 0x4>;
1730                                         #address-cells = <1>;
1731                                         #size-cells = <1>;
1732
1733                                         clk_gpu_div: clk_gpu_div {
1734                                                 compatible = "rockchip,rk3188-div-con";
1735                                                 rockchip,bits = <0 5>;
1736                                                 clocks = <&clk_gpu>;
1737                                                 clock-output-names = "clk_gpu";
1738                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1739                                                 #clock-cells = <0>;
1740                                                 rockchip,clkops-idx =
1741                                                         <CLKOPS_RATE_MUX_DIV>;
1742                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1743                                         };
1744
1745                                         /* reg[5]: reserved */
1746
1747                                         clk_gpu: clk_gpu_mux {
1748                                                 compatible = "rockchip,rk3188-mux-con";
1749                                                 rockchip,bits = <6 2>;
1750                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
1751                                                 clock-output-names = "clk_gpu";
1752                                                 #clock-cells = <0>;
1753                                                 #clock-init-cells = <1>;
1754                                         };
1755
1756                                         clk_sdio1_div: clk_sdio1_div {
1757                                                 compatible = "rockchip,rk3188-div-con";
1758                                                 rockchip,bits = <8 6>;
1759                                                 clocks = <&clk_sdio1>;
1760                                                 clock-output-names = "clk_sdio1";
1761                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1762                                                 #clock-cells = <0>;
1763                                                 rockchip,clkops-idx =
1764                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1765                                         };
1766
1767                                         clk_sdio1: clk_sdio1_mux {
1768                                                 compatible = "rockchip,rk3188-mux-con";
1769                                                 rockchip,bits = <14 2>;
1770                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
1771                                                 clock-output-names = "clk_sdio1";
1772                                                 #clock-cells = <0>;
1773                                         };
1774                                 };
1775
1776                                 clk_sel_con35: sel-con@00ec {
1777                                         compatible = "rockchip,rk3188-selcon";
1778                                         reg = <0x00ec 0x4>;
1779                                         #address-cells = <1>;
1780                                         #size-cells = <1>;
1781
1782                                         clk_tsp_div: clk_tsp_div {
1783                                                 compatible = "rockchip,rk3188-div-con";
1784                                                 rockchip,bits = <0 5>;
1785                                                 clocks = <&clk_tsp>;
1786                                                 clock-output-names = "clk_tsp";
1787                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1788                                                 #clock-cells = <0>;
1789                                                 rockchip,clkops-idx =
1790                                                         <CLKOPS_RATE_MUX_DIV>;
1791                                         };
1792
1793                                         /* reg[5]: reserved */
1794
1795                                         clk_tsp: clk_tsp_mux {
1796                                                 compatible = "rockchip,rk3188-mux-con";
1797                                                 rockchip,bits = <6 2>;
1798                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
1799                                                 clock-output-names = "clk_tsp";
1800                                                 #clock-cells = <0>;
1801                                                 #clock-init-cells = <1>;
1802                                         };
1803
1804                                         clk_tspout_div: clk_tspout_div {
1805                                                 compatible = "rockchip,rk3188-div-con";
1806                                                 rockchip,bits = <8 5>;
1807                                                 clocks = <&clk_tspout>;
1808                                                 clock-output-names = "clk_tspout";
1809                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1810                                                 #clock-cells = <0>;
1811                                                 rockchip,clkops-idx =
1812                                                         <CLKOPS_RATE_MUX_DIV>;
1813                                         };
1814
1815                                         /* reg[13]: reserved */
1816
1817                                         clk_tspout: clk_tspout_mux {
1818                                                 compatible = "rockchip,rk3188-mux-con";
1819                                                 rockchip,bits = <14 2>;
1820                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
1821                                                 clock-output-names = "clk_tspout";
1822                                                 #clock-cells = <0>;
1823                                                 #clock-init-cells = <1>;
1824                                         };
1825                                 };
1826
1827                                 clk_sel_con36: sel-con@00f0 {
1828                                         compatible = "rockchip,rk3188-selcon";
1829                                         reg = <0x00f0 0x4>;
1830                                         #address-cells = <1>;
1831                                         #size-cells = <1>;
1832
1833                                         clk_core0: clk_core0_div {
1834                                                 compatible = "rockchip,rk3188-div-con";
1835                                                 rockchip,bits = <0 3>;
1836                                                 clocks = <&clk_core>;
1837                                                 clock-output-names = "clk_core0";
1838                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1839                                                 #clock-cells = <0>;
1840                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1841                                         };
1842
1843                                         /* reg[3]: reserved */
1844
1845                                         clk_core1: clk_core1_div {
1846                                                 compatible = "rockchip,rk3188-div-con";
1847                                                 rockchip,bits = <4 3>;
1848                                                 clocks = <&clk_core>;
1849                                                 clock-output-names = "clk_core1";
1850                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1851                                                 #clock-cells = <0>;
1852                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1853                                         };
1854
1855                                         /* reg[7]: reserved */
1856
1857                                         clk_core2: clk_core2_div {
1858                                                 compatible = "rockchip,rk3188-div-con";
1859                                                 rockchip,bits = <8 3>;
1860                                                 clocks = <&clk_core>;
1861                                                 clock-output-names = "clk_core2";
1862                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1863                                                 #clock-cells = <0>;
1864                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1865                                         };
1866
1867                                         /* reg[11]: reserved */
1868
1869                                         clk_core3: clk_core3_div {
1870                                                 compatible = "rockchip,rk3188-div-con";
1871                                                 rockchip,bits = <12 3>;
1872                                                 clocks = <&clk_core>;
1873                                                 clock-output-names = "clk_core3";
1874                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1875                                                 #clock-cells = <0>;
1876                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1877                                         };
1878
1879                                         /* reg[15]: reserved */
1880                                 };
1881
1882                                 clk_sel_con37: sel-con@00f4 {
1883                                         compatible = "rockchip,rk3188-selcon";
1884                                         reg = <0x00f4 0x4>;
1885                                         #address-cells = <1>;
1886                                         #size-cells = <1>;
1887
1888                                         clk_l2ram: clk_l2ram_div {
1889                                                 compatible = "rockchip,rk3188-div-con";
1890                                                 rockchip,bits = <0 3>;
1891                                                 clocks = <&clk_core>;
1892                                                 clock-output-names = "clk_l2ram";
1893                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1894                                                 #clock-cells = <0>;
1895                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1896                                         };
1897
1898                                         /* reg[3]: reserved */
1899
1900                                         atclk_core: atclk_core_div {
1901                                                 compatible = "rockchip,rk3188-div-con";
1902                                                 rockchip,bits = <4 5>;
1903                                                 clocks = <&clk_core>;
1904                                                 clock-output-names = "atclk_core";
1905                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1906                                                 #clock-cells = <0>;
1907                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1908                                         };
1909
1910                                         pclk_dbg_src: pclk_core_dbg_div {
1911                                                 compatible = "rockchip,rk3188-div-con";
1912                                                 rockchip,bits = <9 5>;
1913                                                 clocks = <&clk_core>;
1914                                                 clock-output-names = "pclk_dbg_src";
1915                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1916                                                 #clock-cells = <0>;
1917                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1918                                         };
1919
1920                                         /* reg[15:14]: reserved */
1921                                 };
1922
1923                                 clk_sel_con38: sel-con@00f8 {
1924                                         compatible = "rockchip,rk3188-selcon";
1925                                         reg = <0x00f8 0x4>;
1926                                         #address-cells = <1>;
1927                                         #size-cells = <1>;
1928
1929                                         clk_nandc0_div: clk_nandc0_div {
1930                                                 compatible = "rockchip,rk3188-div-con";
1931                                                 rockchip,bits = <0 5>;
1932                                                 clocks = <&clk_nandc0>;
1933                                                 clock-output-names = "clk_nandc0";
1934                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1935                                                 #clock-cells = <0>;
1936                                                 rockchip,clkops-idx =
1937                                                         <CLKOPS_RATE_MUX_DIV>;
1938                                         };
1939
1940                                         /* reg[6:5]: reserved */
1941
1942                                         clk_nandc0: clk_nandc0_mux {
1943                                                 compatible = "rockchip,rk3188-mux-con";
1944                                                 rockchip,bits = <7 1>;
1945                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
1946                                                 clock-output-names = "clk_nandc0";
1947                                                 #clock-cells = <0>;
1948                                         };
1949
1950                                         clk_nandc1_div: clk_nandc1_div {
1951                                                 compatible = "rockchip,rk3188-div-con";
1952                                                 rockchip,bits = <8 5>;
1953                                                 clocks = <&clk_nandc1>;
1954                                                 clock-output-names = "clk_nandc1";
1955                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1956                                                 #clock-cells = <0>;
1957                                                 rockchip,clkops-idx =
1958                                                         <CLKOPS_RATE_MUX_DIV>;
1959                                         };
1960
1961                                         /* reg[14:13]: reserved */
1962
1963                                         clk_nandc1: clk_nandc1_mux {
1964                                                 compatible = "rockchip,rk3188-mux-con";
1965                                                 rockchip,bits = <15 1>;
1966                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
1967                                                 clock-output-names = "clk_nandc1";
1968                                                 #clock-cells = <0>;
1969                                         };
1970                                 };
1971
1972                                 clk_sel_con39: sel-con@00fc {
1973                                         compatible = "rockchip,rk3188-selcon";
1974                                         reg = <0x00fc 0x4>;
1975                                         #address-cells = <1>;
1976                                         #size-cells = <1>;
1977
1978                                         clk_spi2_div: clk_spi2_div {
1979                                                 compatible = "rockchip,rk3188-div-con";
1980                                                 rockchip,bits = <0 7>;
1981                                                 clocks = <&clk_spi2>;
1982                                                 clock-output-names = "clk_spi2";
1983                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1984                                                 #clock-cells = <0>;
1985                                                 rockchip,clkops-idx =
1986                                                         <CLKOPS_RATE_MUX_DIV>;
1987                                         };
1988
1989                                         clk_spi2: clk_spi2_mux {
1990                                                 compatible = "rockchip,rk3188-mux-con";
1991                                                 rockchip,bits = <7 1>;
1992                                                 clocks = <&dummy_cpll>, <&clk_gpll>;
1993                                                 clock-output-names = "clk_spi2";
1994                                                 #clock-cells = <0>;
1995                                         };
1996
1997                                         aclk_hevc_div: aclk_hevc_div {
1998                                                 compatible = "rockchip,rk3188-div-con";
1999                                                 rockchip,bits = <8 5>;
2000                                                 clocks = <&aclk_hevc>;
2001                                                 clock-output-names = "aclk_hevc";
2002                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2003                                                 #clock-cells = <0>;
2004                                                 rockchip,clkops-idx =
2005                                                         <CLKOPS_RATE_MUX_DIV>;
2006                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
2007                                         };
2008
2009                                         /* reg[13]: reserved */
2010
2011                                         aclk_hevc: aclk_hevc_mux {
2012                                                 compatible = "rockchip,rk3188-mux-con";
2013                                                 rockchip,bits = <14 2>;
2014                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
2015                                                 clock-output-names = "aclk_hevc";
2016                                                 #clock-cells = <0>;
2017                                                 #clock-init-cells = <1>;
2018                                         };
2019                                 };
2020
2021                                 clk_sel_con40: sel-con@0100 {
2022                                         compatible = "rockchip,rk3188-selcon";
2023                                         reg = <0x0100 0x4>;
2024                                         #address-cells = <1>;
2025                                         #size-cells = <1>;
2026
2027                                         spdif_8ch_div: spdif_8ch_div {
2028                                                 compatible = "rockchip,rk3188-div-con";
2029                                                 rockchip,bits = <0 7>;
2030                                                 clocks = <&clk_spdif_pll>;
2031                                                 clock-output-names = "spdif_8ch_div";
2032                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2033                                                 #clock-cells = <0>;
2034                                         };
2035
2036                                         /* reg[7]: reserved */
2037
2038                                         clk_spdif_8ch: spdif_8ch_clk_mux {
2039                                                 compatible = "rockchip,rk3188-mux-con";
2040                                                 rockchip,bits = <8 2>;
2041                                                 clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
2042                                                 clock-output-names = "clk_spdif_8ch";
2043                                                 #clock-cells = <0>;
2044                                                 rockchip,clkops-idx =
2045                                                         <CLKOPS_RATE_RK3288_I2S>;
2046                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
2047                                         };
2048
2049                                         /* reg[11:10]: reserved */
2050
2051                                         hclk_hevc: hclk_hevc_div {
2052                                                 compatible = "rockchip,rk3188-div-con";
2053                                                 rockchip,bits = <12 2>;
2054                                                 clocks = <&aclk_hevc>;
2055                                                 clock-output-names = "hclk_hevc";
2056                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2057                                                 #clock-cells = <0>;
2058                                                 #clock-init-cells = <1>;
2059                                         };
2060
2061                                         /* reg[15:14]: reserved */
2062                                 };
2063
2064                                 clk_sel_con41: sel-con@0104 {
2065                                         compatible = "rockchip,rk3188-selcon";
2066                                         reg = <0x0104 0x4>;
2067                                         #address-cells = <1>;
2068                                         #size-cells = <1>;
2069
2070                                         spdif_8ch_frac: spdif_8ch_frac {
2071                                                 compatible = "rockchip,rk3188-frac-con";
2072                                                 clocks = <&spdif_8ch_div>;
2073                                                 clock-output-names = "spdif_8ch_frac";
2074                                                 /* numerator    denominator */
2075                                                 rockchip,bits = <0 32>;
2076                                                 rockchip,clkops-idx =
2077                                                         <CLKOPS_RATE_FRAC>;
2078                                                 #clock-cells = <0>;
2079                                         };
2080                                 };
2081
2082                                 clk_sel_con42: sel-con@0108 {
2083                                         compatible = "rockchip,rk3188-selcon";
2084                                         reg = <0x0108 0x4>;
2085                                         #address-cells = <1>;
2086                                         #size-cells = <1>;
2087
2088                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
2089                                                 compatible = "rockchip,rk3188-div-con";
2090                                                 rockchip,bits = <0 5>;
2091                                                 clocks = <&clk_hevc_cabac>;
2092                                                 clock-output-names = "clk_hevc_cabac";
2093                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2094                                                 #clock-cells = <0>;
2095                                                 rockchip,clkops-idx =
2096                                                         <CLKOPS_RATE_MUX_DIV>;
2097                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
2098                                         };
2099
2100                                         /* reg[5]: reserved */
2101
2102                                         clk_hevc_cabac: clk_hevc_cabac_mux {
2103                                                 compatible = "rockchip,rk3188-mux-con";
2104                                                 rockchip,bits = <6 2>;
2105                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
2106                                                 clock-output-names = "clk_hevc_cabac";
2107                                                 #clock-cells = <0>;
2108                                                 #clock-init-cells = <1>;
2109                                         };
2110
2111                                         clk_hevc_core_div: clk_hevc_core_div {
2112                                                 compatible = "rockchip,rk3188-div-con";
2113                                                 rockchip,bits = <8 5>;
2114                                                 clocks = <&clk_hevc_core>;
2115                                                 clock-output-names = "clk_hevc_core";
2116                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2117                                                 #clock-cells = <0>;
2118                                                 rockchip,clkops-idx =
2119                                                         <CLKOPS_RATE_MUX_DIV>;
2120                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
2121                                         };
2122
2123                                         /* reg[13]: reserved */
2124
2125                                         clk_hevc_core: clk_hevc_core_mux {
2126                                                 compatible = "rockchip,rk3188-mux-con";
2127                                                 rockchip,bits = <14 2>;
2128                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
2129                                                 clock-output-names = "clk_hevc_core";
2130                                                 #clock-cells = <0>;
2131                                                 #clock-init-cells = <1>;
2132                                         };
2133                                 };
2134
2135                         };
2136
2137
2138                         /* Gate control regs */
2139                         clk_gate_cons {
2140                                 compatible = "rockchip,rk-gate-cons";
2141                                 #address-cells = <1>;
2142                                 #size-cells = <1>;
2143                                 ranges ;
2144
2145                                 clk_gates0: gate-clk@0160 {
2146                                         compatible = "rockchip,rk3188-gate-clk";
2147                                         reg = <0x0160 0x4>;
2148                                         clocks =
2149                                                 <&dummy>,               <&clk_apll>,
2150                                                 <&clk_gpll>,    <&aclk_bus>,
2151
2152                                                 <&hclk_bus>,    <&pclk_bus>,
2153                                                 <&dummy>,               <&aclk_bus>,
2154
2155                                                 <&clk_dpll>,    <&clk_gpll>,
2156                                                 <&clk_gpll>,    <&clk_cpll>,
2157
2158                                                 <&xin24m>,              <&dummy>,
2159                                                 <&dummy>,               <&dummy>;
2160
2161                                         clock-output-names =
2162                                                 "reserved",                     "reserved",      /* do not use bit1 = "core_apll" */
2163                                                 "clk_arm_gpll",         "g_aclk_bus",
2164
2165                                                 "hclk_bus",             "pclk_bus",
2166                                                 "reserved",             "aclk_bus_2pmu",
2167
2168                                                 "reserved",             "reserved",             /*"clk_ddr_dpll",       "clk_ddr_gpll",*/
2169                                                 "reserved",             "reserved",             /*"clk_bus_gpll",       "clk_bus_cpll",*/
2170
2171                                                 "clk_acc_efuse",                "reserved",
2172                                                 "reserved",             "reserved";
2173                                         rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
2174
2175                                         #clock-cells = <1>;
2176                                 };
2177
2178                                 clk_gates1: gate-clk@0164 {
2179                                         compatible = "rockchip,rk3188-gate-clk";
2180                                         reg = <0x0164 0x4>;
2181                                         clocks =
2182                                                 <&xin24m>,              <&xin24m>,
2183                                                 <&xin24m>,              <&xin24m>,
2184
2185                                                 <&xin24m>,              <&xin24m>,
2186                                                 <&dummy>,               <&dummy>,
2187
2188                                                 <&clk_uart0_pll>,               <&uart0_frac>,
2189                                                 <&clk_uart1_div>,               <&uart1_frac>,
2190
2191                                                 <&clk_uart2_div>,               <&uart2_frac>,
2192                                                 <&clk_uart3_div>,               <&uart3_frac>;
2193
2194                                         clock-output-names =
2195                                                 "clk_timer0",           "clk_timer1",
2196                                                 "clk_timer2",           "clk_timer3",
2197
2198                                                 "clk_timer4",           "clk_timer5",
2199                                                 "reserved",                     "reserved",
2200
2201                                                 "clk_uart0_pll",        "uart0_frac",
2202                                                 "clk_uart1_div",        "uart1_frac",
2203
2204                                                 "clk_uart2_div",        "uart2_frac",
2205                                                 "clk_uart3_div",        "uart3_frac";
2206
2207                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
2208                                         #clock-cells = <1>;
2209                                 };
2210
2211                                 clk_gates2: gate-clk@0168 {
2212                                         compatible = "rockchip,rk3188-gate-clk";
2213                                         reg = <0x0168 0x4>;
2214                                         clocks =
2215                                                 <&aclk_peri>,           <&aclk_peri>,
2216                                                 <&hclk_peri>,           <&pclk_peri>,
2217
2218                                                 <&dummy>,               <&clk_mac_pll>,
2219                                                 <&clk_hsadc_pll>,               <&clk_tsadc>,
2220
2221                                                 <&clk_saradc>,          <&clk_spi0>,
2222                                                 <&clk_spi1>,            <&clk_spi2>,
2223
2224                                                 <&clk_uart4_div>,               <&uart4_frac>,
2225                                                 <&dummy>,               <&dummy>;
2226
2227                                         clock-output-names =
2228                                                 "aclk_peri",            "reserved", /*"g_aclk_periph",*/
2229                                                 "hclk_peri",            "pclk_peri",
2230
2231                                                 "reserved",             "clk_mac_pll",
2232                                                 "clk_hsadc_pll",                "clk_tsadc",
2233
2234                                                 "clk_saradc",           "clk_spi0",
2235                                                 "clk_spi1",             "clk_spi2",
2236
2237                                                 "clk_uart4_div",                "uart4_frac",
2238                                                 "reserved",             "reserved";
2239                                             rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
2240
2241                                         #clock-cells = <1>;
2242                                 };
2243
2244                                 clk_gates3: gate-clk@016c {
2245                                         compatible = "rockchip,rk3188-gate-clk";
2246                                         reg = <0x016c 0x4>;
2247                                         clocks =
2248                                                 <&aclk_vio0>,           <&dclk_lcdc0>,
2249                                                 <&aclk_vio1>,           <&dclk_lcdc1>,
2250
2251                                                 <&clk_rga>,                     <&aclk_rga>,
2252                                                 <&ehci1phy_480m>,               <&clk_cif_pll>,
2253
2254                                                 <&dummy>,               <&clk_vepu>,
2255                                                 <&dummy>,               <&clk_vdpu>,
2256
2257                                                 <&clk_edp_24m>,         <&clk_edp>,
2258                                                 <&clk_isp>,             <&clk_isp_jpe>;
2259
2260                                         clock-output-names =
2261                                                 "aclk_vio0",            "dclk_lcdc0",
2262                                                 "aclk_vio1",            "dclk_lcdc1",
2263
2264                                                 "clk_rga",              "aclk_rga",
2265                                                 "ehci1phy_480m",                "clk_cif_pll",
2266
2267                                                 /*Not use hclk_vpu_gate tmp, fixme*/
2268                                                 "reserved",             "clk_vepu",
2269                                                 "reserved",             "clk_vdpu",
2270
2271                                                 "clk_edp_24m",          "clk_edp",
2272                                                 "clk_isp",              "clk_isp_jpe";
2273                                                 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2274
2275                                         #clock-cells = <1>;
2276                                 };
2277
2278                                 clk_gates4: gate-clk@0170 {
2279                                         compatible = "rockchip,rk3188-gate-clk";
2280                                         reg = <0x0170 0x4>;
2281                                         clocks =
2282                                                 <&clk_i2s_out>,         <&clk_i2s_pll>,
2283                                                 <&i2s_frac>,            <&clk_i2s>,
2284
2285                                                 <&spdif_div>,           <&spdif_frac>,
2286                                                 <&clk_spdif>,           <&spdif_8ch_div>,
2287
2288                                                 <&spdif_8ch_frac>,              <&clk_spdif_8ch>,
2289                                                 <&clk_tsp>,             <&clk_tspout>,
2290
2291                                                 <&clk_ddr>,             <&clk_ddr>,
2292                                                 <&jtag_clkin>,          <&dummy>;
2293
2294                                         clock-output-names =
2295                                                 "clk_i2s_out",          "clk_i2s_pll",
2296                                                 "i2s_frac",             "clk_i2s",
2297
2298                                                 "spdif_div",            "spdif_frac",
2299                                                 "clk_spdif",            "spdif_8ch_div",
2300
2301                                                 "spdif_8ch_frac",               "clk_spdif_8ch",
2302                                                 "clk_tsp",              "clk_tspout",
2303
2304                                                 /* Not use these ddr gates */
2305                                                 "reserved",             "reserved",        /*"g_clk_ddrphy0",           "g_clk_ddrphy1",*/
2306                                                 "clk_jtag",             "reserved";             /*"testclk_gate_en";*/
2307
2308                                             rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
2309                                         #clock-cells = <1>;
2310                                 };
2311
2312                                 clk_gates5: gate-clk@0174 {
2313                                         compatible = "rockchip,rk3188-gate-clk";
2314                                         reg = <0x0174 0x4>;
2315                                         clocks =
2316                                                 <&clk_mac>,             <&clk_mac>,
2317                                                 <&clk_mac>,             <&clk_mac>,
2318
2319                                                 <&clk_crypto>,          <&clk_nandc0>,
2320                                                 <&clk_nandc1>,          <&clk_gpu>,
2321
2322                                                 <&pclk_pd_pmu>,         <&xin24m>,
2323                                                 <&xin24m>,              <&xin32k>,
2324
2325                                                 <&xin24m>,              <&xin24m>,
2326                                                 <&usbphy_480m>,         <&xin24m>;
2327
2328                                         clock-output-names =
2329                                                 "g_clk_mac_rx",         "g_clk_mac_tx",
2330                                                 "g_clk_mac_ref",        "g_mac_refout",
2331
2332                                                 "clk_crypto",           "clk_nandc0",
2333                                                 "clk_nandc1",           "clk_gpu",
2334
2335                                                 "pclk_pd_pmu",          "g_clk_pvtm_core",
2336                                                 "g_clk_pvtm_gpu",               "g_hdmi_cec_clk",
2337
2338                                                 "g_hdmi_hdcp_clk",              "g_ps2c_clk",
2339                                                 "usbphy_480m",          "g_mipidsi_24m";
2340                                                 rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
2341
2342                                         #clock-cells = <1>;
2343                                 };
2344
2345                                 clk_gates6: gate-clk@0178 {
2346                                         compatible = "rockchip,rk3188-gate-clk";
2347                                         reg = <0x0178 0x4>;
2348                                         clocks =
2349                                                 <&hclk_peri>,           <&pclk_peri>,
2350                                                 <&aclk_peri>,           <&aclk_peri>,
2351
2352                                                 <&pclk_peri>,           <&pclk_peri>,
2353                                                 <&pclk_peri>,           <&pclk_peri>,
2354
2355                                                 <&pclk_peri>,           <&pclk_peri>,
2356                                                 <&dummy>,                       <&pclk_peri>,
2357
2358                                                 <&pclk_peri>,           <&pclk_peri>,
2359                                                 <&pclk_peri>,           <&pclk_peri>;
2360
2361                                         clock-output-names =
2362                                                 "g_hp_matrix",          "g_pp_axi_matrix",
2363                                                 "g_ap_axi_matrix",              "g_aclk_dmac2",
2364
2365                                                 "g_pclk_spi0",          "g_pclk_spi1",
2366                                                 "g_pclk_spi2",          "g_pclk_ps2c",
2367
2368                                                 "g_pclk_uart0",         "g_pclk_uart1",
2369                                                 "reserved",             "g_pclk_uart3",
2370
2371                                                 "g_pclk_uart4",         "g_pclk_i2c1",
2372                                                 "g_pclk_i2c3",          "g_pclk_i2c4";
2373                                             rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
2374
2375                                         #clock-cells = <1>;
2376                                 };
2377
2378                                 clk_gates7: gate-clk@017c {
2379                                         compatible = "rockchip,rk3188-gate-clk";
2380                                         reg = <0x017c 0x4>;
2381                                         clocks =
2382                                                 <&pclk_peri>,           <&pclk_peri>,
2383                                                 <&pclk_peri>,           <&pclk_peri>,
2384
2385                                                 <&hclk_peri>,           <&hclk_peri>,
2386                                                 <&hclk_peri>,           <&hclk_peri>,
2387
2388                                                 <&hclk_peri>,           <&hclk_peri>,
2389                                                 <&hclk_peri>,           <&aclk_peri>,
2390
2391                                                 <&hclk_peri>,           <&hclk_peri>,
2392                                                 <&hclk_peri>,           <&hclk_peri>;
2393
2394                                         clock-output-names =
2395                                                 "g_pclk_i2c5",          "g_pclk_saradc",
2396                                                 "g_pclk_tsadc",         "g_pclk_sim",
2397
2398                                                 "g_hclk_otg0",          "g_pmu_hclk_otg0",
2399                                                 "g_hclk_host0",         "g_hclk_host1",
2400
2401                                                 "g_hclk_ehci1",         "g_hclk_usb_peri",
2402                                                 "g_hp_ahb_arbi",                "g_aclk_peri_niu",
2403
2404                                                 "g_h_emem_peri",                "g_hclk_mem_peri",
2405                                                 "g_hclk_nandc0",                "g_hclk_nandc1";
2406                                                 rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
2407
2408                                         #clock-cells = <1>;
2409                                 };
2410
2411                                 clk_gates8: gate-clk@0180 {
2412                                         compatible = "rockchip,rk3188-gate-clk";
2413                                         reg = <0x0180 0x4>;
2414                                         clocks =
2415                                                 <&aclk_peri>,           <&pclk_peri>,
2416                                                 <&aclk_peri>,           <&hclk_peri>,
2417
2418                                                 <&hclk_peri>,           <&hclk_peri>,
2419                                                 <&hclk_peri>,           <&hclk_peri>,
2420
2421                                                 <&hclk_peri>,           <&hsadc_0_tsp>,
2422                                                 <&hsadc_1_tsp>,         <&io_27m_in>,
2423
2424                                                 <&aclk_peri>,           <&dummy>,
2425                                                 <&dummy>,               <&dummy>;
2426
2427                                         clock-output-names =
2428                                                 "g_aclk_gmac",          "g_pclk_gmac",
2429                                                 "g_hclk_gps",           "g_hclk_sdmmc",
2430
2431                                                 "g_hclk_sdio0",         "g_hclk_sdio1",
2432                                                 "g_hclk_emmc",          "g_hclk_hsadc",
2433
2434                                                 "g_hclk_tsp",           "g_hsadc_0_tsp",
2435                                                 "g_hsadc_1_tsp",                "g_clk_27m_tsp",
2436
2437                                                 "g_aclk_peri_mmu",              "reserved",
2438                                                 "reserved",             "reserved";
2439
2440                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2441                                         #clock-cells = <1>;
2442                                 };
2443
2444                                 clk_gates9: gate-clk@0184 {
2445                                         compatible = "rockchip,rk3188-gate-clk";
2446                                         reg = <0x0184 0x4>;
2447                                         clocks =
2448                                                 <&dummy>,               <&dummy>,
2449                                                 <&dummy>,               <&dummy>,
2450
2451                                                 <&dummy>,               <&dummy>,
2452                                                 <&dummy>,               <&dummy>,
2453
2454                                                 <&dummy>,               <&dummy>,
2455                                                 <&dummy>,               <&dummy>,
2456
2457                                                 <&dummy>,               <&dummy>,
2458                                                 <&dummy>,               <&dummy>;
2459
2460                                         clock-output-names =
2461                                                 "reserved",             "reserved",             /*"aclk_video_gate_en", "hclk_video_clock_en",*/
2462                                                 "reserved",             "reserved",
2463
2464                                                 "reserved",             "reserved",
2465                                                 "reserved",             "reserved",
2466
2467                                                 "reserved",             "reserved",
2468                                                 "reserved",             "reserved",
2469
2470                                                 "reserved",             "reserved",
2471                                                 "reserved",             "reserved";
2472                                     rockchip,suspend-clkgating-setting=<0x0 0x0>;
2473
2474                                         #clock-cells = <1>;
2475                                 };
2476
2477                                 clk_gates10: gate-clk@0188 {
2478                                         compatible = "rockchip,rk3188-gate-clk";
2479                                         reg = <0x0188 0x4>;
2480                                         clocks =
2481                                                 <&pclk_bus>,            <&pclk_bus>,
2482                                                 <&pclk_bus>,            <&pclk_bus>,
2483
2484                                                 <&aclk_bus>,            <&aclk_bus>,
2485                                                 <&aclk_bus>,            <&aclk_bus>,
2486
2487                                                 <&hclk_bus>,            <&hclk_bus>,
2488                                                 <&hclk_bus>,            <&hclk_bus>,
2489
2490                                                 <&aclk_bus>,            <&aclk_bus>,
2491                                                 <&pclk_bus>,            <&pclk_bus>;
2492
2493                                         clock-output-names =
2494                                                 "g_pclk_pwm",           "g_pclk_timer",
2495                                                 "g_pclk_i2c0",          "g_pclk_i2c2",
2496
2497                                                 "g_aclk_intmem",                "g_clk_intmem0",
2498                                                 "g_clk_intmem1",                "g_clk_intmem2",
2499
2500                                                 "g_hclk_i2s",           "g_hclk_rom",
2501                                                 "g_hclk_spdif",         "g_h_spdif_8ch",
2502
2503                                                 "g_aclk_dmac1",         "g_aclk_strc_sys",
2504                                                 "reserved",             "reserved";     /*"g_p_ddrupctl0",      "g_pclk_publ0";*/
2505
2506                                                 //rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>;          // use sram  mem no gating
2507                                                 rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>;       // pwm logic vol
2508
2509                                         #clock-cells = <1>;
2510                                 };
2511
2512                                 clk_gates11: gate-clk@018c {
2513                                         compatible = "rockchip,rk3188-gate-clk";
2514                                         reg = <0x018c 0x4>;
2515                                         clocks =
2516                                                 <&pclk_bus>,            <&pclk_bus>,
2517                                                 <&pclk_bus>,            <&pclk_bus>,
2518
2519                                                 <&dummy>,               <&dummy>,
2520                                                 <&aclk_bus>,            <&hclk_bus>,
2521
2522                                                 <&aclk_bus>,            <&pclk_bus>,
2523                                                 <&pclk_bus>,            <&pclk_bus>,
2524
2525                                                 <&dummy>,               <&dummy>,
2526                                                 <&dummy>,               <&dummy>;
2527
2528                                         clock-output-names =
2529                                                 "reserved",     "reserved",     /*"g_p_ddrupctl1",      "g_pclk_publ1",*/
2530                                                 "g_p_efuse_1024",       "g_pclk_tzpc",
2531
2532                                                 "reserved",             "reserved",             /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
2533                                                 "g_aclk_crypto",        "g_hclk_crypto",
2534
2535                                                 "g_aclk_ccp",   "g_pclk_uart2",
2536                                                 "g_p_efuse_256",        "g_pclk_rkpwm",
2537
2538                                                 "reserved",             "reserved",
2539                                                 "reserved",             "reserved";
2540                                                rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
2541
2542                                         #clock-cells = <1>;
2543                                 };
2544
2545                                 clk_gates12: gate-clk@0190 {
2546                                         compatible = "rockchip,rk3188-gate-clk";
2547                                         reg = <0x0190 0x4>;
2548                                         clocks =
2549                                                 <&clk_core0>,           <&clk_core1>,
2550                                                 <&clk_core2>,           <&clk_core3>,
2551
2552                                                 <&clk_l2ram>,           <&aclk_core_m0>,
2553                                                 <&aclk_core_mp>,                <&atclk_core>,
2554
2555                                                 <&pclk_dbg_src>,                <&pclk_dbg_src>,
2556                                                 <&pclk_dbg_src>,                <&pclk_dbg_src>,
2557
2558                                                 <&dummy>,               <&dummy>,
2559                                                 <&dummy>,               <&dummy>;
2560
2561                                         clock-output-names =
2562                                                 "clk_core0",            "clk_core1",
2563                                                 "clk_core2",            "clk_core3",
2564
2565                                                 "clk_l2ram",            "aclk_core_m0",
2566                                                 "aclk_core_mp",         "atclk_core",
2567
2568                                                 "pclk_dbg_src",         "g_dbg_core_clk",
2569                                                 "g_cs_dbg_clk",         "g_pclk_core_niu",
2570
2571                                                 "reserved",             "reserved",
2572                                                 "reserved",             "reserved";
2573                                             rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
2574
2575                                         #clock-cells = <1>;
2576                                 };
2577
2578                                 clk_gates13: gate-clk@0194 {
2579                                         compatible = "rockchip,rk3188-gate-clk";
2580                                         reg = <0x0194 0x4>;
2581                                         clocks =
2582                                                 <&clk_sdmmc>,           <&clk_sdio0>,
2583                                                 <&clk_sdio1>,           <&clk_emmc>,
2584
2585                                                 <&xin24m>,              <&xin24m>,
2586                                                 <&xin24m>,              <&xin32k>,
2587
2588                                                 <&aclk_bus_src>,                <&xin12m>,
2589                                                 <&xin24m>,              <&xin24m>,
2590
2591                                                 <&dummy>,               <&aclk_hevc>,
2592                                                 <&clk_hevc_cabac>,              <&clk_hevc_core>;
2593
2594                                         clock-output-names =
2595                                                 "clk_sdmmc",            "clk_sdio0",
2596                                                 "clk_sdio1",            "clk_emmc",
2597
2598                                                 "clk_otgphy0",          "clk_otgphy1",
2599                                                 "clk_otgphy2",          "clk_otg_adp",
2600
2601                                                 "g_clk_c2c_host",               "g_clk_ehci1_12m",
2602                                                 "g_clk_lcdc_pwm0",              "g_clk_lcdc_pwm1",
2603
2604                                                 "g_clk_wifi",           "aclk_hevc",
2605                                                 "clk_hevc_cabac",               "clk_hevc_core";
2606                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2607
2608                                         #clock-cells = <1>;
2609                                 };
2610
2611                                 clk_gates14: gate-clk@0198 {
2612                                         compatible = "rockchip,rk3188-gate-clk";
2613                                         reg = <0x0198 0x4>;
2614                                         clocks =
2615                                                 <&dummy>,               <&pclk_pd_alive>,
2616                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2617
2618                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2619                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2620
2621                                                 <&pclk_pd_alive>,               <&dummy>,
2622                                                 <&dummy>,               <&pclk_pd_alive>,
2623
2624                                                 <&pclk_pd_alive>,               <&dummy>,
2625                                                 <&dummy>,               <&dummy>;
2626
2627                                         clock-output-names =
2628                                                 "reserved",             "g_pclk_gpio1",
2629                                                 "g_pclk_gpio2",         "g_pclk_gpio3",
2630
2631                                                 "g_pclk_gpio4",         "g_pclk_gpio5",
2632                                                 "g_pclk_gpio6",         "g_pclk_gpio7",
2633
2634                                                 "g_pclk_gpio8",         "reserved",
2635                                                 "reserved",             "g_pclk_grf",
2636
2637                                                 "g_p_alive_niu",                "reserved",
2638                                                 "reserved",             "reserved";
2639                                                 //rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
2640
2641                                                 rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
2642
2643                                         #clock-cells = <1>;
2644                                 };
2645
2646                                 clk_gates15: gate-clk@019c {
2647                                         compatible = "rockchip,rk3188-gate-clk";
2648                                         reg = <0x019c 0x4>;
2649                                         clocks =
2650                                                 <&aclk_rga>,            <&hclk_vio>,
2651                                                 <&clk_gates15 11>,      <&hclk_vio>,
2652
2653                                                 <&dummy>,               <&clk_gates15 11>,
2654                                                 <&hclk_vio>,            <&clk_gates15 12>,
2655
2656                                                 <&hclk_vio>,            <&dummy>,
2657                                                 <&dummy>,               <&aclk_vio0>,
2658
2659                                                 <&aclk_vio1>,           <&aclk_rga>,
2660                                                 <&clk_gates15 11>,      <&hclk_vio>;
2661
2662                                         clock-output-names =
2663                                                 "reserved", /*"g_aclk_rga"*/    "g_hclk_rga",
2664                                                 "g_aclk_iep",           "g_hclk_iep",
2665
2666                                                 "g_aclk_lcdc_iep",              "g_aclk_lcdc0",
2667                                                 "g_hclk_lcdc0",         "g_aclk_lcdc1",
2668
2669                                                 "g_hclk_lcdc1",         "reserved", /* "g_h_vio_ahb" */
2670                                                 "reserved",/*"g_hclk_vio_niu"*/         "g_aclk_vio0_niu",
2671
2672                                                 "g_aclk_vio1_niu",              "reserved",/*"g_aclk_rga_niu"*/
2673                                                 "g_aclk_vip",           "g_hclk_vip";
2674                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2675
2676                                         #clock-cells = <1>;
2677                                 };
2678
2679                                 clk_gates16: gate-clk@01a0 {
2680                                         compatible = "rockchip,rk3188-gate-clk";
2681                                         reg = <0x01a0 0x4>;
2682                                         clocks =
2683                                                 <&pclkin_cif>,          <&hclk_vio>,
2684                                                 <&clk_gates15 12>,      <&pclkin_isp>,
2685
2686                                                 <&hclk_vio>,            <&hclk_vio>,
2687                                                 <&hclk_vio>,            <&hclk_vio>,
2688
2689                                                 <&hclk_vio>,            <&hclk_vio>,
2690                                                 <&dummy>,               <&dummy>,
2691
2692                                                 <&dummy>,               <&dummy>,
2693                                                 <&dummy>,               <&dummy>;
2694
2695                                         clock-output-names =
2696                                                 "g_pclkin_cif",         "g_hclk_isp",
2697                                                 "g_aclk_isp",           "g_pclkin_isp",
2698
2699                                                 "g_p_mipi_dsi0",                "g_p_mipi_dsi1",
2700                                                 "g_p_mipi_csi",         "g_pclk_lvds_phy",
2701
2702                                                 "g_pclk_edp_ctrl",              "g_p_hdmi_ctrl",
2703                                                 "reserved",             "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
2704
2705                                                 "reserved",             "reserved",
2706                                                 "reserved",             "reserved";
2707                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
2708
2709                                         #clock-cells = <1>;
2710                                 };
2711
2712                                 clk_gates17: gate-clk@01a4 {
2713                                         compatible = "rockchip,rk3188-gate-clk";
2714                                         reg = <0x01a4 0x4>;
2715                                         clocks =
2716                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2717                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2718
2719                                                 <&pclk_pd_pmu>,         <&dummy>,
2720                                                 <&dummy>,               <&dummy>,
2721
2722                                                 <&dummy>,               <&dummy>,
2723                                                 <&dummy>,               <&dummy>,
2724
2725                                                 <&dummy>,               <&dummy>,
2726                                                 <&dummy>,               <&dummy>;
2727
2728                                         clock-output-names =
2729                                                 "g_pclk_pmu",           "g_pclk_intmem1",
2730                                                 "g_pclk_pmu_niu",               "g_pclk_sgrf",
2731
2732                                                 "g_pclk_gpio0",         "reserved",
2733                                                 "reserved",             "reserved",
2734
2735                                                 "reserved",             "reserved",
2736                                                 "reserved",             "reserved",
2737
2738                                                 "reserved",             "reserved",
2739                                                 "reserved",             "reserved";
2740                                              rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
2741
2742                                         #clock-cells = <1>;
2743                                 };
2744
2745                                 clk_gates18: gate-clk@01a8 {
2746                                         compatible = "rockchip,rk3188-gate-clk";
2747                                         reg = <0x01a8 0x4>;
2748                                         clocks =
2749                                                 <&clk_gpu>,             <&dummy>,
2750                                                 <&dummy>,               <&dummy>,
2751
2752                                                 <&dummy>,               <&dummy>,
2753                                                 <&dummy>,               <&dummy>,
2754
2755                                                 <&dummy>,               <&dummy>,
2756                                                 <&dummy>,               <&dummy>,
2757
2758                                                 <&dummy>,               <&dummy>,
2759                                                 <&dummy>,               <&dummy>;
2760
2761                                         clock-output-names =
2762                                                 "reserved", /*"g_aclk_gpu",*/   "reserved",
2763                                                 "reserved",             "reserved",
2764
2765                                                 "reserved",             "reserved",
2766                                                 "reserved",             "reserved",
2767
2768                                                 "reserved",             "reserved",
2769                                                 "reserved",             "reserved",
2770
2771                                                 "reserved",             "reserved",
2772                                                 "reserved",             "reserved";
2773
2774                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
2775                                         #clock-cells = <1>;
2776                                 };
2777
2778                         };
2779                 };
2780         };
2781 };