oota-llvm.git
11 years agoSectionMemoryManager shouldn't be a JITMemoryManager. Previously, the
Filip Pizlo [Tue, 14 May 2013 19:29:00 +0000 (19:29 +0000)]
SectionMemoryManager shouldn't be a JITMemoryManager. Previously, the
EngineBuilder interface required a JITMemoryManager even if it was being used
to construct an MCJIT. But the MCJIT actually wants a RTDyldMemoryManager.
Consequently, the SectionMemoryManager, which is meant for MCJIT, derived
from the JITMemoryManager and then stubbed out a bunch of JITMemoryManager
methods that weren't relevant to the MCJIT.

This patch fixes the situation: it teaches the EngineBuilder that
RTDyldMemoryManager is a supertype of JITMemoryManager, and that it's
appropriate to pass a RTDyldMemoryManager instead of a JITMemoryManager if
we're using the MCJIT. This allows us to remove the stub methods from
SectionMemoryManager, and make SectionMemoryManager a direct subtype of
RTDyldMemoryManager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181820 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Pass to replace tranfer/copy instructions into combine instruction
Jyotsna Verma [Tue, 14 May 2013 18:54:06 +0000 (18:54 +0000)]
Hexagon: Pass to replace tranfer/copy instructions into combine instruction
where possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReapply "Subtract isn't commutative, fix this for MMX psub." with
Eric Christopher [Tue, 14 May 2013 18:33:40 +0000 (18:33 +0000)]
Reapply "Subtract isn't commutative, fix this for MMX psub." with
a somewhat randomly chosen cpu that will minimize cpu specific
differences on bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181814 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTemporarily revert "Subtract isn't commutative, fix this for MMX psub."
Eric Christopher [Tue, 14 May 2013 18:20:42 +0000 (18:20 +0000)]
Temporarily revert "Subtract isn't commutative, fix this for MMX psub."

It's causing failures on the atom bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181812 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix __clear_cache declaration.
Rafael Espindola [Tue, 14 May 2013 18:06:14 +0000 (18:06 +0000)]
Fix __clear_cache declaration.

This fixes the build with gcc in gnu++98 and gnu++11 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181811 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSubtract isn't commutative, fix this for MMX psub.
Eric Christopher [Tue, 14 May 2013 17:52:05 +0000 (17:52 +0000)]
Subtract isn't commutative, fix this for MMX psub.

Patch by Andrea DiBiagio.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181809 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRecognize sparc64 as an alias for sparcv9 triples.
Jakob Stoklund Olesen [Tue, 14 May 2013 17:47:27 +0000 (17:47 +0000)]
Recognize sparc64 as an alias for sparcv9 triples.

Patch by Brad Smith!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181808 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Add patterns to generate 'combine' instructions.
Jyotsna Verma [Tue, 14 May 2013 17:16:38 +0000 (17:16 +0000)]
Hexagon: Add patterns to generate 'combine' instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: ArePredicatesComplement should not restrict itself to TFRs.
Jyotsna Verma [Tue, 14 May 2013 16:36:34 +0000 (16:36 +0000)]
Hexagon: ArePredicatesComplement should not restrict itself to TFRs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd bitcast to store of personality function.
Kai Nacke [Tue, 14 May 2013 16:30:51 +0000 (16:30 +0000)]
Add bitcast to store of personality function.

The personality function is user defined and may have an arbitrary result type.
The code assumes always i8*. This results in an assertion failure if a different
type is used. A bitcast to i8* is added to prevent this failure.

Reviewed by: Renato Golin, Bob Wilson

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181802 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix ARM FastISel tests, as a first step to enabling ARM FastISel
Derek Schuff [Tue, 14 May 2013 16:26:38 +0000 (16:26 +0000)]
Fix ARM FastISel tests, as a first step to enabling ARM FastISel

ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on
enabling it for other targets. As a first step I've fixed some of the tests.
Changes to ARM FastISel tests:
- Different triples don't generate the same relocations (especially
  movw/movt versus constant pool loads). Use a regex to allow either.
- Mangling is different. Use a regex to allow either.
- The reserved registers are sometimes different, so registers get
  allocated in a different order. Capture the names only where this
  occurs.
- Add -verify-machineinstrs to some tests where it works. It doesn't
  work everywhere it should yet.
- Add -fast-isel-abort to many tests that didn't have it before.
- Split out the VarArg test from fast-isel-call.ll into its own
  test. This simplifies test setup because of --check-prefix.

Patch by JF Bastien

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC32: Fix stack collision between FP and CR save areas.
Bill Schmidt [Tue, 14 May 2013 16:08:32 +0000 (16:08 +0000)]
PPC32: Fix stack collision between FP and CR save areas.

The changes to CR spill handling missed a case for 32-bit PowerPC.
The code in PPCFrameLowering::processFunctionBeforeFrameFinalized()
checks whether CR spill has occurred using a flag in the function
info.  This flag is only set by storeRegToStackSlot and
loadRegFromStackSlot.  spillCalleeSavedRegisters does not call
storeRegToStackSlot, but instead produces MI directly.  Thus we don't
see the CR is spilled when assigning frame offsets, and the CR spill
ends up colliding with some other location (generally the FP slot).

This patch sets the flag in spillCalleeSavedRegisters for PPC32 so
that the CR spill is properly detected and gets its own slot in the
stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181800 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Test case to check if branch probabilities are properly reflected in
Jyotsna Verma [Tue, 14 May 2013 15:50:49 +0000 (15:50 +0000)]
Hexagon: Test case to check if branch probabilities are properly reflected in
the jump instructions in the form of taken/not-taken hint.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181799 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Remove dead-code after unconditional return from addPreSched2.
Jyotsna Verma [Tue, 14 May 2013 15:33:27 +0000 (15:33 +0000)]
Hexagon: Remove dead-code after unconditional return from addPreSched2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Add processor type for Hainan asic
Tom Stellard [Tue, 14 May 2013 14:42:56 +0000 (14:42 +0000)]
R600/SI: Add processor type for Hainan asic

Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181792 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoGet the unittests compiling when building with cmake and the setting
Duncan Sands [Tue, 14 May 2013 13:29:16 +0000 (13:29 +0000)]
Get the unittests compiling when building with cmake and the setting
-DLLVM_ENABLE_THREADS=false.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181788 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDeclare __clear_cache.
Rafael Espindola [Tue, 14 May 2013 13:02:37 +0000 (13:02 +0000)]
Declare __clear_cache.

GCC declares __clear_cache in the gnu modes (-std=gnu++98,
-std=gnu++11), but not in the strict modes (-std=c++98, -std=c++11). This patch
declares it and therefore fixes the build when using one of the strict modes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181785 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Add disassembler support
Richard Sandiford [Tue, 14 May 2013 10:17:52 +0000 (10:17 +0000)]
[SystemZ] Add disassembler support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Add lit test coverage for the remaining patterns added recently
Michel Danzer [Tue, 14 May 2013 09:53:30 +0000 (09:53 +0000)]
R600/SI: Add lit test coverage for the remaining patterns added recently

Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181775 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Add extra testscases for r181773
Richard Sandiford [Tue, 14 May 2013 09:49:11 +0000 (09:49 +0000)]
[SystemZ] Add extra testscases for r181773

Forgot to svn add these...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181774 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Rework handling of constant PC-relative operands
Richard Sandiford [Tue, 14 May 2013 09:47:26 +0000 (09:47 +0000)]
[SystemZ] Rework handling of constant PC-relative operands

The GNU assembler treats things like:

        brasl   %r14, 100

in the same way as:

        brasl   %r14, .+100

rather than as a branch to absolute address 100.  We implemented this in
LLVM by creating an immediate operand rather than the usual expr operand,
and by handling immediate operands specially in the code emitter.
This was undesirable for (at least) three reasons:

- the specialness of immediate operands was exposed to the backend MC code,
  rather than being limited to the assembler parser.

- in disassembly, an immediate operand really is an absolute address.
  (Note that this means reassembling printed disassembly can't recreate
  the original code.)

- it would interfere with any assembly manipulation that we might
  try in future.  E.g. operations like branch shortening can change
  the relative position of instructions, but any code that updates
  sym+offset addresses wouldn't update an immediate "100" operand
  in the same way as an explicit ".+100" operand.

This patch changes the implementation so that the assembler creates
a "." label for immediate PC-relative operands, so that the operand
to the MCInst is always the absolute address.  The patch also adds
some error checking of the offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Remove bogus isAsmParserOnly
Richard Sandiford [Tue, 14 May 2013 09:38:07 +0000 (09:38 +0000)]
[SystemZ] Remove bogus isAsmParserOnly

Marking instructions as isAsmParserOnly stops them from being disassembled.
However, in cases where separate asm and codegen versions exist, we actually
want to disassemble to the asm ones.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181772 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Match operands to fields by name rather than by order
Richard Sandiford [Tue, 14 May 2013 09:36:44 +0000 (09:36 +0000)]
[SystemZ] Match operands to fields by name rather than by order

The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists.  This isn't desirable
for disassembly, where the two are matched only by name.  E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.

The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though.  The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field.  That's the approach taken in this patch.

Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181771 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Match operands to fields by name rather than by order
Richard Sandiford [Tue, 14 May 2013 09:28:21 +0000 (09:28 +0000)]
[SystemZ] Match operands to fields by name rather than by order

The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists.  This isn't desirable
for disassembly, where the two are matched only by name.  E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.

The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though.  The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field.  That's the approach taken in this patch.

Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemoved trailing whitespace.
Michael Gottesman [Tue, 14 May 2013 06:40:10 +0000 (06:40 +0000)]
Removed trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181760 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix typo.
Reed Kotler [Tue, 14 May 2013 06:00:01 +0000 (06:00 +0000)]
Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181759 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemoved an unnamed namespace and forgot to make two of the functions inside
Reed Kotler [Tue, 14 May 2013 02:13:45 +0000 (02:13 +0000)]
Removed an unnamed namespace and forgot to make two of the functions inside
"static".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoThis is the first of three patches which creates stubs used for
Reed Kotler [Tue, 14 May 2013 02:00:24 +0000 (02:00 +0000)]
This is the first of three patches which creates stubs used for
Mips16/32 floating point interoperability.

When Mips16 code calls external functions that would normally have some
of its parameters or return values passed in floating point registers,
it needs (Mips32) helper functions to do this because while in Mips16 mode
there is no ability to access the floating point registers.

In Pic mode, this is done with a set of predefined functions in libc.
This case is already handled in llvm for Mips16.

In static relocation mode, for efficiency reasons, the compiler generates
stubs that the linker will use if it turns out that the external function
is a Mips32 function. (If it's Mips16, then it does not need the helper
stubs).

These stubs are identically named and the linker knows about these tricks
and will not create multiple copies and will delete them if they are not
needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoStackColoring: don't clear an instruction's mem operand if the underlying
Akira Hatanaka [Tue, 14 May 2013 01:42:44 +0000 (01:42 +0000)]
StackColoring: don't clear an instruction's mem operand if the underlying
object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e.,
points to memory that has a constant value).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181751 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAssert that DIEEntries are constructed with non-null DIEs
David Blaikie [Tue, 14 May 2013 00:35:19 +0000 (00:35 +0000)]
Assert that DIEEntries are constructed with non-null DIEs

This just brings a crash a little further forward from DWARF emission to
DIE construction to make errors easier to diagnose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181748 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoLoopVectorize: Handle loops with multiple forward inductions
Arnold Schwaighofer [Tue, 14 May 2013 00:21:18 +0000 (00:21 +0000)]
LoopVectorize: Handle loops with multiple forward inductions

We used to give up if we saw two integer inductions. After this patch, we base
further induction variables on the chosen one like we do in the reverse
induction and pointer induction case.

Fixes PR15720.

radar://13851975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181746 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[objc-arc-opts] Added debug statements when we set and unset whether a pointer is...
Michael Gottesman [Tue, 14 May 2013 00:08:09 +0000 (00:08 +0000)]
[objc-arc-opts] Added debug statements when we set and unset whether a pointer is known positive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181745 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs if and...
Michael Gottesman [Mon, 13 May 2013 23:49:42 +0000 (23:49 +0000)]
[objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs if and only if we are both KnownSafeBU/KnownSafeTD rather than just either or.

In the presense of a block being initialized, the frontend will emit the
objc_retain on the original pointer and the release on the pointer loaded from
the alloca. The optimizer will through the provenance analysis realize that the
two are related (albiet different), but since we only require KnownSafe in one
direction, will match the inner retain on the original pointer with the guard
release on the original pointer. This is fixed by ensuring that in the presense
of allocas we only unconditionally remove pointers if both our retain and our
release are KnownSafe (i.e. we are KnownSafe in both directions) since we must
deal with the possibility that the frontend will emit what (to the optimizer)
appears to be unbalanced retain/releases.

An example of the miscompile is:

  %A = alloca
  retain(%x)
  retain(%x) <--- Inner Retain
  store %x, %A
  %y = load %A
  ... DO STUFF ...
  release(%y)
  call void @use(%x)
  release(%x) <--- Guarding Release

getting optimized to:

  %A = alloca
  retain(%x)
  store %x, %A
  %y = load %A
  ... DO STUFF ...
  release(%y)
  call void @use(%x)

rdar://13750319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181743 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMove a couple more statistics inside '#ifndef NDEBUG'.
Matt Beaumont-Gay [Mon, 13 May 2013 21:10:49 +0000 (21:10 +0000)]
Move a couple more statistics inside '#ifndef NDEBUG'.

Suppresses an unused-variable warning in -Asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181733 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMips assembler: Assembler macro ADDIU $rs,imm
Jack Carter [Mon, 13 May 2013 20:26:46 +0000 (20:26 +0000)]
Mips assembler: Assembler macro ADDIU $rs,imm

This patch adds alias for addiu instruction which enables following syntax:

    addiu $rs,imm

The macro is translated as:

    addiu $rs,$rs,imm

Contributer: Vladimir Medic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[objc-arc-opts] Add comment to BBState making it clear that get{TopDown,BottomUp...
Michael Gottesman [Mon, 13 May 2013 19:40:39 +0000 (19:40 +0000)]
[objc-arc-opts] Add comment to BBState making it clear that get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181726 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix goofy commentary in PPCTargetObjectFile.cpp.
Bill Schmidt [Mon, 13 May 2013 19:40:36 +0000 (19:40 +0000)]
Fix goofy commentary in PPCTargetObjectFile.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC64: Constant initializers with dynamic relocations go in .data.rel.ro.
Bill Schmidt [Mon, 13 May 2013 19:34:37 +0000 (19:34 +0000)]
PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.

This fixes warning messages observed in the oggenc application test in
projects/test-suite.  Special handling is needed for the 64-bit
PowerPC SVR4 ABI when a constant is initialized with a pointer to a
function in a shared library.  Because a function address is
implemented as the address of a function descriptor, the use of copy
relocations can lead to problems with initialization.  GNU ld
therefore replaces copy relocations with dynamic relocations to be
resolved by the dynamic linker.  This means the constant cannot reside
in the read-only data section, but instead belongs in .data.rel.ro,
which is designed for constants containing dynamic relocations.

The implementation creates a class PPC64LinuxTargetObjectFile
inheriting from TargetLoweringObjectFileELF, which behaves like its
parent except to place constants of this sort into .data.rel.ro.

The test case is reduced from the oggenc application.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove redundant variable introduced by r181682.
Bob Wilson [Mon, 13 May 2013 19:02:31 +0000 (19:02 +0000)]
Remove redundant variable introduced by r181682.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181721 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[objc-arc] Move the before optimization statistics gathering phase out of OptimizeInd...
Michael Gottesman [Mon, 13 May 2013 18:29:07 +0000 (18:29 +0000)]
[objc-arc] Move the before optimization statistics gathering phase out of OptimizeIndividualCalls.

This makes the statistics gathering completely independent of the actual
optimization occuring, preventing any sort of bleeding over from occuring.

Additionally, it simplifies a switch statement in the non-statistic gathering case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181719 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Add option -mno-ldc1-sdc1.
Akira Hatanaka [Mon, 13 May 2013 18:23:35 +0000 (18:23 +0000)]
[mips] Add option -mno-ldc1-sdc1.

This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * -14.5f +...
Shuxin Yang [Mon, 13 May 2013 18:03:12 +0000 (18:03 +0000)]
Fix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * -14.5f + 225.0f" to 225.0f.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181715 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Define a helper function which creates an instruction with the same
Akira Hatanaka [Mon, 13 May 2013 17:57:42 +0000 (17:57 +0000)]
[mips] Define a helper function which creates an instruction with the same
operands as the prototype instruction but with a different opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Rename functions. No functionality changes.
Akira Hatanaka [Mon, 13 May 2013 17:43:19 +0000 (17:43 +0000)]
[mips] Rename functions. No functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove unused fields and arguments.
Rafael Espindola [Mon, 13 May 2013 14:34:48 +0000 (14:34 +0000)]
Remove unused fields and arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoThe purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when...
Mihai Popa [Mon, 13 May 2013 14:10:04 +0000 (14:10 +0000)]
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCorrectly preserve the input chain for potential tailcall nodes whose
Lang Hames [Mon, 13 May 2013 10:21:19 +0000 (10:21 +0000)]
Correctly preserve the input chain for potential tailcall nodes whose
return values are bitcasts.

The chain had previously been being clobbered with the entry node to
the dag, which sometimes caused other code in the function to be
erroneously deleted when tailcall optimization kicked in.

<rdar://problem/13827621>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181696 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSuppress GCC compiler warnings in release builds about variables that are only
Duncan Sands [Mon, 13 May 2013 07:50:47 +0000 (07:50 +0000)]
Suppress GCC compiler warnings in release builds about variables that are only
read in asserts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSLPVectorizer: Swap LHS and RHS. No functionality change.
Nadav Rotem [Mon, 13 May 2013 05:13:13 +0000 (05:13 +0000)]
SLPVectorizer: Swap LHS and RHS. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181684 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix PR15950 A bug in DAG Combiner about undef mask
Hao Liu [Mon, 13 May 2013 02:07:05 +0000 (02:07 +0000)]
Fix PR15950 A bug in DAG Combiner about undef mask

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181682 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove the MachineMove class.
Rafael Espindola [Mon, 13 May 2013 01:16:13 +0000 (01:16 +0000)]
Remove the MachineMove class.

It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoXFAIL this test for mingw too.
Rafael Espindola [Mon, 13 May 2013 00:18:24 +0000 (00:18 +0000)]
XFAIL this test for mingw too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181678 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSLPVectorizer: Fix a bug in the code that generates extracts for values with multiple...
Nadav Rotem [Sun, 12 May 2013 22:58:45 +0000 (22:58 +0000)]
SLPVectorizer: Fix a bug in the code that generates extracts for values with multiple users.
The external user does not have to be in lane #0. We have to save the lane for each scalar so that we know which vector lane to extract.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181674 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSLPVectorizer: Clear the map that maps between scalars to vectors after each round...
Nadav Rotem [Sun, 12 May 2013 22:55:57 +0000 (22:55 +0000)]
SLPVectorizer: Clear the map that maps between scalars to vectors after each round of vectorization.
Testcase in the next commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181673 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoInstCombine: Flip the order of two urem transforms
David Majnemer [Sun, 12 May 2013 00:07:05 +0000 (00:07 +0000)]
InstCombine: Flip the order of two urem transforms

There are two transforms in visitUrem that conflict with each other.

*) One, if a divisor is a power of two, subtracts one from the divisor
   and turns it into a bitwise-and.
*) The other unwraps both operands if they are surrounded by zext
   instructions.

Flipping the order allows the subtraction to go beneath the sign
extension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181668 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoLoopVectorize: Use the widest induction variable type
Arnold Schwaighofer [Sat, 11 May 2013 23:04:28 +0000 (23:04 +0000)]
LoopVectorize: Use the widest induction variable type

Use the widest induction type encountered for the cannonical induction variable.

We used to turn the following loop into an empty loop because we used i8 as
induction variable type and truncated 1024 to 0 as trip count.

int a[1024];
void fail() {
  int reverse_induction = 1023;
  unsigned char forward_induction = 0;
  while ((reverse_induction) >= 0) {
    forward_induction++;
    a[reverse_induction] = forward_induction;
    --reverse_induction;
  }
}

radar://13862901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181667 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoLoopVectorize: Use variable instead of repeated function call
Arnold Schwaighofer [Sat, 11 May 2013 23:04:26 +0000 (23:04 +0000)]
LoopVectorize: Use variable instead of repeated function call

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181666 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoLoopVectorize: Use IRBuilder interface in more places
Arnold Schwaighofer [Sat, 11 May 2013 23:04:24 +0000 (23:04 +0000)]
LoopVectorize: Use IRBuilder interface in more places

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181665 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCorrect parameter name in doc comment to match declaration.
David Blaikie [Sat, 11 May 2013 19:14:10 +0000 (19:14 +0000)]
Correct parameter name in doc comment to match declaration.

(review feedback on r181632 from Dmitri)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181664 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoStringRefize some debug accel table bits.
Benjamin Kramer [Sat, 11 May 2013 18:24:28 +0000 (18:24 +0000)]
StringRefize some debug accel table bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181663 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoInstCombine: Turn urem to bitwise-and more often
David Majnemer [Sat, 11 May 2013 09:01:28 +0000 (09:01 +0000)]
InstCombine: Turn urem to bitwise-and more often

Use isKnownToBeAPowerOfTwo in visitUrem so that we may more aggressively
fold away urem instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181661 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoChange getFrameMoves to return a const reference.
Rafael Espindola [Sat, 11 May 2013 02:38:11 +0000 (02:38 +0000)]
Change getFrameMoves to return a const reference.

To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove more dead code.
Rafael Espindola [Sat, 11 May 2013 02:24:41 +0000 (02:24 +0000)]
Remove more dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181656 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd -mtriple=mipsel-linux-gnu to the test so that the compiler does
Reed Kotler [Sat, 11 May 2013 01:02:20 +0000 (01:02 +0000)]
Add -mtriple=mipsel-linux-gnu to the test so that the compiler does
not think it can support small data sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181654 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove dead code.
Rafael Espindola [Fri, 10 May 2013 23:34:51 +0000 (23:34 +0000)]
Remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181649 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSLPVectorizer: Add support for trees with external users.
Nadav Rotem [Fri, 10 May 2013 22:59:33 +0000 (22:59 +0000)]
SLPVectorizer: Add support for trees with external users.

For example:
bar() {
  int a = A[i];
  int b = A[i+1];
  B[i] = a;
  B[i+1] = b;
  foo(a);  <--- a is used outside the vectorized expression.
}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181648 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a debug print
Nadav Rotem [Fri, 10 May 2013 22:56:18 +0000 (22:56 +0000)]
Add a debug print

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181647 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd an additional testcase for PR15882.
Nadav Rotem [Fri, 10 May 2013 22:55:44 +0000 (22:55 +0000)]
Add an additional testcase for PR15882.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181646 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCheckin in of first of several patches to finish implementation of
Reed Kotler [Fri, 10 May 2013 22:25:39 +0000 (22:25 +0000)]
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.

This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.

Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.

This is needed when returning float, double, single complex, double complex
in the Mips ABI.

Helper functions in libc for mips16 are available to do this.

For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.

Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.

This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.

The only register that is modified is ra in this call.

The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMicro-optimization: don't shift an entire bitcode record over to get the code.
Jordan Rose [Fri, 10 May 2013 22:17:10 +0000 (22:17 +0000)]
Micro-optimization: don't shift an entire bitcode record over to get the code.

Previously, BitstreamCursor read an abbreviated record by splatting the
whole thing into a data vector, then extracting and removing the /first/
element. Now, it reads the first element--the record code--separately from
the actual field values.

No (intended) functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181639 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoGive the test from r181632 a target triple.
David Blaikie [Fri, 10 May 2013 22:14:39 +0000 (22:14 +0000)]
Give the test from r181632 a target triple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181637 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPR14492: Debug Info: Support for values of non-integer non-type template parameters.
David Blaikie [Fri, 10 May 2013 21:52:07 +0000 (21:52 +0000)]
PR14492: Debug Info: Support for values of non-integer non-type template parameters.

This is only tested for global variables at the moment (& includes tests
for the unnamed parameter case, since apparently this entire function
was completely untested previously)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181632 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix unused variable error.
Jyotsna Verma [Fri, 10 May 2013 21:44:02 +0000 (21:44 +0000)]
Fix unused variable error.
Earlier, this variable was used in an assert and was causing failure on
darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181630 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.
Jyotsna Verma [Fri, 10 May 2013 20:58:11 +0000 (20:58 +0000)]
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181628 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
Jyotsna Verma [Fri, 10 May 2013 20:27:34 +0000 (20:27 +0000)]
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix the R600 build.
Rafael Espindola [Fri, 10 May 2013 18:31:42 +0000 (18:31 +0000)]
Fix the R600 build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181621 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[ms-inline asm] Fix a crasher when we fail on a direct match.
Chad Rosier [Fri, 10 May 2013 18:24:17 +0000 (18:24 +0000)]
[ms-inline asm] Fix a crasher when we fail on a direct match.

The issue was that the MatchingInlineAsm and VariantID args to the
MatchInstructionImpl function weren't being set properly.  Specifically, when
parsing intel syntax, the parser thought it was parsing inline assembly in the
at&t dialect; that will never be the case.

The crash was caused when the emitter tried to emit the instruction, but the
operands weren't set.  When parsing inline assembly we only set the opcode, not
the operands, which is used to lookup the instruction descriptor.
rdar://13854391 and PR15945

Also, this commit reverts r176036.  Now that we're correctly parsing the intel
syntax the pushad/popad don't match properly.  I've reimplemented that fix using
a MnemonicAlias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181620 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove unused argument.
Rafael Espindola [Fri, 10 May 2013 18:16:59 +0000 (18:16 +0000)]
Remove unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix MCJITCAPITest.cpp unit test on Windows.
Andrew Kaylor [Fri, 10 May 2013 17:58:41 +0000 (17:58 +0000)]
Fix MCJITCAPITest.cpp unit test on Windows.

MCJIT on Windows requires an explicit target triple with "-elf" appended to generate objects in ELF format.  The common test framework was setting up this triple, but it wasn't passed to the C API in the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181614 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoBetter output for long help strings for command-line options.
Alexander Kornienko [Fri, 10 May 2013 17:15:51 +0000 (17:15 +0000)]
Better output for long help strings for command-line options.

Summary:
This patch allows using \n inside long help strings for command-line
options, so that all lines are equally indented. This is not a perfect solution,
as we don't (and probably don't want to) know about terminal width, but it
allows to format long help strings somehow readable without manually padding
them with spaces. A motivating example is -help output from clang-format (source
code in tools/clang-format/ClangFormat.cpp, see cl options offset, length,
style, and dump-config).

Reviewers: atrick, alexfh

Reviewed By: alexfh

CC: llvm-commits, rafael
Differential Revision: http://llvm-reviews.chandlerc.com/D779

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181608 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove unused function.
Rafael Espindola [Fri, 10 May 2013 16:53:12 +0000 (16:53 +0000)]
Remove unused function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181606 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoInstCombine: Don't claim to be able to evaluate any shl in a zexted type.
Benjamin Kramer [Fri, 10 May 2013 16:26:37 +0000 (16:26 +0000)]
InstCombine: Don't claim to be able to evaluate any shl in a zexted type.

The shift amount may be larger than the type leading to undefined behavior.
Limit the transform to constant shift amounts. While there update the bits to
clear in the result which may enable additional optimizations.

PR15959.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181604 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement AsmParser for ARM unwind directives.
Logan Chien [Fri, 10 May 2013 16:17:24 +0000 (16:17 +0000)]
Implement AsmParser for ARM unwind directives.

This commit implements the AsmParser for fnstart, fnend,
cantunwind, personality, handlerdata, pad, setfp, save, and
vsave directives.

This commit fixes some minor issue in the ARMELFStreamer:

* The switch back to corresponding section after the .fnend
  directive.

* Emit the unwind opcode while processing .fnend directive
  if there is no .handlerdata directive.

* Emit the unwind opcode to .ARM.extab while processing
  .handlerdata even if .personality directive does not exist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181603 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoXFAILing this test on Win32 to unbreak the build bots.
Aaron Ballman [Fri, 10 May 2013 14:42:16 +0000 (14:42 +0000)]
XFAILing this test on Win32 to unbreak the build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181600 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDAGCombiner: Generate a correct constant for vector types when folding (xor (and...
Benjamin Kramer [Fri, 10 May 2013 14:09:52 +0000 (14:09 +0000)]
DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)).

PR15948.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181597 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoInstCombine: Verify the type before transforming uitofp into select.
Benjamin Kramer [Fri, 10 May 2013 09:16:52 +0000 (09:16 +0000)]
InstCombine: Verify the type before transforming uitofp into select.

PR15952.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181586 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
Tom Stellard [Fri, 10 May 2013 02:09:45 +0000 (02:09 +0000)]
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns

The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.

https://bugs.freedesktop.org/show_bug.cgi?id=64201

Reviewed-by: Christian König <christian.koenig@amd.com>
NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181580 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Expand SUB for v2i32/v4i32
Tom Stellard [Fri, 10 May 2013 02:09:39 +0000 (02:09 +0000)]
R600: Expand SUB for v2i32/v4i32

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181579 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Expand MUL for v4i32/v2i32
Tom Stellard [Fri, 10 May 2013 02:09:34 +0000 (02:09 +0000)]
R600: Expand MUL for v4i32/v2i32

Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181578 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Expand SRA for v4i32/v2i32
Tom Stellard [Fri, 10 May 2013 02:09:29 +0000 (02:09 +0000)]
R600: Expand SRA for v4i32/v2i32

v2: Add v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181577 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Expand vselect for v4i32 and v2i32
Tom Stellard [Fri, 10 May 2013 02:09:24 +0000 (02:09 +0000)]
R600: Expand vselect for v4i32 and v2i32

v2: Add vselect v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181576 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[x86AsmParser] It's valid to stop parsing an operand at an immediate.
Chad Rosier [Thu, 9 May 2013 23:48:53 +0000 (23:48 +0000)]
[x86AsmParser] It's valid to stop parsing an operand at an immediate.
rdar://13854369 and PR15944

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181564 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTeach SelectionDAG to constant fold all-constant FMA nodes the same way that it const...
Owen Anderson [Thu, 9 May 2013 22:27:13 +0000 (22:27 +0000)]
Teach SelectionDAG to constant fold all-constant FMA nodes the same way that it constant folds FADD, FMUL, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181555 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix a documentation warning: \bried -> \brief
Dmitri Gribenko [Thu, 9 May 2013 21:16:18 +0000 (21:16 +0000)]
Fix a documentation warning: \bried -> \brief

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181551 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDocumentation warning: \param, not \parm
Dmitri Gribenko [Thu, 9 May 2013 21:15:03 +0000 (21:15 +0000)]
Documentation warning: \param, not \parm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181549 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRewrite assert to avoid warning when the record element type is byte-sized.
Jordan Rose [Thu, 9 May 2013 21:07:43 +0000 (21:07 +0000)]
Rewrite assert to avoid warning when the record element type is byte-sized.

BitstreamWriter asserts that when blob data is written from the record
element vector, each element fits in a byte. However, if the record
elements are specified as a SmallVector of 'char', this causes a warning
from -Wtautological-constant-out-of-range-compare. Fix this by using
llvm::isUInt<8> instead of a plain comparison against 256.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181545 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoGenerate a compact unwind encoding in the face of a stack alignment push.
Bill Wendling [Thu, 9 May 2013 20:10:38 +0000 (20:10 +0000)]
Generate a compact unwind encoding in the face of a stack alignment push.

We generate a `push' of a random register (%rax) if the stack needs to be
aligned by the size of that register. However, this could mess up compact unwind
generation. In particular, we want to still generate compact unwind in the
presence of this monstrosity.

Check if the push of of the %rax/%eax register. If it is and it's marked with
the `FrameSetup' flag, then we can generate a compact unwind encoding for the
function only if the push is the last FrameSetup instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181540 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.
Jyotsna Verma [Thu, 9 May 2013 19:16:07 +0000 (19:16 +0000)]
Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181535 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[GVN] Split critical-edge on the fly, instead of postpone edge-splitting to next
Shuxin Yang [Thu, 9 May 2013 18:34:27 +0000 (18:34 +0000)]
[GVN] Split critical-edge on the fly, instead of postpone edge-splitting to next
  iteration.

  This on step toward non-iterative GVN. My local hack suggests that getting rid
of iteration will speedup GVN by 30%+ on a medium sized input (2k LOC, C++).
I cannot explain why not 2x or more at this moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181532 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHexagon: Use relation map for getMatchingCondBranchOpcode() and
Jyotsna Verma [Thu, 9 May 2013 18:25:44 +0000 (18:25 +0000)]
Hexagon: Use relation map for getMatchingCondBranchOpcode() and
getInvertedPredicatedOpcode() functions instead of switch cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181530 91177308-0d34-0410-b5e6-96231b3b80d8