[SystemZ] Rework handling of constant PC-relative operands
authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>
Tue, 14 May 2013 09:47:26 +0000 (09:47 +0000)
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>
Tue, 14 May 2013 09:47:26 +0000 (09:47 +0000)
commitb594c4c873bd3e2ee560cc83bd50282ec56b01e9
treebdd4dcfa31b5febdfcd797614742bc7b99a3fe02
parent58b854d7e9e5fb09a60a4e3a66e8049a7e4a01f6
[SystemZ] Rework handling of constant PC-relative operands

The GNU assembler treats things like:

        brasl   %r14, 100

in the same way as:

        brasl   %r14, .+100

rather than as a branch to absolute address 100.  We implemented this in
LLVM by creating an immediate operand rather than the usual expr operand,
and by handling immediate operands specially in the code emitter.
This was undesirable for (at least) three reasons:

- the specialness of immediate operands was exposed to the backend MC code,
  rather than being limited to the assembler parser.

- in disassembly, an immediate operand really is an absolute address.
  (Note that this means reassembling printed disassembly can't recreate
  the original code.)

- it would interfere with any assembly manipulation that we might
  try in future.  E.g. operations like branch shortening can change
  the relative position of instructions, but any code that updates
  sym+offset addresses wouldn't update an immediate "100" operand
  in the same way as an explicit ".+100" operand.

This patch changes the implementation so that the assembler creates
a "." label for immediate PC-relative operands, so that the operand
to the MCInst is always the absolute address.  The patch also adds
some error checking of the offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773 91177308-0d34-0410-b5e6-96231b3b80d8
31 files changed:
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
lib/Target/SystemZ/SystemZOperands.td
test/MC/SystemZ/insn-bras-01.s
test/MC/SystemZ/insn-brasl-01.s
test/MC/SystemZ/insn-brc-01.s
test/MC/SystemZ/insn-brc-02.s
test/MC/SystemZ/insn-brcl-01.s
test/MC/SystemZ/insn-brcl-02.s
test/MC/SystemZ/insn-cgfrl-01.s
test/MC/SystemZ/insn-cghrl-01.s
test/MC/SystemZ/insn-cgrl-01.s
test/MC/SystemZ/insn-chrl-01.s
test/MC/SystemZ/insn-clgfrl-01.s
test/MC/SystemZ/insn-clghrl-01.s
test/MC/SystemZ/insn-clgrl-01.s
test/MC/SystemZ/insn-clhrl-01.s
test/MC/SystemZ/insn-clrl-01.s
test/MC/SystemZ/insn-crl-01.s
test/MC/SystemZ/insn-larl-01.s
test/MC/SystemZ/insn-lgfrl-01.s
test/MC/SystemZ/insn-lghrl-01.s
test/MC/SystemZ/insn-lgrl-01.s
test/MC/SystemZ/insn-lhrl-01.s
test/MC/SystemZ/insn-llgfrl-01.s
test/MC/SystemZ/insn-llghrl-01.s
test/MC/SystemZ/insn-llhrl-01.s
test/MC/SystemZ/insn-lrl-01.s
test/MC/SystemZ/insn-stgrl-01.s
test/MC/SystemZ/insn-sthrl-01.s
test/MC/SystemZ/insn-strl-01.s