oota-llvm.git
11 years agoR600/SI: Add pattern for rotr
Tom Stellard [Mon, 20 May 2013 15:02:24 +0000 (15:02 +0000)]
R600/SI: Add pattern for rotr

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Swap the legality of rotl and rotr
Tom Stellard [Mon, 20 May 2013 15:02:19 +0000 (15:02 +0000)]
R600: Swap the legality of rotl and rotr

The hardware supports rotr and not rotl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Add patterns for 64-bit shift operations
Tom Stellard [Mon, 20 May 2013 15:02:12 +0000 (15:02 +0000)]
R600/SI: Add patterns for 64-bit shift operations

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182284 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Use the same names for VOP3 operands and encoding fields
Tom Stellard [Mon, 20 May 2013 15:02:08 +0000 (15:02 +0000)]
R600/SI: Use the same names for VOP3 operands and encoding fields

This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182283 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: Make fitsRegClass() operands const
Tom Stellard [Mon, 20 May 2013 15:02:01 +0000 (15:02 +0000)]
R600/SI: Make fitsRegClass() operands const

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoVSTn instructions have a number of encoding constraints which are not implemented...
Mihai Popa [Mon, 20 May 2013 14:57:05 +0000 (14:57 +0000)]
VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoQ registers are encoded in fields of the same length as D registers. As Q registers...
Mihai Popa [Mon, 20 May 2013 14:42:43 +0000 (14:42 +0000)]
Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[SystemZ] Add long branch pass
Richard Sandiford [Mon, 20 May 2013 14:23:08 +0000 (14:23 +0000)]
[SystemZ] Add long branch pass

Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoEnable pod-like optimizations for pred and succ iterators.
Benjamin Kramer [Mon, 20 May 2013 13:12:58 +0000 (13:12 +0000)]
Enable pod-like optimizations for pred and succ iterators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182257 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs
Justin Holewinski [Mon, 20 May 2013 12:13:32 +0000 (12:13 +0000)]
[NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs

This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.

The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space.  Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182254 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to...
Justin Holewinski [Mon, 20 May 2013 12:13:28 +0000 (12:13 +0000)]
[NVPTX] Fix i1 kernel parameters and global variables.  ABI rules say we need to use .u8 for i1 parameters for kernels.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182253 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPR15868 fix.
Stepan Dyatkovskiy [Mon, 20 May 2013 08:01:34 +0000 (08:01 +0000)]
PR15868 fix.

Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:

Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack  ------ ...

FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.

We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.

This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDisable remote MCJIT on pre-v6 ARM
Renato Golin [Mon, 20 May 2013 07:46:06 +0000 (07:46 +0000)]
Disable remote MCJIT on pre-v6 ARM

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182235 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPartially revert change in r181200 that tried to simplify JIT unit test #ifdefs.
Bob Wilson [Mon, 20 May 2013 06:13:09 +0000 (06:13 +0000)]
Partially revert change in r181200 that tried to simplify JIT unit test #ifdefs.

The export list for this test requires the following symbols to be available:
  JITTest_AvailableExternallyFunction
  JITTest_AvailableExternallyGlobal
The change in r181200 commented them out, which caused the test to fail to
link, at least on Darwin. I have only reverted the change for arm, since I
can't test the other targets and since it sounds like that change was fixing
real problems for those other targets. It should be possible to rearrange the
code to keep those definitions outside the #ifdefs, but that should be done by
someone who can reproduce the problems that r181200 was trying to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182233 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAlso expand 64-bit bitcasts.
Jakob Stoklund Olesen [Mon, 20 May 2013 01:01:43 +0000 (01:01 +0000)]
Also expand 64-bit bitcasts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement spill and fill of I64Regs.
Jakob Stoklund Olesen [Mon, 20 May 2013 00:53:25 +0000 (00:53 +0000)]
Implement spill and fill of I64Regs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182228 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMark i64 SETCC as expand so it is turned into a SELECT_CC.
Jakob Stoklund Olesen [Mon, 20 May 2013 00:28:36 +0000 (00:28 +0000)]
Mark i64 SETCC as expand so it is turned into a SELECT_CC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182227 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReplace some bit operations with simpler ones. No functionality change.
Benjamin Kramer [Sun, 19 May 2013 22:01:57 +0000 (22:01 +0000)]
Replace some bit operations with simpler ones. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't use %g0 to materialize 0 directly.
Jakob Stoklund Olesen [Sun, 19 May 2013 21:47:13 +0000 (21:47 +0000)]
Don't use %g0 to materialize 0 directly.

The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSelect i64 values with %icc conditions.
Jakob Stoklund Olesen [Sun, 19 May 2013 20:38:21 +0000 (20:38 +0000)]
Select i64 values with %icc conditions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182224 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>
Bob Wilson [Sun, 19 May 2013 20:33:51 +0000 (20:33 +0000)]
Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>

This fixes a bootstrapping problem with builds for Apple ARM targets.
Clang had the wrong prototype for __clear_cache with ARM targets.  Rafael
fixed that in clang svn r181784 and r181810, but without those changes,
we can't build this code for ARM because clang reports an error about the
declaration in Memory.inc not matching the builtin declaration. Some of our
buildbots need to use an older compiler that doesn't have the clang fix.
Since __clear_cache is never used here when __APPLE__ is defined, I'm just
conditionalizing the declaration to match that. I also moved the declaration
of sys_icache_invalidate inside the conditional for __APPLE__ while I was at
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182223 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd floating point selects on %xcc predicates.
Jakob Stoklund Olesen [Sun, 19 May 2013 20:33:11 +0000 (20:33 +0000)]
Add floating point selects on %xcc predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182222 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoImplement SPselectfcc for i64 operands.
Jakob Stoklund Olesen [Sun, 19 May 2013 20:20:54 +0000 (20:20 +0000)]
Implement SPselectfcc for i64 operands.

Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182221 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSubArch support in MCJIT unittest
Renato Golin [Sun, 19 May 2013 20:10:10 +0000 (20:10 +0000)]
SubArch support in MCJIT unittest

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182220 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[Sparc] Rearrange integer registers' allocation order so that register allocator...
Venkatraman Govindaraju [Sun, 19 May 2013 20:07:20 +0000 (20:07 +0000)]
[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.

Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAArch64: enable MCJIT unittests
Tim Northover [Sun, 19 May 2013 19:44:56 +0000 (19:44 +0000)]
AArch64: enable MCJIT unittests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182217 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoHandle i64 FrameIndex nodes in SPARC v9 mode.
Jakob Stoklund Olesen [Sun, 19 May 2013 19:14:24 +0000 (19:14 +0000)]
Handle i64 FrameIndex nodes in SPARC v9 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182216 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAArch64: make RuntimeDyld relocations idempotent
Tim Northover [Sun, 19 May 2013 15:39:03 +0000 (15:39 +0000)]
AArch64: make RuntimeDyld relocations idempotent

AArch64 ELF uses .rela relocations so there's no need to actually make
use of the bits we're setting in the destination  However, we should
make sure all bits are cleared properly since multiple runs of
resolveRelocations are possible and these could combine to produce
invalid results if stale versions remain in the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182214 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoInvalidate instruction cache when setting memory to be executable.
Tim Northover [Sun, 19 May 2013 15:28:16 +0000 (15:28 +0000)]
Invalidate instruction cache when setting memory to be executable.

lli's remote MCJIT code calls setExecutable just prior to running
code. In line with Darwin behaviour this seems to be the place to
invalidate any caches needed so that relocations can take effect
properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182213 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoTemporarily disable this test because it is failing when using libc++.
Bob Wilson [Sun, 19 May 2013 14:59:08 +0000 (14:59 +0000)]
Temporarily disable this test because it is failing when using libc++.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182212 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMove the remaining simplify-libcalls tests to instcombine, merging most of them into...
Benjamin Kramer [Sun, 19 May 2013 13:28:39 +0000 (13:28 +0000)]
Move the remaining simplify-libcalls tests to instcombine, merging most of them into a single file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182211 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPrint uint64_t -debug text correctly on 32-bit hosts
Tim Northover [Sun, 19 May 2013 09:55:06 +0000 (09:55 +0000)]
Print uint64_t -debug text correctly on 32-bit hosts

On 32-bit hosts %p can print garbage when given a uint64_t, we should
use %llx instead. This only affects the output of the debugging text
produced by lli.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182209 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUnsupported remote JIT on ARM
Renato Golin [Sat, 18 May 2013 19:42:07 +0000 (19:42 +0000)]
Unsupported remote JIT on ARM

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182201 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoisKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.
David Majnemer [Sat, 18 May 2013 19:30:37 +0000 (19:30 +0000)]
isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.

This is useful if something that looks like (x & (1 << y)) ? 64 : 32 is
the divisor in a modulo operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182200 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoLoopVectorize: Handle single edge PHIs
Arnold Schwaighofer [Sat, 18 May 2013 18:38:34 +0000 (18:38 +0000)]
LoopVectorize: Handle single edge PHIs

We might encouter single edge PHIs - handle them with an identity select.

Fixes PR15990.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182199 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agodocs/Passes: fix some typos
Dmitri Gribenko [Sat, 18 May 2013 18:01:44 +0000 (18:01 +0000)]
docs/Passes: fix some typos

Patch by Yacine Belkadi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182197 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd basic support for ELF32-ppc relocations to llvm-dwarfdump.
Benjamin Kramer [Sat, 18 May 2013 16:00:35 +0000 (16:00 +0000)]
Add basic support for ELF32-ppc relocations to llvm-dwarfdump.

Should help the ppc32 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182194 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCheck InlineAsm clobbers in PPCCTRLoops
Hal Finkel [Sat, 18 May 2013 09:20:39 +0000 (09:20 +0000)]
Check InlineAsm clobbers in PPCCTRLoops

We don't need to reject all inline asm as using the counter register (most does
not). Only those that explicitly clobber the counter register need to prevent
the transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182191 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAArch64: add CMake dependency to fix very parallel builds
Tim Northover [Sat, 18 May 2013 08:17:47 +0000 (08:17 +0000)]
AArch64: add CMake dependency to fix very parallel builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182190 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoX86: Bad peephole interaction between adc, MOV32r0
David Majnemer [Sat, 18 May 2013 01:02:03 +0000 (01:02 +0000)]
X86: Bad peephole interaction between adc, MOV32r0

The peephole tries to reorder MOV32r0 instructions such that they are
before the instruction that modifies EFLAGS.

The problem is that the peephole does not consider the case where the
instruction that modifies EFLAGS also depends on the previous state of
EFLAGS.

Instead, walk backwards until we find an instruction that has a def for
EFLAGS but does not have a use.
If we find such an instruction, insert the MOV32r0 before it.
If it cannot find such an instruction, skip the optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182184 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove duplicated comment
Matt Arsenault [Sat, 18 May 2013 00:24:09 +0000 (00:24 +0000)]
Remove duplicated comment

The same comment is already made in the header

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182181 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd LLVMContext argument to getSetCCResultType
Matt Arsenault [Sat, 18 May 2013 00:21:46 +0000 (00:21 +0000)]
Add LLVMContext argument to getSetCCResultType

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoSupport unaligned load/store on more ARM targets
JF Bastien [Fri, 17 May 2013 23:49:01 +0000 (23:49 +0000)]
Support unaligned load/store on more ARM targets

This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store
for v6+ Darwin as well as for v7+ on Linux and NaCl.

The distinction is made because v6 doesn't guarantee support (but LLVM
assumes that Apple controls hardware+kernel and therefore have
conformant v6 CPUs), whereas v7 does provide this guarantee (and
Linux/NaCl behave sanely).

The patch keeps the -arm-strict-align command line option, and adds
-arm-no-strict-align. They behave similarly to GCC's -mstrict-align and
-mnostrict-align.

I originally encountered this discrepancy in FastIsel tests which expect
unaligned load/store generation. Overall this should slightly improve
performance in most cases because of reduced I$ pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182175 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix the configure build.
Rafael Espindola [Fri, 17 May 2013 23:20:58 +0000 (23:20 +0000)]
Fix the configure build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182172 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoConvert obj2yaml to use yamlio.
Rafael Espindola [Fri, 17 May 2013 22:58:42 +0000 (22:58 +0000)]
Convert obj2yaml to use yamlio.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182169 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix the build in c++11 mode.
Rafael Espindola [Fri, 17 May 2013 22:45:52 +0000 (22:45 +0000)]
Fix the build in c++11 mode.

The errors were:

non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list

and

non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182168 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoReplace redundant code
Matt Arsenault [Fri, 17 May 2013 21:43:43 +0000 (21:43 +0000)]
Replace redundant code

Use EVT::changeExtendedVectorElementTypeToInteger instead of doing the
same thing that it does

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182165 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd missing -*- C++ -*- to headers
Matt Arsenault [Fri, 17 May 2013 21:43:39 +0000 (21:43 +0000)]
Add missing -*- C++ -*- to headers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182164 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd missing verb to comment in PassNameParser.h
Derek Schuff [Fri, 17 May 2013 16:51:32 +0000 (16:51 +0000)]
Add missing verb to comment in PassNameParser.h
Patch by Mark Seaborn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182131 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Lower int_load_input to copyFromReg instead of Register node
Vincent Lejeune [Fri, 17 May 2013 16:51:06 +0000 (16:51 +0000)]
R600: Lower int_load_input to copyFromReg instead of Register node

It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182130 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Use bottom up scheduling algorithm
Vincent Lejeune [Fri, 17 May 2013 16:50:56 +0000 (16:50 +0000)]
R600: Use bottom up scheduling algorithm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Use depth first scheduling algorithm
Vincent Lejeune [Fri, 17 May 2013 16:50:44 +0000 (16:50 +0000)]
R600: Use depth first scheduling algorithm

It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182128 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Replace big texture opcode switch in scheduler by usesTC/usesVC
Vincent Lejeune [Fri, 17 May 2013 16:50:37 +0000 (16:50 +0000)]
R600: Replace big texture opcode switch in scheduler by usesTC/usesVC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182127 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Relax some vector constraints on Dot4.
Vincent Lejeune [Fri, 17 May 2013 16:50:32 +0000 (16:50 +0000)]
R600: Relax some vector constraints on Dot4.

Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Improve texture handling
Vincent Lejeune [Fri, 17 May 2013 16:50:20 +0000 (16:50 +0000)]
R600: Improve texture handling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Rename 128 bit registers.
Vincent Lejeune [Fri, 17 May 2013 16:50:09 +0000 (16:50 +0000)]
R600: Rename 128 bit registers.

Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182124 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Some factorization
Vincent Lejeune [Fri, 17 May 2013 16:50:02 +0000 (16:50 +0000)]
R600: Some factorization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182123 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Factorize Fetch size limit inside AMDGPUSubTarget
Vincent Lejeune [Fri, 17 May 2013 16:49:55 +0000 (16:49 +0000)]
R600: Factorize Fetch size limit inside AMDGPUSubTarget

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182122 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: prettier dump of clamp
Vincent Lejeune [Fri, 17 May 2013 16:49:49 +0000 (16:49 +0000)]
R600: prettier dump of clamp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182121 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Fix encoding for R600 family GPUs
Tom Stellard [Fri, 17 May 2013 15:23:21 +0000 (15:23 +0000)]
R600: Fix encoding for R600 family GPUs

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182113 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600: Pass MCSubtargetInfo reference to R600CodeEmitter
Tom Stellard [Fri, 17 May 2013 15:23:12 +0000 (15:23 +0000)]
R600: Pass MCSubtargetInfo reference to R600CodeEmitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182112 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[Sparc] Implements hasReservedCallFrame and hasFP.
Venkatraman Govindaraju [Fri, 17 May 2013 15:14:34 +0000 (15:14 +0000)]
[Sparc] Implements hasReservedCallFrame and hasFP.
 This is to generate correct framesetup code when the function
 has variable sized allocas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182108 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoX86: Make shuffle -> shift conversion more aggressive about undefs.
Benjamin Kramer [Fri, 17 May 2013 14:48:34 +0000 (14:48 +0000)]
X86: Make shuffle -> shift conversion more aggressive about undefs.

Shuffles that only move an element into position 0 of the vector are common in
the output of the loop vectorizer and often generate suboptimal code when SSSE3
is not available. Lower them to vector shifts if possible.

We still prefer palignr over psrldq because it has higher throughput on
sandybridge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182102 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFileCheckize test.
Benjamin Kramer [Fri, 17 May 2013 14:48:25 +0000 (14:48 +0000)]
FileCheckize test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182101 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoLoopVectorize: Simplify code. No functionality change.
Benjamin Kramer [Fri, 17 May 2013 14:48:17 +0000 (14:48 +0000)]
LoopVectorize: Simplify code. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182100 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agor182085 introduced a change that triggered an assertion on ARM. This is an immediate fix
David Tweed [Fri, 17 May 2013 14:31:59 +0000 (14:31 +0000)]
r182085 introduced a change that triggered an assertion on ARM. This is an immediate fix
which doesn't resolve the deeper problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182098 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Fix hi/lo encoding in old-style code emitter
Ulrich Weigand [Fri, 17 May 2013 14:14:12 +0000 (14:14 +0000)]
[PowerPC] Fix hi/lo encoding in old-style code emitter

This patch implements the equivalent change to r182091/r182092
in the old-style code emitter.  Instead of having two separate
16-bit immediate encoding routines depending on the instruction,
this patch introduces a single encoder that checks the machine
operand flags to decide whether the low or high half of a
symbol address is required.

Since now both encoders make no further distinction between
"symbolLo" and "symbolHi", the .td operand can now use a
single getS16ImmEncoding method.

Tested by running the old-style JIT tests on 32-bit Linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182097 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Merge/rename PPC fixup types
Ulrich Weigand [Fri, 17 May 2013 12:37:21 +0000 (12:37 +0000)]
[PowerPC] Merge/rename PPC fixup types

Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly
the same everywhere, it no longer makes sense to have two fixup types.

This patch merges them both into a single type fixup_ppc_half16,
and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency.
(The half16 and half16ds names are taken from the description of
relocation types in the PowerPC ABI.)

No change in code generation expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Fix processing of ha16/lo16 fixups
Ulrich Weigand [Fri, 17 May 2013 12:36:29 +0000 (12:36 +0000)]
[PowerPC] Fix processing of ha16/lo16 fixups

The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.

This isn't quite correct, however.  It is valid -if unusual- assembler
to use, e.g.
  li 1, symbol@ha
or
  lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.

In addition, both
  li 1, symbol
and
  lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).

To fix this, two places need to be adapted.  If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType.  This routine already looks at
the VK_ type to determine the relocation.  The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa.  This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.

If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16.  Again, this is incorrect; see the above example
  lis 1, symbol

Now, in theory we'd have to respect a VK_ modifier here.  However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.

If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers.  We'd then have to handle @ha etc. there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix a typo (ouput => output)
Sylvestre Ledru [Fri, 17 May 2013 12:31:43 +0000 (12:31 +0000)]
Fix a typo (ouput => output)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182090 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDon't cast away constness.
Benjamin Kramer [Fri, 17 May 2013 11:39:41 +0000 (11:39 +0000)]
Don't cast away constness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182086 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMinor changes to the MCJITTest unittests to use the correct API for finalizing
David Tweed [Fri, 17 May 2013 10:01:46 +0000 (10:01 +0000)]
Minor changes to the MCJITTest unittests to use the correct API for finalizing
the JIT object (including XFAIL an ARM test that now needs fixing). Also renames
internal function for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182085 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoR600/SI: return undef instead of null for skipped arguments
Christian Konig [Fri, 17 May 2013 09:46:48 +0000 (09:46 +0000)]
R600/SI: return undef instead of null for skipped arguments

This is a candidate for the stable branch.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182084 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot.
Venkatraman Govindaraju [Thu, 16 May 2013 23:53:29 +0000 (23:53 +0000)]
[Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182063 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoGenerate debug info for by-value struct args even if they are not used.
Adrian Prantl [Thu, 16 May 2013 23:44:12 +0000 (23:44 +0000)]
Generate debug info for by-value struct args even if they are not used.
radar://problem/13865940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182062 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agollvm-objdump: Initialize MCDisassembler once instead of for each section.
Ahmed Bougacha [Thu, 16 May 2013 21:28:23 +0000 (21:28 +0000)]
llvm-objdump: Initialize MCDisassembler once instead of for each section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182054 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
Akira Hatanaka [Thu, 16 May 2013 21:17:15 +0000 (21:17 +0000)]
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).

Previously, three instructions were needed:

trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)

Now we need only two:

trunc.w.s $f0, $f2
swc1 $f0, 0($2)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoRemove addFrameMove.
Rafael Espindola [Thu, 16 May 2013 21:02:15 +0000 (21:02 +0000)]
Remove addFrameMove.

Now that we have good testing, remove addFrameMove and create cfi
instructions directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182052 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMore test coverage for addFrameMove.
Rafael Espindola [Thu, 16 May 2013 20:50:56 +0000 (20:50 +0000)]
More test coverage for addFrameMove.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182051 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Factor out unaligned store lowering code.
Akira Hatanaka [Thu, 16 May 2013 20:45:17 +0000 (20:45 +0000)]
[mips] Factor out unaligned store lowering code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182050 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFix cpu on test CodeGen/PowerPC/ctrloop-fp64.ll
Hal Finkel [Thu, 16 May 2013 20:28:05 +0000 (20:28 +0000)]
Fix cpu on test CodeGen/PowerPC/ctrloop-fp64.ll

We need ppc instead of generic to override native features on ppc machines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182049 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMips assembler: Add TwoOperandConstraint definitions
Jack Carter [Thu, 16 May 2013 20:24:27 +0000 (20:24 +0000)]
Mips assembler: Add TwoOperandConstraint definitions

This patch removes alias definition for addiu $rs,$imm
and instead uses the TwoOperandAliasConstraint field in
the ArithLogicI instruction class.

This way all instructions that inherit ArithLogicI class
have the same macro defined.

The usage examples are added to test files.

Patch by Vladimir Medic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMips td file formatting: white space and long lines
Jack Carter [Thu, 16 May 2013 20:08:49 +0000 (20:08 +0000)]
Mips td file formatting: white space and long lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182047 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMore addFrameMove test coverage.
Rafael Espindola [Thu, 16 May 2013 20:00:45 +0000 (20:00 +0000)]
More addFrameMove test coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182046 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoCreate an new preheader in PPCCTRLoops to avoid counter register clobbers
Hal Finkel [Thu, 16 May 2013 19:58:38 +0000 (19:58 +0000)]
Create an new preheader in PPCCTRLoops to avoid counter register clobbers

Some IR-level instructions (such as FP <-> i64 conversions) are not chained
w.r.t. the mtctr intrinsic and yet may become function calls that clobber the
counter register. At the selection-DAG level, these might be reordered with the
mtctr intrinsic causing miscompiles. To avoid this situation, if an existing
preheader has instructions that might use the counter register, create a new
preheader for the mtctr intrinsic. This extra block will be remerged with the
old preheader at the MI level, but will prevent unwanted reordering at the
selection-DAG level.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182045 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Test case for r182042. Add comment.
Akira Hatanaka [Thu, 16 May 2013 19:57:23 +0000 (19:57 +0000)]
[mips] Test case for r182042. Add comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182044 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
Akira Hatanaka [Thu, 16 May 2013 19:48:37 +0000 (19:48 +0000)]
[mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
invalid instruction sequence.

Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.

mtc1 $f4, $4         # int-to-fp move instruction.
mov.s $f2, $f4       # move contents of $f4 to $f2.
cvt.s.w $f0, $f2     # int-to-fp conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMore test coverage for addFrameMove.
Rafael Espindola [Thu, 16 May 2013 19:44:40 +0000 (19:44 +0000)]
More test coverage for addFrameMove.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182041 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMips assembler: Add branch macro definitions
Jack Carter [Thu, 16 May 2013 19:40:19 +0000 (19:40 +0000)]
Mips assembler: Add branch macro definitions

This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm

The corresponding test cases are added.

Patch by Vladimir Medic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoDAGCombine: Also shrink eq compares where the constant is exactly as large as the...
Benjamin Kramer [Thu, 16 May 2013 18:47:58 +0000 (18:47 +0000)]
DAGCombine: Also shrink eq compares where the constant is exactly as large as the smaller type.

if ((x & 255) == 255)

before: movzbl  %al, %eax
        cmpl  $255, %eax

after:  cmpb  $-1, %al

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182038 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Fix indentation.
Akira Hatanaka [Thu, 16 May 2013 18:42:42 +0000 (18:42 +0000)]
[mips] Fix indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182036 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[mips] Delete unused enum value.
Akira Hatanaka [Thu, 16 May 2013 18:40:12 +0000 (18:40 +0000)]
[mips] Delete unused enum value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182035 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd TargetRegisterInfo::getCoveringLanes().
Jakob Stoklund Olesen [Thu, 16 May 2013 18:03:08 +0000 (18:03 +0000)]
Add TargetRegisterInfo::getCoveringLanes().

This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8

11 years ago[PowerPC] Use true offset value in "memrix" machine operands
Ulrich Weigand [Thu, 16 May 2013 17:58:02 +0000 (17:58 +0000)]
[PowerPC] Use true offset value in "memrix" machine operands

This is the second part of the change to always return "true"
offset values from getPreIndexedAddressParts, tackling the
case of "memrix" type operands.

This is about instructions like LD/STD that only have a 14-bit
field to encode immediate offsets, which are implicitly extended
by two zero bits by the machine, so that in effect we can access
16-bit offsets as long as they are a multiple of 4.

The PowerPC back end currently handles such instructions by
carrying the 14-bit value (as it will get encoded into the
actual machine instructions) in the machine operand fields
for such instructions.  This means that those values are
in fact not the true offset, but rather the offset divided
by 4 (and then truncated to an unsigned 14-bit value).

Like in the case fixed in r182012, this makes common code
operations on such offset values not work as expected.
Furthermore, there doesn't really appear to be any strong
reason why we should encode machine operands this way.

This patch therefore changes the encoding of "memrix" type
machine operands to simply contain the "true" offset value
as a signed immediate value, while enforcing the rules that
it must fit in a 16-bit signed value and must also be a
multiple of 4.

This change must be made simultaneously in all places that
access machine operands of this type.  However, just about
all those changes make the code simpler; in many cases we
can now just share the same code for memri and memrix
operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoPPC32 cannot form counter loops around i64 FP conversions
Hal Finkel [Thu, 16 May 2013 16:52:41 +0000 (16:52 +0000)]
PPC32 cannot form counter loops around i64 FP conversions

On PPC32, i64 FP conversions are implemented using runtime calls (which clobber
the counter register). These must be excluded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182023 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd a triple to the test to try to fix the windows bots.
Rafael Espindola [Thu, 16 May 2013 16:48:46 +0000 (16:48 +0000)]
Add a triple to the test to try to fix the windows bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182022 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoMore addFrameMove test coverage.
Rafael Espindola [Thu, 16 May 2013 16:34:38 +0000 (16:34 +0000)]
More addFrameMove test coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182021 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoUse new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll
Bill Schmidt [Thu, 16 May 2013 16:15:18 +0000 (16:15 +0000)]
Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll

While testing some experimental code to add vector-scalar registers to
PowerPC, I noticed that a couple of independent instructions were
flipped by the scheduler.  The new CHECK-DAG support is perfect for
avoiding this problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182020 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoAdd more addFrameMove test coverage.
Rafael Espindola [Thu, 16 May 2013 16:09:54 +0000 (16:09 +0000)]
Add more addFrameMove test coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182019 91177308-0d34-0410-b5e6-96231b3b80d8

11 years agoFixing a 64-bit conversion warning in MSVC.
Aaron Ballman [Thu, 16 May 2013 16:03:36 +0000 (16:03 +0000)]
Fixing a 64-bit conversion warning in MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182018 91177308-0d34-0410-b5e6-96231b3b80d8