DataFlowSanitizer: move abilist input file to Inputs.
[oota-llvm.git] / test / CodeGen / R600 /
2013-08-14 Tom StellardR600/SI: Handle MSAA texture targets
2013-08-14 Tom StellardR600/SI: Allow conversion between v32i8 and v8i32
2013-08-14 Tom StellardR600/SI: Add pattern for fp_to_uint
2013-08-12 Tom StellardR600: Set scheduling preference to Sched::Source
2013-08-10 Niels Ole SalscheiderR600/SI: FMA is faster than fmul and fadd for f64
2013-08-10 Niels Ole SalscheiderR600/SI: Add FMA pattern
2013-08-08 Niels Ole SalscheiderR600/SI: Implement fp32<->fp64 conversions
2013-08-08 Niels Ole SalscheiderR600/SI: Implement sint<->fp64 conversions
2013-08-06 Tom StellardR600/SI: Use VSrc_* register classes as the default...
2013-08-06 Tom StellardR600/SI: Add more special cases for opcodes to ensureSR...
2013-08-06 Tom StellardFactor FlattenCFG out from SimplifyCFG
2013-08-05 Tom StellardR600/SI: Add missing test for r187749
2013-08-01 Tom StellardR600: Add 64-bit float load/store support
2013-08-01 Tom StellardR600: Use 64-bit alignment for 64-bit kernel arguments
2013-08-01 Tom StellardR600/SI: Custom lower i64 ZERO_EXTEND
2013-07-31 Tom StellardRevert "R600: Non vector only instruction can be schedu...
2013-07-31 Vincent LejeuneR600: Avoid more than 4 literals in the same instructio...
2013-07-31 Vincent LejeuneR600: Non vector only instruction can be scheduled...
2013-07-30 Tom StellardR600/SI: Expand vector fp <-> int conversions
2013-07-30 Quentin Colombet[R600] Replicate old DAGCombiner behavior in target...
2013-07-30 Quentin Colombet[DAGCombiner] insert_vector_elt: Avoid building a vecto...
2013-07-23 Tom StellardDAGCombiner: Pass the correct type to TargetLowering...
2013-07-23 Tom StellardR600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS...
2013-07-23 Tom StellardR600: Add support for 24-bit MAD instructions
2013-07-23 Tom StellardR600: Add support for 24-bit MUL instructions
2013-07-23 Tom StellardR600: Improve support for < 32-bit loads
2013-07-23 Tom StellardR600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISe...
2013-07-23 Tom StellardR600: Use KCache for kernel arguments
2013-07-23 Tom StellardR600: Use the same compute kernel calling convention...
2013-07-23 Tom StellardR600: Use correct LoadExtType when lowering kernel...
2013-07-23 Tom StellardR600: Clean up extended load patterns
2013-07-23 Tom StellardR600: Expand vector FNEG
2013-07-19 Vincent LejeuneR600: Don't emit empty then clause and use alu_pop_after
2013-07-18 Tom StellardR600/SI: Fix crash with VSELECT
2013-07-18 Tom StellardR600/SI: Add support for v2f32 loads
2013-07-18 Tom StellardR600/SI: Add support for v2f32 stores
2013-07-18 Tom StellardR600: Expand VSELECT for all types
2013-07-15 Tom StellardR600/SI: Add support for 64-bit loads
2013-07-12 Benjamin KramerR600: Reapply testcase from r186178, the big endian...
2013-07-12 Tom StellardR600: Remove the fpconst64.ll test which was failing...
2013-07-12 Tom StellardR600/SI: Add support for f64 kernel arguments
2013-07-12 Tom StellardR600/SI: Implement select and compares for SI
2013-07-12 Tom StellardR600/SI: Add fsqrt pattern for SI
2013-07-12 Tom StellardR600/SI: Add double precision fsub pattern for SI
2013-07-12 Tom StellardR600/SI: SI support for 64bit ConstantFP
2013-07-12 Tom StellardR600/SI: Add initial double precision support for SI
2013-07-10 Michel DanzerR600/SI: Initial local memory support
2013-07-10 Michel DanzerR600/SI: Add intrinsic for retrieving the current thread ID
2013-07-10 Michel DanzerR600/SI: Add intrinsics for texture sampling with user...
2013-07-09 Vincent LejeuneR600: Do not predicated basic block with multiple alu...
2013-07-09 Vincent LejeuneR600: Fix a rare bug where swizzle optimization returns...
2013-07-09 Vincent LejeuneR600: Fix wrong export reswizzling
2013-07-09 Vincent LejeuneR600: Use DAG lowering pass to handle fcos/fsin
2013-07-03 Rafael EspindolaPrefix failing commands with not to make clear they...
2013-06-29 Vincent LejeuneR600: Support schedule and packetization of trans-only...
2013-06-28 Tom StellardR600: Add local memory support via LDS
2013-06-28 Tom StellardR600: Add support for GROUP_BARRIER instruction
2013-06-27 Tom StellardR600: Remove alu-split.ll test
2013-06-25 Tom StellardR600: Use new getNamedOperandIdx function generated...
2013-06-25 Aaron WatryR600: Add v2i32 test for vselect
2013-06-25 Aaron WatryR600/SI: Expand xor v2i32/v4i32
2013-06-25 Aaron WatryR600: Add v2i32 test for setcc on evergreen
2013-06-25 Aaron WatryR600/SI: Expand urem of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
2013-06-25 Aaron WatryR600/SI: Expand ashr of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand srl of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand shl of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand or of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand mul of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand and of v2i32/v4i32 for SI
2013-06-25 Tom StellardR600/SI: Report unaligned memory accesses as legal...
2013-06-25 Tom StellardR600: Add support for i32 loads from the constant addre...
2013-06-25 Tom StellardR600/SI: Add support for v4i32 and v4f32 kernel args
2013-06-25 Tom StellardR600: Fix typo in R600Schedule.td
2013-06-20 Tom StellardR600/SI: Expand sub for v2i32 and v4i32 for SI
2013-06-20 Tom StellardR600/SI: Expand add for v2i32 and v4i32
2013-06-20 Tom StellardR600: Expand v2i32 load/store instead of custom lowering
2013-06-17 Vincent LejeuneR600: PV stores Reg id, not index
2013-06-17 Vincent LejeuneR600: Properly set COUNT_3 bit in TEX clause initiating...
2013-06-15 Tom StellardR600: Add SI load support for v[24]i32 and store for...
2013-06-14 Tom StellardR600: Use correct encoding for Vertex Fetch instruction...
2013-06-14 Tom StellardR600: Use EXPORT_RAT_INST_STORE_DWORD for stores on...
2013-06-07 Vincent LejeuneR600: Anti dep better handled in tex clause
2013-06-07 Tom StellardR600: Fix calculation of stack offset in AMDGPUFrameLow...
2013-06-07 Tom StellardR600: Fix the fetch limits for R600 generation GPUs
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs...
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register"
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
2013-06-04 Vincent LejeuneR600: Add a test for r183108
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri...
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
2013-06-03 Tom StellardR600/SI: Add support for global loads
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
2013-05-23 Tom StellardR600: Fix R600ControlFlowFinalizer not considering...
2013-05-20 Tom StellardR600: Fix rotr.ll on non-asserts builds
next