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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
test
/
CodeGen
/
R600
/ unaligned-load-store.ll
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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commitdiff
2015-04-08
Tom Stellard
R600/SI: Don't print offset0/offset1 DS operands when...
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commitdiff
2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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2015-02-27
David Blaikie
[opaque pointer type] Add textual IR support for explic...
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commitdiff
2015-02-04
Tom Stellard
R600/SI: Expand misaligned 16-bit memory accesses
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commitdiff
2015-02-04
Tom Stellard
R600/SI: Make more store operations legal
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2015-02-04
Tom Stellard
R600: Don't promote i64 stores to v2i32 during DAG...
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2015-02-02
Tom Stellard
R600/SI: 64-bit and larger memory access must be at...
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2015-02-02
Tom Stellard
R600/SI: Merge two test files
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2015-01-27
Marek Olsak
R600/SI: Enable all tests that pass on VI without changes
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commitdiff
2015-01-14
Matt Arsenault
Implement new way of expanding extloads.
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2015-01-06
Tom Stellard
R600/SI: Add a stub GCNTargetMachine
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2014-11-05
Tom Stellard
R600/SI: Change all instruction assembly names to lower...
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2014-10-10
Matt Arsenault
R600/SI: Change how DS offsets are printed
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2014-10-01
Tom Stellard
R600: Call EmitFunctionHeader() in the AsmPrinter to...
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2014-09-14
Matt Arsenault
R600/SI: Fix broken check lines
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2014-08-22
Tom Stellard
R600/SI: Use READ2/WRITE2 instructions for 64-bit mem...
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2014-07-27
Matt Arsenault
Add alignment value to allowsUnalignedMemoryAccess
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2014-07-26
Matt Arsenault
R600/SI: Fix broken test.
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2014-04-29
Tom Stellard
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
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2013-11-13
Tom Stellard
R600/SI: Add support for private address space load...
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2013-11-12
Matt Arsenault
R600/SI: Change formatting of printed registers.
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2013-10-30
Matt Arsenault
Fix CodeGen for unaligned loads with address spaces
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