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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
lib
/
Target
/
R600
/ R600RegisterInfo.cpp
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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2015-03-11
Eric Christopher
Remove the need to cache the subtarget in the R600...
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2014-06-13
Tom Stellard
R600: Remove AMDIL instruction and register definitions
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2014-06-13
Tom Stellard
R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine...
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2013-11-15
Tom Stellard
R600: Fix scheduling of instructions that use the LDS...
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2013-11-13
Tom Stellard
R600/SI: Add support for private address space load...
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2013-10-22
Tom Stellard
R600: Simplify handling of private address space
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2013-08-14
Tom Stellard
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-05-17
Vincent Lejeune
R600: Use bottom up scheduling algorithm
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2013-02-19
Tom Stellard
R600: Mark all members of the TRegMem register class...
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2013-02-07
Tom Stellard
R600: Consolidate sub register indices.
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2013-02-06
Tom Stellard
R600: Support for indirect addressing v4
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2013-02-05
Tom Stellard
R600: improve inputs/interpolation handling
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2013-01-23
Tom Stellard
R600: rework handling of the constants
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2012-12-11
Tom Stellard
Add R600 backend
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