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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
lib
/
Target
/
R600
/ R600InstrInfo.h
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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2015-06-11
Ahmed Bougacha
[CodeGen] ArrayRef'ize cond/pred in various TII APIs...
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2014-10-09
Eric Christopher
Remove unused argument to CreateTargetScheduleState...
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2014-09-03
Benjamin Kramer
Add override to overriden virtual methods, remove virtu...
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2014-08-13
Benjamin Kramer
Canonicalize header guards into a common format.
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2014-07-20
Matt Arsenault
R600: Remove unused function
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2014-06-17
Tom Stellard
R600: Use LDS and vectors for private memory
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2014-06-13
Tom Stellard
R600: Remove AMDIL instruction and register definitions
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2014-06-13
Tom Stellard
R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine...
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2014-04-29
Craig Topper
[C++11] Add 'override' keywords and remove 'virtual...
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2014-04-28
Craig Topper
[C++] Use 'nullptr'.
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2014-01-24
Alp Toker
Fix known typos
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2013-11-22
Tom Stellard
R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()
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2013-11-15
Tom Stellard
R600: Fix scheduling of instructions that use the LDS...
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2013-11-13
Tom Stellard
R600/SI: Add support for private address space load...
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2013-10-22
Tom Stellard
R600: Simplify handling of private address space
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2013-10-22
Tom Stellard
R600: Remove unused InstrInfo::getMovImmInstr() function
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2013-10-01
Vincent Lejeune
R600: add a pass that merges clauses.
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2013-09-30
Arnold Schwaighofer
IfConverter: Use TargetSchedule for instruction latencies
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2013-09-12
Tom Stellard
R600: Don't use trans slot for instructions that read...
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2013-09-05
Tom Stellard
R600: Add support for local memory atomic add
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2013-09-04
Vincent Lejeune
R600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-08-16
Tom Stellard
R600: Add IsExport bit to TableGen instruction definitions
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2013-07-31
Tom Stellard
Revert "R600: Use SchedModel enum for is{Trans,Vector...
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2013-07-31
Vincent Lejeune
R600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-07-23
Tom Stellard
R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISe...
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2013-06-29
Vincent Lejeune
R600: Support schedule and packetization of trans-only...
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2013-06-29
Vincent Lejeune
R600: Bank Swizzle now display SCL equivalent
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2013-06-28
Tom Stellard
R600: Add local memory support via LDS
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2013-06-28
Tom Stellard
R600: Add support for GROUP_BARRIER instruction
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2013-06-25
Tom Stellard
R600: Use new getNamedOperandIdx function generated...
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2013-06-07
Tom Stellard
R600: Rework subtarget info and remove AMDILDevice...
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2013-06-04
Vincent Lejeune
R600: Const/Neg/Abs can be folded to dot4
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2013-05-17
Vincent Lejeune
R600: Relax some vector constraints on Dot4.
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2013-05-17
Vincent Lejeune
R600: Some factorization
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2013-04-30
Vincent Lejeune
R600: Rework Scheduling to handle difference between...
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2013-04-30
Vincent Lejeune
R600: Add FetchInst bit to instruction defs to denote...
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2013-04-03
Vincent Lejeune
R600: Factorize maximum alu per clause in a single...
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2013-03-14
Vincent Lejeune
R600: Factorize code handling Const Read Port limitation
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2013-02-06
Tom Stellard
R600: Support for indirect addressing v4
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2013-01-02
Chandler Carruth
Resort the #include lines in include/... and lib/....
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2012-12-11
Tom Stellard
Add R600 backend
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