[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.

[oota-llvm.git] / test / MC / Disassembler / Hexagon / alu32_pred.txt

diff --git a/test/MC/Disassembler/Hexagon/alu32_pred.txt b/test/MC/Disassembler/Hexagon/alu32_pred.txt
index c8e31a39fb63fc3a4fb437b3ca105dd1bc65bf2b..c671760e6d3967f6d17277311c50edcca643d23d 100644 (file)
--- a/test/MC/Disassembler/Hexagon/alu32_pred.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_pred.txt
@@ -16,6 +16,12 @@
 0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31)
+0x03 0x40 0x45 0x85 0x70 0xff 0x15 0xfd
+# CHECK: { p3 = r5
+# CHECK-NEXT: if (p3.new) r17:16 = combine(r21, r31) }
+0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd
+# CHECK: { p3 = r5
+# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31) }
 0x71 0xdf 0x15 0xf9
 # CHECK: if (p3) r17 = and(r21, r31)
 0x71 0xdf 0x35 0xf9
@@ -28,6 +34,16 @@
 # CHECK: if (p3) r17 = sxtb(r21)
 0x11 0xe3 0xf5 0x70
 # CHECK: if (p3) r17 = sxth(r21)
+0xb1 0xc2 0x60 0x7e
+# CHECK: { if (p3) r17 = #21 }
+0xb1 0xc2 0xe0 0x7e
+# CHECK: { if (!p3) r17 = #21 }
+0x03 0x40 0x45 0x85 0xb1 0xe2 0x60 0x7e
+# CHECK: { p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = #21 }
+0x03 0x40 0x45 0x85 0xb1 0xe2 0xe0 0x7e
+# CHECK: { p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = #21 }
 0x11 0xe3 0x95 0x70
 # CHECK: if (p3) r17 = zxtb(r21)
 0x11 0xe3 0xd5 0x70