[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.

[oota-llvm.git] / test / MC / Disassembler / Hexagon / alu32_alu.txt

diff --git a/test/MC/Disassembler/Hexagon/alu32_alu.txt b/test/MC/Disassembler/Hexagon/alu32_alu.txt
index 74d4c732eaa492a956d9d66103ada2dab51d9208..4ae3f9693e0f2a32291f701fe6b3a98750ca7e6c 100644 (file)
--- a/test/MC/Disassembler/Hexagon/alu32_alu.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_alu.txt
@@ -30,5 +30,11 @@
 # CHECK: r17.h = #21
 0x15 0xc0 0x31 0x71
 # CHECK: r17.l = #21
+0xf1 0xff 0x5f 0x78
+# CHECK: { r17 = #32767 }
+0xf1 0xff 0xdf 0x78
+# CHECK: { r17 = #-1 }
+0x11 0xc0 0x75 0x70
+# CHECK: { r17 = r21 }
 0x11 0xc0 0xd5 0x70
 # CHECK: r17 = zxth(r21)