Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)

[oota-llvm.git] / test / MC / Disassembler / ARM / neon.txt

diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
index 58fe20eaa275890751c3ec8f8dcaf5fbe1ea0f19..c5dbee3aa89332b3c4d26f9dbb49fd60c4b29cfa 100644 (file)
--- a/test/MC/Disassembler/ARM/neon.txt
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -2243,3 +2243,40 @@
 # CHECK: vld4.16       {d8, d10, d12, d14}, [r4] 
 0x8f 0x81 0x24 0xf4
 # CHECK: vld4.32       {d8, d10, d12, d14}, [r4] 
+
+# rdar://11256967
+0x0f 0x0d 0xa2 0xf4
+# CHECK: vld2.8        {d0[], d1[]}, [r2]      
+0x4f 0x0d 0xa2 0xf4
+# CHECK: vld2.16       {d0[], d1[]}, [r2]      
+0x8f 0x0d 0xa2 0xf4
+# CHECK: vld2.32       {d0[], d1[]}, [r2]      
+0x0d 0x0d 0xa2 0xf4
+# CHECK: vld2.8        {d0[], d1[]}, [r2]!     
+0x4d 0x0d 0xa2 0xf4
+# CHECK: vld2.16       {d0[], d1[]}, [r2]!     
+0x8d 0x0d 0xa2 0xf4
+# CHECK: vld2.32       {d0[], d1[]}, [r2]!     
+0x03 0x0d 0xa2 0xf4
+# CHECK: vld2.8        {d0[], d1[]}, [r2], r3  
+0x43 0x0d 0xa2 0xf4
+# CHECK: vld2.16       {d0[], d1[]}, [r2], r3  
+0x83 0x0d 0xa2 0xf4
+# CHECK: vld2.32       {d0[], d1[]}, [r2], r3  
+0x2f 0x0d 0xa3 0xf4
+# CHECK: vld2.8        {d0[], d2[]}, [r3]      
+0x6f 0x0d 0xa3 0xf4
+# CHECK: vld2.16       {d0[], d2[]}, [r3]      
+0xaf 0x0d 0xa3 0xf4
+# CHECK: vld2.32       {d0[], d2[]}, [r3]      
+0x2d 0x0d 0xa3 0xf4
+# CHECK: vld2.8        {d0[], d2[]}, [r3]!     
+0x6d 0x0d 0xa3 0xf4
+# CHECK: vld2.16       {d0[], d2[]}, [r3]!     
+0xad 0x0d 0xa3 0xf4
+# CHECK: vld2.32       {d0[], d2[]}, [r3]!     
+0x24 0x0d 0xa3 0xf4
+# CHECK: vld2.8        {d0[], d2[]}, [r3], r4  
+0x64 0x0d 0xa3 0xf4
+0xa4 0x0d 0xa3 0xf4
+# CHECK: vld2.32       {d0[], d2[]}, [r3], r4