Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)

instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 2f504b756b1b34c57e76e3e5934c48cd889910cd..f352bffa4465b54c8cb8b0505636f85a044f59fd 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2690,7 +2690,6 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned align = fieldFromInstruction32(Insn, 4, 1);
   unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
-  unsigned pred = fieldFromInstruction32(Insn, 22, 4);
   align *= 2*size;
 
   switch (Inst.getOpcode()) {
@@ -2721,16 +2720,11 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::CreateImm(align));
 
-  if (Rm == 0xD)
-    Inst.addOperand(MCOperand::CreateReg(0));
-  else if (Rm != 0xF) {
+  if (Rm != 0xD && Rm != 0xF) {
     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
-  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
-    return MCDisassembler::Fail;
-
   return S;
 }
 

diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
index 58fe20eaa275890751c3ec8f8dcaf5fbe1ea0f19..c5dbee3aa89332b3c4d26f9dbb49fd60c4b29cfa 100644 (file)
--- a/test/MC/Disassembler/ARM/neon.txt
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -2243,3 +2243,40 @@
 # CHECK: vld4.16       {d8, d10, d12, d14}, [r4] 
 0x8f 0x81 0x24 0xf4
 # CHECK: vld4.32       {d8, d10, d12, d14}, [r4] 
+
+# rdar://11256967
+0x0f 0x0d 0xa2 0xf4
+# CHECK: vld2.8        {d0[], d1[]}, [r2]      
+0x4f 0x0d 0xa2 0xf4
+# CHECK: vld2.16       {d0[], d1[]}, [r2]      
+0x8f 0x0d 0xa2 0xf4
+# CHECK: vld2.32       {d0[], d1[]}, [r2]      
+0x0d 0x0d 0xa2 0xf4
+# CHECK: vld2.8        {d0[], d1[]}, [r2]!     
+0x4d 0x0d 0xa2 0xf4
+# CHECK: vld2.16       {d0[], d1[]}, [r2]!     
+0x8d 0x0d 0xa2 0xf4
+# CHECK: vld2.32       {d0[], d1[]}, [r2]!     
+0x03 0x0d 0xa2 0xf4
+# CHECK: vld2.8        {d0[], d1[]}, [r2], r3  
+0x43 0x0d 0xa2 0xf4
+# CHECK: vld2.16       {d0[], d1[]}, [r2], r3  
+0x83 0x0d 0xa2 0xf4
+# CHECK: vld2.32       {d0[], d1[]}, [r2], r3  
+0x2f 0x0d 0xa3 0xf4
+# CHECK: vld2.8        {d0[], d2[]}, [r3]      
+0x6f 0x0d 0xa3 0xf4
+# CHECK: vld2.16       {d0[], d2[]}, [r3]      
+0xaf 0x0d 0xa3 0xf4
+# CHECK: vld2.32       {d0[], d2[]}, [r3]      
+0x2d 0x0d 0xa3 0xf4
+# CHECK: vld2.8        {d0[], d2[]}, [r3]!     
+0x6d 0x0d 0xa3 0xf4
+# CHECK: vld2.16       {d0[], d2[]}, [r3]!     
+0xad 0x0d 0xa3 0xf4
+# CHECK: vld2.32       {d0[], d2[]}, [r3]!     
+0x24 0x0d 0xa3 0xf4
+# CHECK: vld2.8        {d0[], d2[]}, [r3], r4  
+0x64 0x0d 0xa3 0xf4
+0xa4 0x0d 0xa3 0xf4
+# CHECK: vld2.32       {d0[], d2[]}, [r3], r4  

diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt
index efe7e60ddaed4968e6fcdf6302d6b560190f3d7b..65cd2304149def514ee9dc6a91db7926d4151a6c 100644 (file)
--- a/test/MC/Disassembler/ARM/neont2.txt
+++ b/test/MC/Disassembler/ARM/neont2.txt
@@ -1960,3 +1960,41 @@
 # CHECK: vld4.16       {d8, d10, d12, d14}, [r4] 
 0x24 0xf9 0x8f 0x81
 # CHECK: vld4.32       {d8, d10, d12, d14}, [r4] 
+
+# rdar://11256967
+0xa2 0xf9 0x0f 0x0d
+# CHECK: vld2.8        {d0[], d1[]}, [r2]      
+0xa2 0xf9 0x4f 0x0d
+# CHECK: vld2.16       {d0[], d1[]}, [r2]      
+0xa2 0xf9 0x8f 0x0d
+# CHECK: vld2.32       {d0[], d1[]}, [r2]      
+0xa2 0xf9 0x0d 0x0d
+# CHECK: vld2.8        {d0[], d1[]}, [r2]!     
+0xa2 0xf9 0x4d 0x0d
+# CHECK: vld2.16       {d0[], d1[]}, [r2]!     
+0xa2 0xf9 0x8d 0x0d
+# CHECK: vld2.32       {d0[], d1[]}, [r2]!     
+0xa2 0xf9 0x03 0x0d
+# CHECK: vld2.8        {d0[], d1[]}, [r2], r3  
+0xa2 0xf9 0x43 0x0d
+# CHECK: vld2.16       {d0[], d1[]}, [r2], r3  
+0xa2 0xf9 0x83 0x0d
+# CHECK: vld2.32       {d0[], d1[]}, [r2], r3  
+0xa3 0xf9 0x2f 0x0d
+# CHECK: vld2.8        {d0[], d2[]}, [r3]      
+0xa3 0xf9 0x6f 0x0d
+# CHECK: vld2.16       {d0[], d2[]}, [r3]      
+0xa3 0xf9 0xaf 0x0d
+# CHECK: vld2.32       {d0[], d2[]}, [r3]      
+0xa3 0xf9 0x2d 0x0d
+# CHECK: vld2.8        {d0[], d2[]}, [r3]!     
+0xa3 0xf9 0x6d 0x0d
+# CHECK: vld2.16       {d0[], d2[]}, [r3]!     
+0xa3 0xf9 0xad 0x0d
+# CHECK: vld2.32       {d0[], d2[]}, [r3]!     
+0xa3 0xf9 0x24 0x0d
+# CHECK: vld2.8        {d0[], d2[]}, [r3], r4  
+0xa3 0xf9 0x64 0x0d
+# CHECK: vld2.16       {d0[], d2[]}, [r3], r4  
+0xa3 0xf9 0xa4 0x0d
+# CHECK: vld2.32       {d0[], d2[]}, [r3], r4