CellSPU:

[oota-llvm.git] / test / CodeGen / CellSPU / shift_ops.ll

diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll
index 928e4904b403462585f5218db75d582b0dc6a58a..3c26baa7c7ab705d5a0db162a6ca5010f369e0b1 100644 (file)
--- a/test/CodeGen/CellSPU/shift_ops.ll
+++ b/test/CodeGen/CellSPU/shift_ops.ll
@@ -1,22 +1,20 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep -w shlh      %t1.s | count 9
-; RUN: grep -w shlhi     %t1.s | count 3
-; RUN: grep -w shl       %t1.s | count 9
-; RUN: grep -w shli      %t1.s | count 3
-; RUN: grep -w xshw      %t1.s | count 5
-; RUN: grep -w and       %t1.s | count 5
-; RUN: grep -w andi      %t1.s | count 2
-; RUN: grep -w rotmi     %t1.s | count 2
-; RUN: grep -w rotqmbyi  %t1.s | count 1
-; RUN: grep -w rotqmbii  %t1.s | count 2
-; RUN: grep -w rotqmby   %t1.s | count 1
-; RUN: grep -w rotqmbi   %t1.s | count 1
-; RUN: grep -w rotqbyi   %t1.s | count 1
-; RUN: grep -w rotqbii   %t1.s | count 2
-; RUN: grep -w rotqbybi  %t1.s | count 1
-; RUN: grep -w sfi       %t1.s | count 3
-
-; XFAIL: alpha|linux|sparc|ia64|arm
+; RUN: grep {shlh      }  %t1.s | count 9
+; RUN: grep {shlhi     }  %t1.s | count 3
+; RUN: grep {shl       }  %t1.s | count 9
+; RUN: grep {shli      }  %t1.s | count 3
+; RUN: grep {xshw      }  %t1.s | count 5
+; RUN: grep {and       }  %t1.s | count 5
+; RUN: grep {andi      }  %t1.s | count 2
+; RUN: grep {rotmi     }  %t1.s | count 2
+; RUN: grep {rotqmbyi  }  %t1.s | count 1
+; RUN: grep {rotqmbii  }  %t1.s | count 2
+; RUN: grep {rotqmby   }  %t1.s | count 1
+; RUN: grep {rotqmbi   }  %t1.s | count 1
+; RUN: grep {rotqbyi   }  %t1.s | count 1
+; RUN: grep {rotqbii   }  %t1.s | count 2
+; RUN: grep {rotqbybi  }  %t1.s | count 1
+; RUN: grep {sfi       }  %t1.s | count 3
 
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
@@ -277,3 +275,9 @@ define i64 @ashr_i64_3(i64 %arg1, i32 %shift) {
        %2 = ashr i64 %arg1, %1
        ret i64 %2
 }
+
+define i32 @hi32_i64(i64 %arg) {
+       %1 = lshr i64 %arg, 32
+       %2 = trunc i64 %1 to i32
+       ret i32 %2
+}