//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Constant.h"
#include "llvm/DerivedTypes.h"
using namespace llvm;
-TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
- unsigned numOpcodes)
- : desc(Desc), NumOpcodes(numOpcodes) {
-}
-
-TargetInstrInfo::~TargetInstrInfo() {
-}
-
/// findTiedToSrcOperand - Returns the operand that is tied to the specified
/// dest operand. Returns -1 if there isn't one.
-int
-TargetInstrInfo::findTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const {
- for (unsigned i = 0, e = getNumOperands(Opc); i != e; ++i) {
+int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
if (i == OpNum)
continue;
- int ti = getOperandConstraint(Opc, i, TIED_TO);
- if (ti == (int)OpNum)
+ if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
return i;
}
return -1;
}
-// commuteInstruction - The default implementation of this method just exchanges
-// operand 1 and 2.
-MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
- assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
- "This only knows how to commute register operands so far");
- unsigned Reg1 = MI->getOperand(1).getReg();
- unsigned Reg2 = MI->getOperand(2).getReg();
- bool Reg1IsKill = MI->getOperand(1).isKill();
- bool Reg2IsKill = MI->getOperand(2).isKill();
- MI->getOperand(2).setReg(Reg1);
- MI->getOperand(1).setReg(Reg2);
- if (Reg1IsKill)
- MI->getOperand(2).setIsKill();
- else
- MI->getOperand(2).unsetIsKill();
- if (Reg2IsKill)
- MI->getOperand(1).setIsKill();
- else
- MI->getOperand(1).unsetIsKill();
- return MI;
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
+ unsigned numOpcodes)
+ : Descriptors(Desc), NumOpcodes(numOpcodes) {
+}
+
+TargetInstrInfo::~TargetInstrInfo() {
+}
+
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isTerminator()) return false;
+
+ // Conditional branch is a special case.
+ if (TID.isBranch() && !TID.isBarrier())
+ return true;
+ if (!TID.isPredicable())
+ return true;
+ return !isPredicated(MI);
}