For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 2fdcf8b660c9dadf1860b2bb0a12083c65a23a82..a37e9e6bd0739a1db59bcfa99a7bf43034fb088e 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -407,6 +407,13 @@ public:
     return false;
   }
 
+  /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
+  /// live interval splitting pass should ignore barriers of the specified
+  /// register class.
+  virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{
+    return true;
+  }
+
   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
   /// values.
   virtual const TargetRegisterClass *getPointerRegClass() const {
@@ -425,7 +432,6 @@ public:
   /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
   /// 
   virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
-
 };
 
 /// TargetInstrInfoImpl - This is the default implementation of

diff --git a/lib/CodeGen/PreAllocSplitting.cpp b/lib/CodeGen/PreAllocSplitting.cpp
index 547c528ca2397463c417b49845bc90d8333bdeaf..33e3e8054ce678b48cce91ff1326643dbb4e9e4c 100644 (file)
--- a/lib/CodeGen/PreAllocSplitting.cpp
+++ b/lib/CodeGen/PreAllocSplitting.cpp
@@ -659,6 +659,8 @@ PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs) {
   // by the current barrier.
   SmallVector<LiveInterval*, 8> Intervals;
   for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
+    if (TII->IgnoreRegisterClassBarriers(*RC))
+      continue;
     std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
     for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
       unsigned Reg = VRs[i];

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 04f10c008851e019deccf12ff82e00fba0698950..c08fdd8f206a2be99f7ca04d271cbf840ef918fd 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -2411,6 +2411,14 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
   return false;
 }
 
+bool X86InstrInfo::
+IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
+  // FIXME: Ignore bariers of x87 stack registers for now. We can't
+  // allow any loads of these registers before FpGet_ST0_80.
+  return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
+    RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
+}
+
 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
   if (Subtarget->is64Bit())

diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 17be894a8872321db9adc6a29624b0f2df213cee..dc76f3ec1f9cafa20e2666d3b326dda598132f59 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -405,6 +405,11 @@ public:
   virtual
   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 
+  /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
+  /// live interval splitting pass should ignore barriers of the specified
+  /// register class.
+  bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
+
   const TargetRegisterClass *getPointerRegClass() const;
 
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the

diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index 93e8613b97b2ff7bc8725e9e421b77197c00cade..25d7b07bad14db8b36a88c37358a85788fc85fef 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -94,6 +94,10 @@ public:
 
   /// Code Generation virtual methods...
   /// 
+
+  /// getCrossCopyRegClass - Returns a legal register class to copy a register
+  /// in the specified class to or from. Returns NULL if it is possible to copy
+  /// between a two registers of the specified class.
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const;
 

diff --git a/test/CodeGen/X86/pre-split7.ll b/test/CodeGen/X86/pre-split7.ll
new file mode 100644 (file)
index 0000000..7f7b933
--- /dev/null
+++ b/test/CodeGen/X86/pre-split7.ll
@@ -0,0 +1,34 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
+
+@object_distance = external global double, align 8             ; <double*> [#uses=1]
+@axis_slope_angle = external global double, align 8            ; <double*> [#uses=1]
+@current_surfaces.b = external global i1               ; <i1*> [#uses=1]
+
+declare double @sin(double) nounwind readonly
+
+declare double @asin(double) nounwind readonly
+
+declare double @tan(double) nounwind readonly
+
+define fastcc void @trace_line(i32 %line) nounwind {
+entry:
+       %.b3 = load i1* @current_surfaces.b             ; <i1> [#uses=1]
+       br i1 %.b3, label %bb, label %return
+
+bb:            ; preds = %bb, %entry
+       %0 = tail call double @asin(double 0.000000e+00) nounwind readonly              ; <double> [#uses=1]
+       %1 = add double 0.000000e+00, %0                ; <double> [#uses=2]
+       %2 = tail call double @asin(double 0.000000e+00) nounwind readonly              ; <double> [#uses=1]
+       %3 = sub double %1, %2          ; <double> [#uses=2]
+       store double %3, double* @axis_slope_angle, align 8
+       %4 = fdiv double %1, 2.000000e+00               ; <double> [#uses=1]
+       %5 = tail call double @sin(double %4) nounwind readonly         ; <double> [#uses=1]
+       %6 = mul double 0.000000e+00, %5                ; <double> [#uses=1]
+       %7 = tail call double @tan(double %3) nounwind readonly         ; <double> [#uses=0]
+       %8 = add double 0.000000e+00, %6                ; <double> [#uses=1]
+       store double %8, double* @object_distance, align 8
+       br label %bb
+
+return:                ; preds = %entry
+       ret void
+}