#include "SPUHazardRecognizers.h"
#include "SPUFrameInfo.h"
#include "SPURegisterNames.h"
+#include "SPUTargetMachine.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Constants.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Compiler.h"
-#include <queue>
-#include <set>
using namespace llvm;
bool
isI64IntS10Immediate(ConstantSDNode *CN)
{
- return isS10Constant(CN->getSignExtended());
+ return isS10Constant(CN->getSExtValue());
}
//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
bool
isI32IntS10Immediate(ConstantSDNode *CN)
{
- return isS10Constant(CN->getSignExtended());
+ return isS10Constant(CN->getSExtValue());
}
#if 0
bool
isI32IntU10Immediate(ConstantSDNode *CN)
{
- return isU10Constant(CN->getSignExtended());
+ return isU10Constant(CN->getSExtValue());
}
//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
bool
isI16IntS10Immediate(ConstantSDNode *CN)
{
- return isS10Constant(CN->getSignExtended());
+ return isS10Constant(CN->getSExtValue());
}
//! SDNode predicate for i16 sign-extended, 10-bit immediate values
bool
isI16IntU10Immediate(ConstantSDNode *CN)
{
- return isU10Constant((short) CN->getValue());
+ return isU10Constant((short) CN->getZExtValue());
}
//! SDNode predicate for i16 sign-extended, 10-bit immediate values
isIntS16Immediate(ConstantSDNode *CN, short &Imm)
{
MVT vt = CN->getValueType(0);
- Imm = (short) CN->getValue();
+ Imm = (short) CN->getZExtValue();
if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
return true;
} else if (vt == MVT::i32) {
- int32_t i_val = (int32_t) CN->getValue();
+ int32_t i_val = (int32_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
} else {
- int64_t i_val = (int64_t) CN->getValue();
+ int64_t i_val = (int64_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
}
}
bool
- isHighLow(const SDOperand &Op)
+ isHighLow(const SDValue &Op)
{
return (Op.getOpcode() == SPUISD::IndirectAddr
&& ((Op.getOperand(0).getOpcode() == SPUISD::Hi
MVT VT;
unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
bool ldresult_imm; /// LDRESULT instruction requires immediate?
- int prefslot_byte; /// Byte offset of the "preferred" slot
+ unsigned lrinst; /// LR instruction
};
const valtype_map_s valtype_map[] = {
- { MVT::i1, 0, false, 3 },
- { MVT::i8, SPU::ORBIr8, true, 3 },
- { MVT::i16, SPU::ORHIr16, true, 2 },
- { MVT::i32, SPU::ORIr32, true, 0 },
- { MVT::i64, SPU::ORr64, false, 0 },
- { MVT::f32, SPU::ORf32, false, 0 },
- { MVT::f64, SPU::ORf64, false, 0 },
+ { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
+ { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
+ { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
+ { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
+ { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
+ { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
// vector types... (sigh!)
- { MVT::v16i8, 0, false, 0 },
- { MVT::v8i16, 0, false, 0 },
- { MVT::v4i32, 0, false, 0 },
- { MVT::v2i64, 0, false, 0 },
- { MVT::v4f32, 0, false, 0 },
- { MVT::v2f64, 0, false, 0 }
+ { MVT::v16i8, 0, false, SPU::LRv16i8 },
+ { MVT::v8i16, 0, false, SPU::LRv8i16 },
+ { MVT::v4i32, 0, false, SPU::LRv4i32 },
+ { MVT::v2i64, 0, false, SPU::LRv2i64 },
+ { MVT::v4f32, 0, false, SPU::LRv4f32 },
+ { MVT::v2f64, 0, false, SPU::LRv2f64 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
unsigned GlobalBaseReg;
public:
- SPUDAGToDAGISel(SPUTargetMachine &tm) :
- SelectionDAGISel(*tm.getTargetLowering()),
+ explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
+ SelectionDAGISel(tm),
TM(tm),
SPUtli(*tm.getTargetLowering())
{}
-
+
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
GlobalBaseReg = 0;
SelectionDAGISel::runOnFunction(Fn);
return true;
}
-
+
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
- inline SDOperand getI32Imm(uint32_t Imm) {
+ inline SDValue getI32Imm(uint32_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
- inline SDOperand getI64Imm(uint64_t Imm) {
+ inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
-
+
/// getSmallIPtrImm - Return a target constant of pointer type.
- inline SDOperand getSmallIPtrImm(unsigned Imm) {
+ inline SDValue getSmallIPtrImm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
+ }
+
+ SDNode *emitBuildVector(SDValue build_vec) {
+ MVT vecVT = build_vec.getValueType();
+ SDNode *bvNode = build_vec.getNode();
+ bool canBeSelected = false;
+
+ // Check to see if this vector can be represented as a CellSPU immediate
+ // constant.
+ if (vecVT == MVT::v8i16) {
+ if (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0) {
+ canBeSelected = true;
+ }
+ } else if (vecVT == MVT::v4i32) {
+ if ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0)
+ || (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0)
+ || (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0)
+ || (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0)) {
+ canBeSelected = true;
+ }
+ } else if (vecVT == MVT::v2i64) {
+ if ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)
+ || (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)
+ || (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)) {
+ canBeSelected = true;
+ }
+ }
+
+ if (canBeSelected) {
+ return Select(build_vec);
+ }
+
+ // No, need to emit a constant pool spill:
+ std::vector<Constant*> CV;
+
+ for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
+ ConstantSDNode *V = dyn_cast<ConstantSDNode > (build_vec.getOperand(i));
+ CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
+ }
+
+ Constant *CP = ConstantVector::get(CV);
+ SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
+ unsigned Alignment = 1 << cast<ConstantPoolSDNode > (CPIdx)->getAlignment();
+ SDValue CGPoolOffset =
+ SPU::LowerConstantPool(CPIdx, *CurDAG,
+ SPUtli.getSPUTargetMachine());
+ return SelectCode(CurDAG->getLoad(build_vec.getValueType(),
+ CurDAG->getEntryNode(), CGPoolOffset,
+ PseudoSourceValue::getConstantPool(), 0,
+ false, Alignment));
}
/// Select - Convert the specified operand from a target-independent to a
/// target-specific node if it hasn't already been changed.
- SDNode *Select(SDOperand Op);
+ SDNode *Select(SDValue Op);
+
+ //! Emit the instruction sequence for i64 shl
+ SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
+
+ //! Emit the instruction sequence for i64 srl
+ SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
+
+ //! Emit the instruction sequence for i64 sra
+ SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
+
+ //! Emit the necessary sequence for loading i64 constants:
+ SDNode *SelectI64Constant(SDValue &Op, MVT OpVT);
//! Returns true if the address N is an A-form (local store) address
- bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index);
+ bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index);
//! D-form address predicate
- bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index);
+ bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index);
/// Alternate D-form address using i7 offset predicate
- bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base);
+ bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base);
/// D-form address selection workhorse
- bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base, int minOffset, int maxOffset);
+ bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base, int minOffset, int maxOffset);
//! Address predicate if N can be expressed as an indexed [r+r] operation.
- bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index);
+ bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDOperand> &OutOps,
- SelectionDAG &DAG) {
- SDOperand Op0, Op1;
+ std::vector<SDValue> &OutOps) {
+ SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
- if (!SelectDFormAddr(Op, Op, Op0, Op1)
+ if (!SelectDFormAddr(Op, Op, Op0, Op1)
&& !SelectAFormAddr(Op, Op, Op0, Op1))
SelectXFormAddr(Op, Op, Op0, Op1);
break;
if (!SelectDFormAddr(Op, Op, Op0, Op1)
&& !SelectAFormAddr(Op, Op, Op0, Op1)) {
Op0 = Op;
- AddToISelQueue(Op0); // r+0.
Op1 = getSmallIPtrImm(0);
}
break;
#endif
break;
}
-
+
OutOps.push_back(Op0);
OutOps.push_back(Op1);
return false;
}
- /// InstructionSelectBasicBlock - This callback is invoked by
+ /// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+ virtual void InstructionSelect();
virtual const char *getPassName() const {
return "Cell SPU DAG->DAG Pattern Instruction Selection";
- }
-
+ }
+
/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
/// this target when scheduling the DAG.
- virtual HazardRecognizer *CreateTargetHazardRecognizer() {
- const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
+ virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
+ const TargetInstrInfo *II = TM.getInstrInfo();
assert(II && "No InstrInfo?");
- return new SPUHazardRecognizer(*II);
+ return new SPUHazardRecognizer(*II);
}
// Include the pieces autogenerated from the target description.
}
-/// InstructionSelectBasicBlock - This callback is invoked by
+/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void
-SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
+SPUDAGToDAGISel::InstructionSelect()
{
DEBUG(BB->dump());
// Select target instructions for the DAG.
- DAG.setRoot(SelectRoot(DAG.getRoot()));
- DAG.RemoveDeadNodes();
-
- // Emit machine code to BB.
- ScheduleAndEmitDAG(DAG);
+ SelectRoot(*CurDAG);
+ CurDAG->RemoveDeadNodes();
}
/*!
\arg Index The base address index
*/
bool
-SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
+SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
// These match the addr256k operand type:
MVT OffsVT = MVT::i16;
- SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
+ SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
case ISD::Constant:
abort();
/*NOTREACHED*/
- case SPUISD::AFormAddr:
+ case SPUISD::AFormAddr:
// Just load from memory if there's only a single use of the location,
// otherwise, this will get handled below with D-form offset addresses
if (N.hasOneUse()) {
- SDOperand Op0 = N.getOperand(0);
+ SDValue Op0 = N.getOperand(0);
switch (Op0.getOpcode()) {
case ISD::TargetConstantPool:
case ISD::TargetJumpTable:
return false;
}
-bool
-SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
- SDOperand &Base) {
+bool
+SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
+ SDValue &Base) {
const int minDForm2Offset = -(1 << 7);
const int maxDForm2Offset = (1 << 7) - 1;
return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
displacement, [r+I10] (D-form address).
\return true if \a N is a D-form address with \a Base and \a Index set
- to non-empty SDOperand instances.
+ to non-empty SDValue instances.
*/
bool
-SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
+SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
return DFormAddressPredicate(Op, N, Base, Index,
- SPUFrameInfo::minFrameOffset(),
- SPUFrameInfo::maxFrameOffset());
+ SPUFrameInfo::minFrameOffset(),
+ SPUFrameInfo::maxFrameOffset());
}
bool
-SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index, int minOffset,
+SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index, int minOffset,
int maxOffset) {
unsigned Opc = N.getOpcode();
MVT PtrTy = SPUtli.getPointerTy();
}
} else if (Opc == ISD::ADD) {
// Generated by getelementptr
- const SDOperand Op0 = N.getOperand(0);
- const SDOperand Op1 = N.getOperand(1);
+ const SDValue Op0 = N.getOperand(0);
+ const SDValue Op1 = N.getOperand(1);
if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
|| (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
} else if (Op1.getOpcode() == ISD::Constant
|| Op1.getOpcode() == ISD::TargetConstant) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
- int32_t offset = int32_t(CN->getSignExtended());
+ int32_t offset = int32_t(CN->getSExtValue());
if (Op0.getOpcode() == ISD::FrameIndex) {
FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
} else if (Op0.getOpcode() == ISD::Constant
|| Op0.getOpcode() == ISD::TargetConstant) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
- int32_t offset = int32_t(CN->getSignExtended());
+ int32_t offset = int32_t(CN->getSExtValue());
if (Op1.getOpcode() == ISD::FrameIndex) {
FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
}
} else if (Opc == SPUISD::IndirectAddr) {
// Indirect with constant offset -> D-Form address
- const SDOperand Op0 = N.getOperand(0);
- const SDOperand Op1 = N.getOperand(1);
+ const SDValue Op0 = N.getOperand(0);
+ const SDValue Op1 = N.getOperand(1);
if (Op0.getOpcode() == SPUISD::Hi
&& Op1.getOpcode() == SPUISD::Lo) {
return true;
} else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
int32_t offset = 0;
- SDOperand idxOp;
+ SDValue idxOp;
if (isa<ConstantSDNode>(Op1)) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
- offset = int32_t(CN->getSignExtended());
+ offset = int32_t(CN->getSExtValue());
idxOp = Op0;
} else if (isa<ConstantSDNode>(Op0)) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
- offset = int32_t(CN->getSignExtended());
+ offset = int32_t(CN->getSExtValue());
idxOp = Op1;
- }
+ }
if (offset >= minOffset && offset <= maxOffset) {
Base = CurDAG->getTargetConstant(offset, PtrTy);
Base = CurDAG->getTargetConstant(0, N.getValueType());
Index = N;
return true;
+ } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
+ unsigned OpOpc = Op.getOpcode();
+
+ if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
+ // Direct load/store without getelementptr
+ SDValue Addr, Offs;
+
+ // Get the register from CopyFromReg
+ if (Opc == ISD::CopyFromReg)
+ Addr = N.getOperand(1);
+ else
+ Addr = N; // Register
+
+ Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
+
+ if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
+ if (Offs.getOpcode() == ISD::UNDEF)
+ Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
+
+ Base = Offs;
+ Index = Addr;
+ return true;
+ }
+ } else {
+ /* If otherwise unadorned, default to D-form address with 0 offset: */
+ if (Opc == ISD::CopyFromReg) {
+ Index = N.getOperand(1);
+ } else {
+ Index = N;
+ }
+
+ Base = CurDAG->getTargetConstant(0, Index.getValueType());
+ return true;
+ }
}
+
return false;
}
\arg Base The base pointer operand
\arg Index The offset/index operand
- If the address \a N can be expressed as a [r + s10imm] address, returns false.
- Otherwise, creates two operands, Base and Index that will become the [r+r]
- address.
+ If the address \a N can be expressed as an A-form or D-form address, returns
+ false. Otherwise, creates two operands, Base and Index that will become the
+ (r)(r) X-form address.
*/
bool
-SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
- SDOperand &Index) {
- if (SelectAFormAddr(Op, N, Base, Index)
- || SelectDFormAddr(Op, N, Base, Index))
- return false;
+SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
+ SDValue &Index) {
+ if (!SelectAFormAddr(Op, N, Base, Index)
+ && !SelectDFormAddr(Op, N, Base, Index)) {
+ // If the address is neither A-form or D-form, punt and use an X-form
+ // address:
+ Base = N.getOperand(1);
+ Index = N.getOperand(0);
+ return true;
+ }
- // All else fails, punt and use an X-form address:
- Base = N.getOperand(0);
- Index = N.getOperand(1);
- return true;
+ return false;
}
//! Convert the operand from a target-independent to a target-specific node
/*!
*/
SDNode *
-SPUDAGToDAGISel::Select(SDOperand Op) {
- SDNode *N = Op.Val;
+SPUDAGToDAGISel::Select(SDValue Op) {
+ SDNode *N = Op.getNode();
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
MVT OpVT = Op.getValueType();
- SDOperand Ops[8];
+ SDValue Ops[8];
- if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
+ if (N->isMachineOpcode()) {
return NULL; // Already selected.
- } else if (Opc == ISD::FrameIndex) {
- // Selects to (add $sp, FI * stackSlotSize)
- int FI =
- SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
- MVT PtrVT = SPUtli.getPointerTy();
-
- // Adjust stack slot to actual offset in frame:
- if (isS10Constant(FI)) {
- DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
- << FI
- << "\n");
+ }
+
+ if (Opc == ISD::FrameIndex) {
+ int FI = cast<FrameIndexSDNode>(N)->getIndex();
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
+ SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
+
+ if (FI < 128) {
NewOpc = SPU::AIr32;
- Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
- Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
+ Ops[0] = TFI;
+ Ops[1] = Imm0;
n_ops = 2;
} else {
- DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
- << FI
- << "\n");
NewOpc = SPU::Ar32;
- Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
- Ops[1] = CurDAG->getConstant(FI, PtrVT);
+ Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
+ Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, Op.getValueType(),
+ TFI, Imm0), 0);
n_ops = 2;
+ }
+ } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
+ // Catch the i64 constants that end up here. Note: The backend doesn't
+ // attempt to legalize the constant (it's useless because DAGCombiner
+ // will insert 64-bit constants and we can't stop it).
+ return SelectI64Constant(Op, OpVT);
+ } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
+ && OpVT == MVT::i64) {
+ SDValue Op0 = Op.getOperand(0);
+ MVT Op0VT = Op0.getValueType();
+ MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
+ MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ SDValue shufMask;
+
+ switch (Op0VT.getSimpleVT()) {
+ default:
+ cerr << "CellSPU Select: Unhandled zero/any extend MVT\n";
+ abort();
+ /*NOTREACHED*/
+ break;
+ case MVT::i32:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x00010203, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x08090a0b, MVT::i32));
+ break;
- AddToISelQueue(Ops[1]);
- }
- } else if (Opc == ISD::ZERO_EXTEND) {
- // (zero_extend:i16 (and:i8 <arg>, <const>))
- const SDOperand &Op1 = N->getOperand(0);
-
- if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
- if (Op1.getOpcode() == ISD::AND) {
- // Fold this into a single ANDHI. This is often seen in expansions of i1
- // to i8, then i8 to i16 in logical/branching operations.
- DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
- "<arg>, <const>))\n");
- NewOpc = SPU::ANDHIi8i16;
- Ops[0] = Op1.getOperand(0);
- Ops[1] = Op1.getOperand(1);
- n_ops = 2;
+ case MVT::i16:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80800203, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80800a0b, MVT::i32));
+ break;
+
+ case MVT::i8:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80808003, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x8080800b, MVT::i32));
+ break;
+ }
+
+ SDNode *shufMaskLoad = emitBuildVector(shufMask);
+ SDNode *PromoteScalar =
+ SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0));
+
+ SDValue zextShuffle =
+ CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
+ SDValue(PromoteScalar, 0),
+ SDValue(PromoteScalar, 0),
+ SDValue(shufMaskLoad, 0));
+
+ // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
+ // re-use it in the VEC2PREFSLOT selection without needing to explicitly
+ // call SelectCode (it's already done for us.)
+ SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, OpVecVT, zextShuffle));
+ return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, OpVT,
+ zextShuffle));
+ } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ SDNode *CGLoad =
+ emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
+
+ return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT,
+ Op.getOperand(0), Op.getOperand(1),
+ SDValue(CGLoad, 0)));
+ } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ SDNode *CGLoad =
+ emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG));
+
+ return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT,
+ Op.getOperand(0), Op.getOperand(1),
+ SDValue(CGLoad, 0)));
+ } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ SDNode *CGLoad =
+ emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
+
+ return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT,
+ Op.getOperand(0), Op.getOperand(1),
+ SDValue(CGLoad, 0)));
+ } else if (Opc == ISD::TRUNCATE) {
+ SDValue Op0 = Op.getOperand(0);
+ if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
+ && OpVT == MVT::i32
+ && Op0.getValueType() == MVT::i64) {
+ // Catch the (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32 to
+ // take advantage of the fact that the upper 32 bits are in the
+ // i32 preferred slot and avoid all kinds of other shuffle gymnastics:
+ ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
+ if (CN != 0) {
+ unsigned shift_amt = unsigned(CN->getZExtValue());
+
+ if (shift_amt >= 32) {
+ SDNode *hi32 =
+ CurDAG->getTargetNode(SPU::ORr32_r64, OpVT, Op0.getOperand(0));
+
+ shift_amt -= 32;
+ if (shift_amt > 0) {
+ // Take care of the additional shift, if present:
+ SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
+ unsigned Opc = SPU::ROTMAIr32_i32;
+
+ if (Op0.getOpcode() == ISD::SRL)
+ Opc = SPU::ROTMr32;
+
+ hi32 = CurDAG->getTargetNode(Opc, OpVT, SDValue(hi32, 0), shift);
+ }
+
+ return hi32;
+ }
}
}
+ } else if (Opc == ISD::SHL) {
+ if (OpVT == MVT::i64) {
+ return SelectSHLi64(Op, OpVT);
+ }
+ } else if (Opc == ISD::SRL) {
+ if (OpVT == MVT::i64) {
+ return SelectSRLi64(Op, OpVT);
+ }
+ } else if (Opc == ISD::SRA) {
+ if (OpVT == MVT::i64) {
+ return SelectSRAi64(Op, OpVT);
+ }
} else if (Opc == SPUISD::LDRESULT) {
// Custom select instructions for LDRESULT
MVT VT = N->getValueType(0);
- SDOperand Arg = N->getOperand(0);
- SDOperand Chain = N->getOperand(1);
+ SDValue Arg = N->getOperand(0);
+ SDValue Chain = N->getOperand(1);
SDNode *Result;
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
abort();
}
- AddToISelQueue(Arg);
Opc = vtm->ldresult_ins;
if (vtm->ldresult_imm) {
- SDOperand Zero = CurDAG->getTargetConstant(0, VT);
+ SDValue Zero = CurDAG->getTargetConstant(0, VT);
- AddToISelQueue(Zero);
Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
} else {
- Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
+ Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain);
}
- Chain = SDOperand(Result, 1);
- AddToISelQueue(Chain);
-
return Result;
} else if (Opc == SPUISD::IndirectAddr) {
- SDOperand Op0 = Op.getOperand(0);
- if (Op0.getOpcode() == SPUISD::LDRESULT) {
- /* || Op0.getOpcode() == SPUISD::AFormAddr) */
- // (IndirectAddr (LDRESULT, imm))
- SDOperand Op1 = Op.getOperand(1);
- MVT VT = Op.getValueType();
-
- DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
- DEBUG(Op.getOperand(0).Val->dump(CurDAG));
- DEBUG(cerr << "\nOp1 = ");
- DEBUG(Op.getOperand(1).Val->dump(CurDAG));
- DEBUG(cerr << "\n");
-
+ // Look at the operands: SelectCode() will catch the cases that aren't
+ // specifically handled here.
+ //
+ // SPUInstrInfo catches the following patterns:
+ // (SPUindirect (SPUhi ...), (SPUlo ...))
+ // (SPUindirect $sp, imm)
+ MVT VT = Op.getValueType();
+ SDValue Op0 = N->getOperand(0);
+ SDValue Op1 = N->getOperand(1);
+ RegisterSDNode *RN;
+
+ if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
+ || (Op0.getOpcode() == ISD::Register
+ && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
+ && RN->getReg() != SPU::R1))) {
+ NewOpc = SPU::Ar32;
if (Op1.getOpcode() == ISD::Constant) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
- Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
+ Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
- AddToISelQueue(Op0);
- AddToISelQueue(Op1);
- Ops[0] = Op0;
- Ops[1] = Op1;
- n_ops = 2;
}
+ Ops[0] = Op0;
+ Ops[1] = Op1;
+ n_ops = 2;
}
}
-
+
if (n_ops > 0) {
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
return SelectCode(Op);
}
-/// createPPCISelDag - This pass converts a legalized DAG into a
+/*!
+ * Emit the instruction sequence for i64 left shifts. The basic algorithm
+ * is to fill the bottom two word slots with zeros so that zeros are shifted
+ * in as the entire quadword is shifted left.
+ *
+ * \note This code could also be used to implement v2i64 shl.
+ *
+ * @param Op The shl operand
+ * @param OpVT Op's machine value value type (doesn't need to be passed, but
+ * makes life easier.)
+ * @return The SDNode with the entire instruction sequence
+ */
+SDNode *
+SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
+ SDValue Op0 = Op.getOperand(0);
+ MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ SDValue ShiftAmt = Op.getOperand(1);
+ MVT ShiftAmtVT = ShiftAmt.getValueType();
+ SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
+ SDValue SelMaskVal;
+
+ VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
+ SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
+ SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, SelMaskVal);
+ ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, VecVT,
+ CurDAG->getTargetConstant(0, OpVT));
+ VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
+ SDValue(ZeroFill, 0),
+ SDValue(VecOp0, 0),
+ SDValue(SelMask, 0));
+
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
+ unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
+ unsigned bits = unsigned(CN->getZExtValue()) & 7;
+
+ if (bytes > 0) {
+ Shift =
+ CurDAG->getTargetNode(SPU::SHLQBYIv2i64, VecVT,
+ SDValue(VecOp0, 0),
+ CurDAG->getTargetConstant(bytes, ShiftAmtVT));
+ }
+
+ if (bits > 0) {
+ Shift =
+ CurDAG->getTargetNode(SPU::SHLQBIIv2i64, VecVT,
+ SDValue((Shift != 0 ? Shift : VecOp0), 0),
+ CurDAG->getTargetConstant(bits, ShiftAmtVT));
+ }
+ } else {
+ SDNode *Bytes =
+ CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
+ ShiftAmt,
+ CurDAG->getTargetConstant(3, ShiftAmtVT));
+ SDNode *Bits =
+ CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
+ ShiftAmt,
+ CurDAG->getTargetConstant(7, ShiftAmtVT));
+ Shift =
+ CurDAG->getTargetNode(SPU::SHLQBYv2i64, VecVT,
+ SDValue(VecOp0, 0), SDValue(Bytes, 0));
+ Shift =
+ CurDAG->getTargetNode(SPU::SHLQBIv2i64, VecVT,
+ SDValue(Shift, 0), SDValue(Bits, 0));
+ }
+
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
+}
+
+/*!
+ * Emit the instruction sequence for i64 logical right shifts.
+ *
+ * @param Op The shl operand
+ * @param OpVT Op's machine value value type (doesn't need to be passed, but
+ * makes life easier.)
+ * @return The SDNode with the entire instruction sequence
+ */
+SDNode *
+SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
+ SDValue Op0 = Op.getOperand(0);
+ MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ SDValue ShiftAmt = Op.getOperand(1);
+ MVT ShiftAmtVT = ShiftAmt.getValueType();
+ SDNode *VecOp0, *Shift = 0;
+
+ VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
+
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
+ unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
+ unsigned bits = unsigned(CN->getZExtValue()) & 7;
+
+ if (bytes > 0) {
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, VecVT,
+ SDValue(VecOp0, 0),
+ CurDAG->getTargetConstant(bytes, ShiftAmtVT));
+ }
+
+ if (bits > 0) {
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, VecVT,
+ SDValue((Shift != 0 ? Shift : VecOp0), 0),
+ CurDAG->getTargetConstant(bits, ShiftAmtVT));
+ }
+ } else {
+ SDNode *Bytes =
+ CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
+ ShiftAmt,
+ CurDAG->getTargetConstant(3, ShiftAmtVT));
+ SDNode *Bits =
+ CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
+ ShiftAmt,
+ CurDAG->getTargetConstant(7, ShiftAmtVT));
+
+ // Ensure that the shift amounts are negated!
+ Bytes = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
+ SDValue(Bytes, 0),
+ CurDAG->getTargetConstant(0, ShiftAmtVT));
+
+ Bits = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
+ SDValue(Bits, 0),
+ CurDAG->getTargetConstant(0, ShiftAmtVT));
+
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQMBYv2i64, VecVT,
+ SDValue(VecOp0, 0), SDValue(Bytes, 0));
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQMBIv2i64, VecVT,
+ SDValue(Shift, 0), SDValue(Bits, 0));
+ }
+
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
+}
+
+/*!
+ * Emit the instruction sequence for i64 arithmetic right shifts.
+ *
+ * @param Op The shl operand
+ * @param OpVT Op's machine value value type (doesn't need to be passed, but
+ * makes life easier.)
+ * @return The SDNode with the entire instruction sequence
+ */
+SDNode *
+SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
+ // Promote Op0 to vector
+ MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ SDValue ShiftAmt = Op.getOperand(1);
+ MVT ShiftAmtVT = ShiftAmt.getValueType();
+
+ SDNode *VecOp0 =
+ CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op.getOperand(0));
+
+ SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
+ SDNode *SignRot =
+ CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, MVT::v2i64,
+ SDValue(VecOp0, 0), SignRotAmt);
+ SDNode *UpperHalfSign =
+ CurDAG->getTargetNode(SPU::ORi32_v4i32, MVT::i32, SDValue(SignRot, 0));
+
+ SDNode *UpperHalfSignMask =
+ CurDAG->getTargetNode(SPU::FSM64r32, VecVT, SDValue(UpperHalfSign, 0));
+ SDNode *UpperLowerMask =
+ CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT,
+ CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
+ SDNode *UpperLowerSelect =
+ CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
+ SDValue(UpperHalfSignMask, 0),
+ SDValue(VecOp0, 0),
+ SDValue(UpperLowerMask, 0));
+
+ SDNode *Shift = 0;
+
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
+ unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
+ unsigned bits = unsigned(CN->getZExtValue()) & 7;
+
+ if (bytes > 0) {
+ bytes = 31 - bytes;
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQBYIv2i64, VecVT,
+ SDValue(UpperLowerSelect, 0),
+ CurDAG->getTargetConstant(bytes, ShiftAmtVT));
+ }
+
+ if (bits > 0) {
+ bits = 8 - bits;
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQBIIv2i64, VecVT,
+ SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
+ CurDAG->getTargetConstant(bits, ShiftAmtVT));
+ }
+ } else {
+ SDNode *NegShift =
+ CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
+ ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
+
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, VecVT,
+ SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
+ Shift =
+ CurDAG->getTargetNode(SPU::ROTQBIv2i64, VecVT,
+ SDValue(Shift, 0), SDValue(NegShift, 0));
+ }
+
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
+}
+
+/*!
+ Do the necessary magic necessary to load a i64 constant
+ */
+SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT) {
+ ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
+ MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
+ SDValue i64vec =
+ SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue());
+
+ // Here's where it gets interesting, because we have to parse out the
+ // subtree handed back in i64vec:
+
+ if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
+ // The degenerate case where the upper and lower bits in the splat are
+ // identical:
+ SDValue Op0 = i64vec.getOperand(0);
+ ReplaceUses(i64vec, Op0);
+
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT,
+ SDValue(emitBuildVector(Op0), 0));
+ } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
+ SDValue lhs = i64vec.getOperand(0);
+ SDValue rhs = i64vec.getOperand(1);
+ SDValue shufmask = i64vec.getOperand(2);
+
+ if (lhs.getOpcode() == ISD::BIT_CONVERT) {
+ ReplaceUses(lhs, lhs.getOperand(0));
+ lhs = lhs.getOperand(0);
+ }
+
+ SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
+ ? lhs.getNode()
+ : emitBuildVector(lhs));
+
+ if (rhs.getOpcode() == ISD::BIT_CONVERT) {
+ ReplaceUses(rhs, rhs.getOperand(0));
+ rhs = rhs.getOperand(0);
+ }
+
+ SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
+ ? rhs.getNode()
+ : emitBuildVector(rhs));
+
+ if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
+ ReplaceUses(shufmask, shufmask.getOperand(0));
+ shufmask = shufmask.getOperand(0);
+ }
+
+ SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
+ ? shufmask.getNode()
+ : emitBuildVector(shufmask));
+
+ SDNode *shufNode =
+ Select(CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
+ SDValue(lhsNode, 0), SDValue(rhsNode, 0),
+ SDValue(shufMaskNode, 0)));
+
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(shufNode, 0));
+ } else {
+ cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n";
+ abort();
+ }
+}
+
+/// createSPUISelDag - This pass converts a legalized DAG into a
/// SPU-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
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