Thumb encodings for conditional moves.

[oota-llvm.git] / lib / Target / ARM / ARMInstrThumb.td

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 3af893411963dd354ec2156e7433e5ba257951f3..5dae5bd7a9b71512c41177d2555b6c84dee244d8 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -136,45 +136,41 @@ def tADJCALLSTACKDOWN :
             Requires<[IsThumb, IsThumb1Only]>;
 }
 
+class T1Disassembly<bits<2> op1, bits<8> op2>
+  : T1Encoding<0b101111> {
+  let Inst{9-8} = op1;
+  let Inst{7-0} = op2;
+}
+
 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
                 [/* For disassembly only; pattern left blank */]>,
-           T1Encoding<0b101111> {
-  // A8.6.110
-  let Inst{9-8} = 0b11;
-  let Inst{7-0} = 0x00;
-} 
+           T1Disassembly<0b11, 0x00>; // A8.6.110
 
 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
                   [/* For disassembly only; pattern left blank */]>,
-             T1Encoding<0b101111> {
-  // A8.6.410
-  let Inst{9-8} = 0b11;
-  let Inst{7-0} = 0x10;
-} 
+           T1Disassembly<0b11, 0x10>; // A8.6.410
 
 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
                 [/* For disassembly only; pattern left blank */]>,
-           T1Encoding<0b101111> {
-  // A8.6.408
-  let Inst{9-8} = 0b11;
-  let Inst{7-0} = 0x20;
-} 
+           T1Disassembly<0b11, 0x20>; // A8.6.408
 
 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
                 [/* For disassembly only; pattern left blank */]>,
-           T1Encoding<0b101111> {
-  // A8.6.409
-  let Inst{9-8} = 0b11;
-  let Inst{7-0} = 0x30;
-} 
+           T1Disassembly<0b11, 0x30>; // A8.6.409
 
 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
                 [/* For disassembly only; pattern left blank */]>,
-           T1Encoding<0b101111> {
-  // A8.6.157
-  let Inst{9-8} = 0b11;
-  let Inst{7-0} = 0x40;
-} 
+           T1Disassembly<0b11, 0x40>; // A8.6.157
+
+// The i32imm operand $val can be used by a debugger to store more information
+// about the breakpoint.
+def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
+                [/* For disassembly only; pattern left blank */]>,
+           T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
+  // A8.6.22
+  bits<8> val;
+  let Inst{7-0} = val;
+}
 
 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
                     [/* For disassembly only; pattern left blank */]>,
@@ -196,17 +192,6 @@ def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
   let Inst{2-0} = 0b000;
 }
 
-// The i32imm operand $val can be used by a debugger to store more information
-// about the breakpoint.
-def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
-                [/* For disassembly only; pattern left blank */]>,
-            T1Encoding<0b101111> {
-  // A8.6.22
-  bits<8> val;
-  let Inst{9-8} = 0b10;
-  let Inst{7-0} = val;
-}
-
 // Change Processor State is a system instruction -- for disassembly only.
 // The singleton $opt operand contains the following information:
 // opt{4-0} = mode ==> don't care
@@ -439,14 +424,11 @@ let isBranch = 1, isTerminator = 1 in {
   def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
                     "bl\t$target",[]>;
 
-  let isCodeGenOnly = 1 in
-  def tBR_JTr : T1JTI<(outs),
-                      (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
-                      IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
-                      [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
-                Encoding16 {
-    let Inst{15-7} = 0b010001101;
-    let Inst{2-0} = 0b111;
+  def tBR_JTr : tPseudoInst<(outs),
+                      (ins tGPR:$target, i32imm:$jt, i32imm:$id),
+                      Size2Bytes, IIC_Br,
+                      [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
+    list<Predicate> Predicates = [IsThumb, IsThumb1Only];
   }
   }
 }
@@ -1228,12 +1210,24 @@ let usesCustomInserter = 1 in  // Expanded after instruction selection.
 let neverHasSideEffects = 1 in {
 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
                     "mov", "\t$dst, $rhs", []>,
-              T1Special<{1,0,?,?}>;
+              T1Special<{1,0,?,?}> {
+  bits<4> rhs;
+  bits<4> dst;
+  let Inst{7}   = dst{3};
+  let Inst{6-3} = rhs;
+  let Inst{2-0} = dst{2-0};
+}
 
 let isMoveImm = 1 in
 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
                     "mov", "\t$dst, $rhs", []>,
-              T1General<{1,0,0,?,?}>;
+              T1General<{1,0,0,?,?}> {
+  bits<8> rhs;
+  bits<3> dst;
+  let Inst{10-8} = dst;
+  let Inst{7-0}  = rhs;
+}
+
 } // neverHasSideEffects
 
 // tLEApcrel - Load a pc-relative address into a register without offending the