Thumb encodings for conditional moves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120334 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 5ac8b98832a890aa8a74137b9a3dd658425e1529..5dae5bd7a9b71512c41177d2555b6c84dee244d8 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -1210,12 +1210,24 @@ let usesCustomInserter = 1 in  // Expanded after instruction selection.
 let neverHasSideEffects = 1 in {
 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
                     "mov", "\t$dst, $rhs", []>,
-              T1Special<{1,0,?,?}>;
+              T1Special<{1,0,?,?}> {
+  bits<4> rhs;
+  bits<4> dst;
+  let Inst{7}   = dst{3};
+  let Inst{6-3} = rhs;
+  let Inst{2-0} = dst{2-0};
+}
 
 let isMoveImm = 1 in
 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
                     "mov", "\t$dst, $rhs", []>,
-              T1General<{1,0,0,?,?}>;
+              T1General<{1,0,0,?,?}> {
+  bits<8> rhs;
+  bits<3> dst;
+  let Inst{10-8} = dst;
+  let Inst{7-0}  = rhs;
+}
+
 } // neverHasSideEffects
 
 // tLEApcrel - Load a pc-relative address into a register without offending the