Revert the SelectionDAG optimization that makes

[oota-llvm.git] / lib / CodeGen / SelectionDAG / LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index c40a783da07a2b1cc8a4406710b0a7be860f062a..3d01bb2fa054c461311c4fc12bb2547939a8646f 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -652,8 +652,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
       Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
 
     SDOperand Ops[] = { Result, Chain };
-    return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 
-                       Ops, 2);
+    return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
   }
   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
          "Unaligned load of unsupported type.");
@@ -702,7 +701,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
                              Hi.getValue(1));
 
   SDOperand Ops[] = { Result, TF };
-  return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
+  return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
 }
 
 /// UnrollVectorOp - We know that the given vector has a legal type, however
@@ -933,8 +932,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // Fall Thru
     case TargetLowering::Legal: {
       SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
-      Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
-                           Ops, 2);
+      Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
       break;
     }
     }
@@ -968,8 +966,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // Fall Thru
     case TargetLowering::Legal: {
       SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
-      Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
-                           Ops, 2);
+      Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
       break;
     }
     }
@@ -4737,10 +4734,10 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
         default: assert(0 && "Unsupported FP setcc!");
         }
       }
-      
+
       SDOperand Dummy;
       Tmp1 = ExpandLibCall(LC1,
-                           DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 
+                           DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
                            false /*sign irrelevant*/, Dummy);
       Tmp2 = DAG.getConstant(0, MVT::i32);
       CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));