#define DEBUG_TYPE "pre-RA-sched"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
#include <climits>
using namespace llvm;
+#ifndef NDEBUG
+static cl::opt<bool> StressSchedOpt(
+ "stress-sched", cl::Hidden, cl::init(false),
+ cl::desc("Stress test instruction scheduling"));
+#endif
+
ScheduleDAG::ScheduleDAG(MachineFunction &mf)
- : DAG(0), BB(0), TM(mf.getTarget()),
+ : TM(mf.getTarget()),
TII(TM.getInstrInfo()),
TRI(TM.getRegisterInfo()),
- TLI(TM.getTargetLowering()),
MF(mf), MRI(mf.getRegInfo()),
- ConstPool(MF.getConstantPool()) {
+ EntrySU(), ExitSU() {
+#ifndef NDEBUG
+ StressSched = StressSchedOpt;
+#endif
}
ScheduleDAG::~ScheduleDAG() {}
+/// getInstrDesc helper to handle SDNodes.
+const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
+ if (!Node || !Node->isMachineOpcode()) return NULL;
+ return &TII->get(Node->getMachineOpcode());
+}
+
/// dump - dump the schedule.
void ScheduleDAG::dumpSchedule() const {
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i])
SU->dump(this);
else
- cerr << "**** NOOP ****\n";
+ dbgs() << "**** NOOP ****\n";
}
}
/// Run - perform scheduling.
///
-void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
+void ScheduleDAG::Run(MachineBasicBlock *bb,
+ MachineBasicBlock::iterator insertPos) {
+ BB = bb;
+ InsertPos = insertPos;
+
SUnits.clear();
Sequence.clear();
- DAG = dag;
- BB = bb;
+ EntrySU = SUnit();
+ ExitSU = SUnit();
Schedule();
-
- DOUT << "*** Final schedule ***\n";
- DEBUG(dumpSchedule());
- DOUT << "\n";
+
+ DEBUG({
+ dbgs() << "*** Final schedule ***\n";
+ dumpSchedule();
+ dbgs() << '\n';
+ });
}
/// addPred - This adds the specified edge as a pred of the current node if
/// not already. It also adds the current node as a successor of the
/// specified node.
-void SUnit::addPred(const SDep &D) {
+bool SUnit::addPred(const SDep &D) {
// If this node already has this depenence, don't add a redundant one.
- for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
- if (Preds[i] == D)
- return;
+ for (SmallVector<SDep, 4>::const_iterator I = Preds.begin(), E = Preds.end();
+ I != E; ++I)
+ if (*I == D)
+ return false;
// Now add a corresponding succ to N.
SDep P = D;
P.setSUnit(this);
SUnit *N = D.getSUnit();
// Update the bookkeeping.
if (D.getKind() == SDep::Data) {
+ assert(NumPreds < UINT_MAX && "NumPreds will overflow!");
+ assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!");
++NumPreds;
++N->NumSuccs;
}
- if (!N->isScheduled)
+ if (!N->isScheduled) {
+ assert(NumPredsLeft < UINT_MAX && "NumPredsLeft will overflow!");
++NumPredsLeft;
- if (!isScheduled)
+ }
+ if (!isScheduled) {
+ assert(N->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
++N->NumSuccsLeft;
+ }
Preds.push_back(D);
N->Succs.push_back(P);
if (P.getLatency() != 0) {
this->setDepthDirty();
N->setHeightDirty();
}
+ return true;
}
/// removePred - This removes the specified edge as a pred of the current
break;
}
assert(FoundSucc && "Mismatching preds / succs lists!");
+ (void)FoundSucc;
Preds.erase(I);
// Update the bookkeeping.
if (P.getKind() == SDep::Data) {
+ assert(NumPreds > 0 && "NumPreds will underflow!");
+ assert(N->NumSuccs > 0 && "NumSuccs will underflow!");
--NumPreds;
--N->NumSuccs;
}
- if (!N->isScheduled)
+ if (!N->isScheduled) {
+ assert(NumPredsLeft > 0 && "NumPredsLeft will underflow!");
--NumPredsLeft;
- if (!isScheduled)
+ }
+ if (!isScheduled) {
+ assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");
--N->NumSuccsLeft;
+ }
if (P.getLatency() != 0) {
this->setDepthDirty();
N->setHeightDirty();
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
/// a group of nodes flagged together.
void SUnit::dump(const ScheduleDAG *G) const {
- cerr << "SU(" << NodeNum << "): ";
+ dbgs() << "SU(" << NodeNum << "): ";
G->dumpNode(this);
}
void SUnit::dumpAll(const ScheduleDAG *G) const {
dump(G);
- cerr << " # preds left : " << NumPredsLeft << "\n";
- cerr << " # succs left : " << NumSuccsLeft << "\n";
- cerr << " Latency : " << Latency << "\n";
- cerr << " Depth : " << Depth << "\n";
- cerr << " Height : " << Height << "\n";
+ dbgs() << " # preds left : " << NumPredsLeft << "\n";
+ dbgs() << " # succs left : " << NumSuccsLeft << "\n";
+ dbgs() << " # rdefs left : " << NumRegDefsLeft << "\n";
+ dbgs() << " Latency : " << Latency << "\n";
+ dbgs() << " Depth : " << Depth << "\n";
+ dbgs() << " Height : " << Height << "\n";
if (Preds.size() != 0) {
- cerr << " Predecessors:\n";
+ dbgs() << " Predecessors:\n";
for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
I != E; ++I) {
- cerr << " ";
+ dbgs() << " ";
switch (I->getKind()) {
- case SDep::Data: cerr << "val "; break;
- case SDep::Anti: cerr << "anti"; break;
- case SDep::Output: cerr << "out "; break;
- case SDep::Order: cerr << "ch "; break;
+ case SDep::Data: dbgs() << "val "; break;
+ case SDep::Anti: dbgs() << "anti"; break;
+ case SDep::Output: dbgs() << "out "; break;
+ case SDep::Order: dbgs() << "ch "; break;
}
- cerr << "#";
- cerr << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")";
+ dbgs() << "#";
+ dbgs() << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")";
if (I->isArtificial())
- cerr << " *";
- cerr << "\n";
+ dbgs() << " *";
+ dbgs() << ": Latency=" << I->getLatency();
+ if (I->isAssignedRegDep())
+ dbgs() << " Reg=" << G->TRI->getName(I->getReg());
+ dbgs() << "\n";
}
}
if (Succs.size() != 0) {
- cerr << " Successors:\n";
+ dbgs() << " Successors:\n";
for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
I != E; ++I) {
- cerr << " ";
+ dbgs() << " ";
switch (I->getKind()) {
- case SDep::Data: cerr << "val "; break;
- case SDep::Anti: cerr << "anti"; break;
- case SDep::Output: cerr << "out "; break;
- case SDep::Order: cerr << "ch "; break;
+ case SDep::Data: dbgs() << "val "; break;
+ case SDep::Anti: dbgs() << "anti"; break;
+ case SDep::Output: dbgs() << "out "; break;
+ case SDep::Order: dbgs() << "ch "; break;
}
- cerr << "#";
- cerr << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")";
+ dbgs() << "#";
+ dbgs() << I->getSUnit() << " - SU(" << I->getSUnit()->NodeNum << ")";
if (I->isArtificial())
- cerr << " *";
- cerr << "\n";
+ dbgs() << " *";
+ dbgs() << ": Latency=" << I->getLatency();
+ dbgs() << "\n";
}
}
- cerr << "\n";
+ dbgs() << "\n";
}
#ifndef NDEBUG
continue;
}
if (!AnyNotSched)
- cerr << "*** Scheduling failed! ***\n";
+ dbgs() << "*** Scheduling failed! ***\n";
SUnits[i].dump(this);
- cerr << "has not been scheduled!\n";
+ dbgs() << "has not been scheduled!\n";
AnyNotSched = true;
}
if (SUnits[i].isScheduled &&
- (isBottomUp ? SUnits[i].getHeight() : SUnits[i].getHeight()) >
+ (isBottomUp ? SUnits[i].getHeight() : SUnits[i].getDepth()) >
unsigned(INT_MAX)) {
if (!AnyNotSched)
- cerr << "*** Scheduling failed! ***\n";
+ dbgs() << "*** Scheduling failed! ***\n";
SUnits[i].dump(this);
- cerr << "has an unexpected "
+ dbgs() << "has an unexpected "
<< (isBottomUp ? "Height" : "Depth") << " value!\n";
AnyNotSched = true;
}
if (isBottomUp) {
if (SUnits[i].NumSuccsLeft != 0) {
if (!AnyNotSched)
- cerr << "*** Scheduling failed! ***\n";
+ dbgs() << "*** Scheduling failed! ***\n";
SUnits[i].dump(this);
- cerr << "has successors left!\n";
+ dbgs() << "has successors left!\n";
AnyNotSched = true;
}
} else {
if (SUnits[i].NumPredsLeft != 0) {
if (!AnyNotSched)
- cerr << "*** Scheduling failed! ***\n";
+ dbgs() << "*** Scheduling failed! ***\n";
SUnits[i].dump(this);
- cerr << "has predecessors left!\n";
+ dbgs() << "has predecessors left!\n";
AnyNotSched = true;
}
}
}
#endif
-/// InitDAGTopologicalSorting - create the initial topological
+/// InitDAGTopologicalSorting - create the initial topological
/// ordering from the DAG to be scheduled.
///
-/// The idea of the algorithm is taken from
+/// The idea of the algorithm is taken from
/// "Online algorithms for managing the topological order of
/// a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly
-/// This is the MNR algorithm, which was first introduced by
-/// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in
+/// This is the MNR algorithm, which was first introduced by
+/// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in
/// "Maintaining a topological order under edge insertions".
///
-/// Short description of the algorithm:
+/// Short description of the algorithm:
///
/// Topological ordering, ord, of a DAG maps each node to a topological
/// index so that for all edges X->Y it is the case that ord(X) < ord(Y).
///
-/// This means that if there is a path from the node X to the node Z,
+/// This means that if there is a path from the node X to the node Z,
/// then ord(X) < ord(Z).
///
/// This property can be used to check for reachability of nodes:
-/// if Z is reachable from X, then an insertion of the edge Z->X would
+/// if Z is reachable from X, then an insertion of the edge Z->X would
/// create a cycle.
///
/// The algorithm first computes a topological ordering for the DAG by
// Collect leaf nodes.
WorkList.push_back(SU);
}
- }
+ }
int Id = DAGSize;
while (!WorkList.empty()) {
SUnit *SU = &SUnits[i];
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
- assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] &&
+ assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] &&
"Wrong topological sorting");
}
}
#endif
}
-/// AddPred - Updates the topological ordering to accomodate an edge
+/// AddPred - Updates the topological ordering to accommodate an edge
/// to be added from SUnit X to SUnit Y.
void ScheduleDAGTopologicalSort::AddPred(SUnit *Y, SUnit *X) {
int UpperBound, LowerBound;
}
}
-/// RemovePred - Updates the topological ordering to accomodate an
+/// RemovePred - Updates the topological ordering to accommodate an
/// an edge to be removed from the specified node N from the predecessors
/// of the current node M.
void ScheduleDAGTopologicalSort::RemovePred(SUnit *M, SUnit *N) {
/// all nodes affected by the edge insertion. These nodes will later get new
/// topological indexes by means of the Shift method.
void ScheduleDAGTopologicalSort::DFS(const SUnit *SU, int UpperBound,
- bool& HasLoop) {
+ bool &HasLoop) {
std::vector<const SUnit*> WorkList;
- WorkList.reserve(SUnits.size());
+ WorkList.reserve(SUnits.size());
WorkList.push_back(SU);
do {
for (int I = SU->Succs.size()-1; I >= 0; --I) {
int s = SU->Succs[I].getSUnit()->NodeNum;
if (Node2Index[s] == UpperBound) {
- HasLoop = true;
+ HasLoop = true;
return;
}
// Visit successors if not already and in affected region.
if (!Visited.test(s) && Node2Index[s] < UpperBound) {
WorkList.push_back(SU->Succs[I].getSUnit());
- }
- }
+ }
+ }
} while (!WorkList.empty());
}
-/// Shift - Renumber the nodes so that the topological ordering is
+/// Shift - Renumber the nodes so that the topological ordering is
/// preserved.
-void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
+void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
int UpperBound) {
std::vector<int> L;
int shift = 0;
// Is Ord(TargetSU) < Ord(SU) ?
if (LowerBound < UpperBound) {
Visited.reset();
- // There may be a path from TargetSU to SU. Check for it.
+ // There may be a path from TargetSU to SU. Check for it.
DFS(TargetSU, UpperBound, HasLoop);
}
return HasLoop;
Index2Node[index] = n;
}
-ScheduleDAGTopologicalSort::ScheduleDAGTopologicalSort(
- std::vector<SUnit> &sunits)
- : SUnits(sunits) {}
+ScheduleDAGTopologicalSort::
+ScheduleDAGTopologicalSort(std::vector<SUnit> &sunits) : SUnits(sunits) {}
ScheduleHazardRecognizer::~ScheduleHazardRecognizer() {}
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