getReservedRegs(const MachineFunction &MF) const {
static const unsigned ReservedCPURegs[] = {
Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
- Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0
+ Mips::GP, Mips::SP, Mips::FP, Mips::RA
};
static const unsigned ReservedCPU64Regs[] = {
Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
- Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 0
+ Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
};
BitVector Reserved(getNumRegs());
typedef TargetRegisterClass::iterator RegIter;
- for (const unsigned *Reg = ReservedCPURegs; *Reg; ++Reg)
- Reserved.set(*Reg);
+ for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
+ Reserved.set(ReservedCPURegs[I]);
if (Subtarget.hasMips64()) {
- for (const unsigned *Reg = ReservedCPU64Regs; *Reg; ++Reg)
- Reserved.set(*Reg);
+ for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
+ Reserved.set(ReservedCPU64Regs[I]);
// Reserve all registers in AFGR64.
for (RegIter Reg = Mips::AFGR64RegisterClass->begin();