enhance vmcore to know that udiv's can be exact, and add a trivial

[oota-llvm.git] / docs / CodeGenerator.html

diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index d4e932a969fe9deb84ca7a6e375207a39a9164d9..a84534644cfeedd9c71ecaed6c23d4e1cec1e076 100644 (file)
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -1030,9 +1030,9 @@ printer, and the type generated by the assembly parser and disassembler.
       SelectionDAG optimizer is run to clean up redundancies exposed by type
       legalization.</li>
 
-  <li><a href="#selectiondag_legalize">Legalize SelectionDAG Types</a> &mdash;
-      This stage transforms SelectionDAG nodes to eliminate any types that are
-      unsupported on the target.</li>
+  <li><a href="#selectiondag_legalize">Legalize SelectionDAG Ops</a> &mdash;
+      This stage transforms SelectionDAG nodes to eliminate any operations 
+      that are unsupported on the target.</li>
 
   <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
       SelectionDAG optimizer is run to eliminate inefficiencies introduced by
@@ -1559,18 +1559,25 @@ bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
    </p>
 
 <p>Virtual registers are also denoted by integer numbers. Contrary to physical
-   registers, different virtual registers never share the same number. The
-   smallest virtual register is normally assigned the number 1024. This may
-   change, so, in order to know which is the first virtual register, you should
-   access <tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
-   number is greater than or equal
-   to <tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
-   register. Whereas physical registers are statically defined in
-   a <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
-   application developer, that is not the case with virtual registers.  In order
-   to create new virtual registers, use the
+   registers, different virtual registers never share the same number. Whereas
+   physical registers are statically defined in a <tt>TargetRegisterInfo.td</tt>
+   file and cannot be created by the application developer, that is not the case
+   with virtual registers. In order to create new virtual registers, use the
    method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
-   will return a virtual register with the highest code.</p>
+   will return a new virtual register. Use an <tt>IndexedMap&lt;Foo,
+   VirtReg2IndexFunctor&gt;</tt> to hold information per virtual register. If you
+   need to enumerate all virtual registers, use the function
+   <tt>TargetRegisterInfo::index2VirtReg()</tt> to find the virtual register
+   numbers:</p>
+
+<div class="doc_code">
+<pre>
+  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
+    unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
+    stuff(VirtReg);
+  }
+</pre>
+</div>
 
 <p>Before register allocation, the operands of an instruction are mostly virtual
    registers, although physical registers may also be used. In order to check if
@@ -1998,7 +2005,23 @@ def : InstAlias&lt;"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)&gt;;
 <p>This example also shows that tied operands are only listed once.  In the X86
 backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
 to the output).  InstAliases take a flattened operand list without duplicates
-for tied operands.</p>
+for tied operands.  The result of an instruction alias can also use immediates
+and fixed physical registers which are added as simple immediate operands in the
+result, for example:</p>
+
+<div class="doc_code">
+<pre>
+// Fixed Immediate operand.
+def : InstAlias&lt;"aad", (AAD8i8 10)&gt;;
+
+// Fixed register operand.
+def : InstAlias&lt;"fcomi", (COM_FIr ST1)&gt;;
+
+// Simple alias.
+def : InstAlias&lt;"fcomi $reg", (COM_FIr RST:$reg)&gt;;
+</pre>
+</div>
+
 
 <p>Instruction aliases can also have a Requires clause to make them
 subtarget specific.</p>
@@ -2091,7 +2114,7 @@ is the key:</p>
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="yes"></td> <!-- Sparc -->
@@ -2106,7 +2129,7 @@ is the key:</p>
   <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
   <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
@@ -2123,7 +2146,7 @@ is the key:</p>
   <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
   <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
@@ -2140,9 +2163,9 @@ is the key:</p>
   <td class="unknown"></td> <!-- Alpha -->
   <td class="yes"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->
@@ -2154,12 +2177,12 @@ is the key:</p>
 <tr>
   <td><a href="#feat_jit">jit</a></td>
   <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
-  <td class="unknown"></td> <!-- Alpha -->
+  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->
@@ -2174,7 +2197,7 @@ is the key:</p>
   <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
   <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
@@ -2193,7 +2216,7 @@ is the key:</p>
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->