enhance vmcore to know that udiv's can be exact, and add a trivial
authorChris Lattner <sabre@nondot.org>
Sun, 6 Feb 2011 21:44:57 +0000 (21:44 +0000)
committerChris Lattner <sabre@nondot.org>
Sun, 6 Feb 2011 21:44:57 +0000 (21:44 +0000)
commit35bda8914c0d1c02a6f90f42e7810c83150737e1
treeb210ccd009a7ac5331c76c6393b5b45d141d12d0
parentbd75021465e7f8c81785e692cfd3ce559764e46f
enhance vmcore to know that udiv's can be exact, and add a trivial
instcombine xform to exercise this.

Nothing forms exact udivs yet though.  This is progress on PR8862

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124992 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
docs/LangRef.html
include/llvm/Bitcode/LLVMBitCodes.h
include/llvm/Constants.h
include/llvm/InstrTypes.h
include/llvm/Operator.h
lib/AsmParser/LLParser.cpp
lib/Bitcode/Reader/BitcodeReader.cpp
lib/Bitcode/Writer/BitcodeWriter.cpp
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
lib/VMCore/AsmWriter.cpp
lib/VMCore/Constants.cpp
lib/VMCore/Instructions.cpp
test/Assembler/flags.ll
test/Transforms/InstCombine/exact-sdiv.ll [deleted file]
test/Transforms/InstCombine/exact.ll [new file with mode: 0644]