enhance vmcore to know that udiv's can be exact, and add a trivial

[oota-llvm.git] / docs / CodeGenerator.html

diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index 06f102e3e695da155b71e9bbad50efd0bb6d3cab..a84534644cfeedd9c71ecaed6c23d4e1cec1e076 100644 (file)
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -1031,8 +1031,8 @@ printer, and the type generated by the assembly parser and disassembler.
       legalization.</li>
 
   <li><a href="#selectiondag_legalize">Legalize SelectionDAG Ops</a> &mdash;
-      This stage transforms SelectionDAG nodes to eliminate any types that are
-      unsupported on the target.</li>
+      This stage transforms SelectionDAG nodes to eliminate any operations 
+      that are unsupported on the target.</li>
 
   <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
       SelectionDAG optimizer is run to eliminate inefficiencies introduced by
@@ -1559,18 +1559,25 @@ bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
    </p>
 
 <p>Virtual registers are also denoted by integer numbers. Contrary to physical
-   registers, different virtual registers never share the same number. The
-   smallest virtual register is normally assigned the number 1024. This may
-   change, so, in order to know which is the first virtual register, you should
-   access <tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
-   number is greater than or equal
-   to <tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
-   register. Whereas physical registers are statically defined in
-   a <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
-   application developer, that is not the case with virtual registers.  In order
-   to create new virtual registers, use the
+   registers, different virtual registers never share the same number. Whereas
+   physical registers are statically defined in a <tt>TargetRegisterInfo.td</tt>
+   file and cannot be created by the application developer, that is not the case
+   with virtual registers. In order to create new virtual registers, use the
    method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
-   will return a virtual register with the highest code.</p>
+   will return a new virtual register. Use an <tt>IndexedMap&lt;Foo,
+   VirtReg2IndexFunctor&gt;</tt> to hold information per virtual register. If you
+   need to enumerate all virtual registers, use the function
+   <tt>TargetRegisterInfo::index2VirtReg()</tt> to find the virtual register
+   numbers:</p>
+
+<div class="doc_code">
+<pre>
+  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
+    unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
+    stuff(VirtReg);
+  }
+</pre>
+</div>
 
 <p>Before register allocation, the operands of an instruction are mostly virtual
    registers, although physical registers may also be used. In order to check if
@@ -2107,7 +2114,7 @@ is the key:</p>
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="yes"></td> <!-- Sparc -->
@@ -2122,7 +2129,7 @@ is the key:</p>
   <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
   <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
@@ -2139,7 +2146,7 @@ is the key:</p>
   <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
   <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
@@ -2156,9 +2163,9 @@ is the key:</p>
   <td class="unknown"></td> <!-- Alpha -->
   <td class="yes"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->
@@ -2175,7 +2182,7 @@ is the key:</p>
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->
@@ -2190,7 +2197,7 @@ is the key:</p>
   <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
-  <td class="no"></td> <!-- MBlaze -->
+  <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
   <td class="no"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
@@ -2209,7 +2216,7 @@ is the key:</p>
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="unknown"></td> <!-- Mips -->
+  <td class="no"></td> <!-- Mips -->
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->