1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
4 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6 define void @fadd_f32() {
7 %r0 = call float @llvm.R600.load.input(i32 0)
8 %r1 = call float @llvm.R600.load.input(i32 1)
9 %r2 = fadd float %r0, %r1
10 call void @llvm.AMDGPU.store.output(float %r2, i32 0)
14 declare float @llvm.R600.load.input(i32) readnone
16 declare void @llvm.AMDGPU.store.output(float, i32)
19 ; CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
20 ; CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
21 define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
23 %0 = fadd <2 x float> %a, %b
24 store <2 x float> %0, <2 x float> addrspace(1)* %out
29 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
30 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
31 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
32 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
34 define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
35 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
36 %a = load <4 x float> addrspace(1) * %in
37 %b = load <4 x float> addrspace(1) * %b_ptr
38 %result = fadd <4 x float> %a, %b
39 store <4 x float> %result, <4 x float> addrspace(1)* %out