1 ; Test the MSA intrinsics that are encoded with the 3RF instruction format.
3 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
5 @llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
6 @llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
7 @llvm_mips_fadd_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
9 define void @llvm_mips_fadd_w_test() nounwind {
11 %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1
12 %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2
13 %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1)
14 store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES
18 declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind
20 ; CHECK: llvm_mips_fadd_w_test:
25 ; CHECK: .size llvm_mips_fadd_w_test
27 @llvm_mips_fadd_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
28 @llvm_mips_fadd_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
29 @llvm_mips_fadd_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
31 define void @llvm_mips_fadd_d_test() nounwind {
33 %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1
34 %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2
35 %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1)
36 store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES
40 declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind
42 ; CHECK: llvm_mips_fadd_d_test:
47 ; CHECK: .size llvm_mips_fadd_d_test
49 @llvm_mips_fdiv_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
50 @llvm_mips_fdiv_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
51 @llvm_mips_fdiv_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
53 define void @llvm_mips_fdiv_w_test() nounwind {
55 %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1
56 %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2
57 %2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1)
58 store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES
62 declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>) nounwind
64 ; CHECK: llvm_mips_fdiv_w_test:
69 ; CHECK: .size llvm_mips_fdiv_w_test
71 @llvm_mips_fdiv_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
72 @llvm_mips_fdiv_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
73 @llvm_mips_fdiv_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
75 define void @llvm_mips_fdiv_d_test() nounwind {
77 %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1
78 %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2
79 %2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1)
80 store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES
84 declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>) nounwind
86 ; CHECK: llvm_mips_fdiv_d_test:
91 ; CHECK: .size llvm_mips_fdiv_d_test
93 @llvm_mips_fmin_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
94 @llvm_mips_fmin_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
95 @llvm_mips_fmin_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
97 define void @llvm_mips_fmin_w_test() nounwind {
99 %0 = load <4 x float>* @llvm_mips_fmin_w_ARG1
100 %1 = load <4 x float>* @llvm_mips_fmin_w_ARG2
101 %2 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %0, <4 x float> %1)
102 store <4 x float> %2, <4 x float>* @llvm_mips_fmin_w_RES
106 declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind
108 ; CHECK: llvm_mips_fmin_w_test:
113 ; CHECK: .size llvm_mips_fmin_w_test
115 @llvm_mips_fmin_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
116 @llvm_mips_fmin_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
117 @llvm_mips_fmin_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
119 define void @llvm_mips_fmin_d_test() nounwind {
121 %0 = load <2 x double>* @llvm_mips_fmin_d_ARG1
122 %1 = load <2 x double>* @llvm_mips_fmin_d_ARG2
123 %2 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %0, <2 x double> %1)
124 store <2 x double> %2, <2 x double>* @llvm_mips_fmin_d_RES
128 declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind
130 ; CHECK: llvm_mips_fmin_d_test:
135 ; CHECK: .size llvm_mips_fmin_d_test
137 @llvm_mips_fmin_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
138 @llvm_mips_fmin_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
139 @llvm_mips_fmin_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
141 define void @llvm_mips_fmin_a_w_test() nounwind {
143 %0 = load <4 x float>* @llvm_mips_fmin_a_w_ARG1
144 %1 = load <4 x float>* @llvm_mips_fmin_a_w_ARG2
145 %2 = tail call <4 x float> @llvm.mips.fmin.a.w(<4 x float> %0, <4 x float> %1)
146 store <4 x float> %2, <4 x float>* @llvm_mips_fmin_a_w_RES
150 declare <4 x float> @llvm.mips.fmin.a.w(<4 x float>, <4 x float>) nounwind
152 ; CHECK: llvm_mips_fmin_a_w_test:
157 ; CHECK: .size llvm_mips_fmin_a_w_test
159 @llvm_mips_fmin_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
160 @llvm_mips_fmin_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
161 @llvm_mips_fmin_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
163 define void @llvm_mips_fmin_a_d_test() nounwind {
165 %0 = load <2 x double>* @llvm_mips_fmin_a_d_ARG1
166 %1 = load <2 x double>* @llvm_mips_fmin_a_d_ARG2
167 %2 = tail call <2 x double> @llvm.mips.fmin.a.d(<2 x double> %0, <2 x double> %1)
168 store <2 x double> %2, <2 x double>* @llvm_mips_fmin_a_d_RES
172 declare <2 x double> @llvm.mips.fmin.a.d(<2 x double>, <2 x double>) nounwind
174 ; CHECK: llvm_mips_fmin_a_d_test:
179 ; CHECK: .size llvm_mips_fmin_a_d_test
181 @llvm_mips_fmax_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
182 @llvm_mips_fmax_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
183 @llvm_mips_fmax_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
185 define void @llvm_mips_fmax_w_test() nounwind {
187 %0 = load <4 x float>* @llvm_mips_fmax_w_ARG1
188 %1 = load <4 x float>* @llvm_mips_fmax_w_ARG2
189 %2 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %0, <4 x float> %1)
190 store <4 x float> %2, <4 x float>* @llvm_mips_fmax_w_RES
194 declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
196 ; CHECK: llvm_mips_fmax_w_test:
201 ; CHECK: .size llvm_mips_fmax_w_test
203 @llvm_mips_fmax_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
204 @llvm_mips_fmax_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
205 @llvm_mips_fmax_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
207 define void @llvm_mips_fmax_d_test() nounwind {
209 %0 = load <2 x double>* @llvm_mips_fmax_d_ARG1
210 %1 = load <2 x double>* @llvm_mips_fmax_d_ARG2
211 %2 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %0, <2 x double> %1)
212 store <2 x double> %2, <2 x double>* @llvm_mips_fmax_d_RES
216 declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind
218 ; CHECK: llvm_mips_fmax_d_test:
223 ; CHECK: .size llvm_mips_fmax_d_test
225 @llvm_mips_fmax_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
226 @llvm_mips_fmax_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
227 @llvm_mips_fmax_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
229 define void @llvm_mips_fmax_a_w_test() nounwind {
231 %0 = load <4 x float>* @llvm_mips_fmax_a_w_ARG1
232 %1 = load <4 x float>* @llvm_mips_fmax_a_w_ARG2
233 %2 = tail call <4 x float> @llvm.mips.fmax.a.w(<4 x float> %0, <4 x float> %1)
234 store <4 x float> %2, <4 x float>* @llvm_mips_fmax_a_w_RES
238 declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>) nounwind
240 ; CHECK: llvm_mips_fmax_a_w_test:
245 ; CHECK: .size llvm_mips_fmax_a_w_test
247 @llvm_mips_fmax_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
248 @llvm_mips_fmax_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
249 @llvm_mips_fmax_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
251 define void @llvm_mips_fmax_a_d_test() nounwind {
253 %0 = load <2 x double>* @llvm_mips_fmax_a_d_ARG1
254 %1 = load <2 x double>* @llvm_mips_fmax_a_d_ARG2
255 %2 = tail call <2 x double> @llvm.mips.fmax.a.d(<2 x double> %0, <2 x double> %1)
256 store <2 x double> %2, <2 x double>* @llvm_mips_fmax_a_d_RES
260 declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>) nounwind
262 ; CHECK: llvm_mips_fmax_a_d_test:
267 ; CHECK: .size llvm_mips_fmax_a_d_test
269 @llvm_mips_fmul_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
270 @llvm_mips_fmul_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
271 @llvm_mips_fmul_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
273 define void @llvm_mips_fmul_w_test() nounwind {
275 %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1
276 %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2
277 %2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
278 store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES
282 declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) nounwind
284 ; CHECK: llvm_mips_fmul_w_test:
289 ; CHECK: .size llvm_mips_fmul_w_test
291 @llvm_mips_fmul_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
292 @llvm_mips_fmul_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
293 @llvm_mips_fmul_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
295 define void @llvm_mips_fmul_d_test() nounwind {
297 %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1
298 %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2
299 %2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1)
300 store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES
304 declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>) nounwind
306 ; CHECK: llvm_mips_fmul_d_test:
311 ; CHECK: .size llvm_mips_fmul_d_test
313 @llvm_mips_fsub_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
314 @llvm_mips_fsub_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
315 @llvm_mips_fsub_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
317 define void @llvm_mips_fsub_w_test() nounwind {
319 %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1
320 %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2
321 %2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1)
322 store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES
326 declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>) nounwind
328 ; CHECK: llvm_mips_fsub_w_test:
333 ; CHECK: .size llvm_mips_fsub_w_test
335 @llvm_mips_fsub_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
336 @llvm_mips_fsub_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
337 @llvm_mips_fsub_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
339 define void @llvm_mips_fsub_d_test() nounwind {
341 %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1
342 %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2
343 %2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1)
344 store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES
348 declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>) nounwind
350 ; CHECK: llvm_mips_fsub_d_test:
355 ; CHECK: .size llvm_mips_fsub_d_test