1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI %s
3 @lds = addrspace(3) global [512 x float] undef, align 4
4 @lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4
5 @lds.v3 = addrspace(3) global [512 x <3 x float>] undef, align 4
6 @lds.v4 = addrspace(3) global [512 x <4 x float>] undef, align 4
7 @lds.v8 = addrspace(3) global [512 x <8 x float>] undef, align 4
8 @lds.v16 = addrspace(3) global [512 x <16 x float>] undef, align 4
10 ; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4:
11 ; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
12 ; CI: s_waitcnt lgkmcnt(0)
13 ; CI: buffer_store_dwordx2 [[RESULT]]
15 define void @simple_read2_v2f32_superreg_align4(<2 x float> addrspace(1)* %out) #0 {
16 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
17 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
18 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4
19 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
20 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
24 ; CI-LABEL: {{^}}simple_read2_v2f32_superreg:
25 ; CI: ds_read_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}
26 ; CI: s_waitcnt lgkmcnt(0)
27 ; CI: buffer_store_dwordx2 [[RESULT]]
29 define void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 {
30 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
31 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
32 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0
33 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
34 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
38 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4:
39 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
41 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
42 ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_W]], v[[REG_Y]]
43 ; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD1]], v[[ADD0]]
44 ; CI: buffer_store_dword v[[ADD2]]
46 define void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 {
47 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
48 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
49 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4
50 %elt0 = extractelement <4 x float> %val0, i32 0
51 %elt1 = extractelement <4 x float> %val0, i32 1
52 %elt2 = extractelement <4 x float> %val0, i32 2
53 %elt3 = extractelement <4 x float> %val0, i32 3
55 %add0 = fadd float %elt0, %elt2
56 %add1 = fadd float %elt1, %elt3
57 %add2 = fadd float %add0, %add1
59 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
60 store float %add2, float addrspace(1)* %out.gep
65 ; FIXME: the v_lshl_b64 x, x, 32 is a bad way of doing a copy
67 ; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4:
68 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
69 ; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
70 ; CI: v_lshr_b64 v{{\[}}[[Y_COPY:[0-9]+]]:{{[0-9]+\]}}, v{{\[}}[[REG_X]]:[[REG_Y]]{{\]}}, 32
71 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
72 ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[Y_COPY]], v[[ADD0]]
73 ; CI: buffer_store_dword v[[ADD1]]
75 define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 {
76 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
77 %arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i
78 %val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4
79 %elt0 = extractelement <3 x float> %val0, i32 0
80 %elt1 = extractelement <3 x float> %val0, i32 1
81 %elt2 = extractelement <3 x float> %val0, i32 2
83 %add0 = fadd float %elt0, %elt2
84 %add1 = fadd float %add0, %elt1
86 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
87 store float %add1, float addrspace(1)* %out.gep
91 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8:
92 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
93 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
94 ; CI: buffer_store_dwordx4
96 define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) #0 {
97 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
98 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
99 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 8
100 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
101 store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
105 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg:
106 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
107 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
108 ; CI: buffer_store_dwordx4
110 define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 {
111 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
112 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
113 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0
114 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
115 store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
119 ; CI-LABEL: {{^}}simple_read2_v8f32_superreg:
120 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
121 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
122 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
123 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
124 ; CI: buffer_store_dword
125 ; CI: buffer_store_dword
126 ; CI: buffer_store_dword
127 ; CI: buffer_store_dword
128 ; CI: buffer_store_dword
129 ; CI: buffer_store_dword
130 ; CI: buffer_store_dword
131 ; CI: buffer_store_dword
133 define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 {
134 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
135 %arrayidx0 = getelementptr inbounds [512 x <8 x float>], [512 x <8 x float>] addrspace(3)* @lds.v8, i32 0, i32 %x.i
136 %val0 = load <8 x float>, <8 x float> addrspace(3)* %arrayidx0
137 %out.gep = getelementptr inbounds <8 x float>, <8 x float> addrspace(1)* %out, i32 %x.i
138 store <8 x float> %val0, <8 x float> addrspace(1)* %out.gep
142 ; CI-LABEL: {{^}}simple_read2_v16f32_superreg:
143 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:15 offset1:14{{$}}
145 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:13 offset1:12{{$}}
147 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:11 offset1:10{{$}}
149 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:9 offset1:8{{$}}
151 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
153 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
155 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
157 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
160 ; CI: s_waitcnt lgkmcnt(0)
161 ; CI: buffer_store_dword
162 ; CI: buffer_store_dword
163 ; CI: buffer_store_dword
164 ; CI: buffer_store_dword
165 ; CI: buffer_store_dword
166 ; CI: buffer_store_dword
167 ; CI: buffer_store_dword
168 ; CI: buffer_store_dword
169 ; CI: buffer_store_dword
170 ; CI: buffer_store_dword
171 ; CI: buffer_store_dword
172 ; CI: buffer_store_dword
173 ; CI: buffer_store_dword
174 ; CI: buffer_store_dword
175 ; CI: buffer_store_dword
176 ; CI: buffer_store_dword
178 define void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 {
179 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
180 %arrayidx0 = getelementptr inbounds [512 x <16 x float>], [512 x <16 x float>] addrspace(3)* @lds.v16, i32 0, i32 %x.i
181 %val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0
182 %out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i
183 store <16 x float> %val0, <16 x float> addrspace(1)* %out.gep
187 ; Do scalar loads into the super register we need.
188 ; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4:
189 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
191 ; CI: buffer_store_dwordx2 v{{\[}}[[REG_ELT0]]:[[REG_ELT1]]{{\]}}
193 define void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 {
194 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
195 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
196 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
198 %val0 = load float, float addrspace(3)* %arrayidx0
199 %val1 = load float, float addrspace(3)* %arrayidx1
201 %vec.0 = insertelement <2 x float> undef, float %val0, i32 0
202 %vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1
204 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
205 store <2 x float> %vec.1, <2 x float> addrspace(1)* %out.gep
209 ; Do scalar loads into the super register we need.
210 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4:
211 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
212 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
214 ; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}}
216 define void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 {
217 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
218 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
219 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
220 %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2
221 %arrayidx3 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 3
223 %val0 = load float, float addrspace(3)* %arrayidx0
224 %val1 = load float, float addrspace(3)* %arrayidx1
225 %val2 = load float, float addrspace(3)* %arrayidx2
226 %val3 = load float, float addrspace(3)* %arrayidx3
228 %vec.0 = insertelement <4 x float> undef, float %val0, i32 0
229 %vec.1 = insertelement <4 x float> %vec.0, float %val1, i32 1
230 %vec.2 = insertelement <4 x float> %vec.1, float %val2, i32 2
231 %vec.3 = insertelement <4 x float> %vec.2, float %val3, i32 3
233 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
234 store <4 x float> %vec.3, <4 x float> addrspace(1)* %out.gep
238 ; Function Attrs: nounwind readnone
239 declare i32 @llvm.r600.read.tgid.x() #1
241 ; Function Attrs: nounwind readnone
242 declare i32 @llvm.r600.read.tgid.y() #1
244 ; Function Attrs: nounwind readnone
245 declare i32 @llvm.r600.read.tidig.x() #1
247 ; Function Attrs: nounwind readnone
248 declare i32 @llvm.r600.read.tidig.y() #1
250 ; Function Attrs: noduplicate nounwind
251 declare void @llvm.AMDGPU.barrier.local() #2
253 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
254 attributes #1 = { nounwind readnone }
255 attributes #2 = { noduplicate nounwind }