1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameLowering.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
36 #define GET_REGINFO_MC_DESC
37 #define GET_REGINFO_TARGET_DESC
38 #include "XCoreGenRegisterInfo.inc"
42 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
43 : XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
44 XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
49 static inline bool isImmUs(unsigned val) {
53 static inline bool isImmU6(unsigned val) {
54 return val < (1 << 6);
57 static inline bool isImmU16(unsigned val) {
58 return val < (1 << 16);
61 static const unsigned XCore_ArgRegs[] = {
62 XCore::R0, XCore::R1, XCore::R2, XCore::R3
65 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
70 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
72 return array_lengthof(XCore_ArgRegs);
75 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
76 return MF.getMMI().hasDebugInfo() ||
77 MF.getFunction()->needsUnwindTableEntry();
80 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
82 static const unsigned CalleeSavedRegs[] = {
83 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
84 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
87 return CalleeSavedRegs;
90 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
91 BitVector Reserved(getNumRegs());
92 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
94 Reserved.set(XCore::CP);
95 Reserved.set(XCore::DP);
96 Reserved.set(XCore::SP);
97 Reserved.set(XCore::LR);
99 Reserved.set(XCore::R10);
105 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
106 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
108 // TODO can we estimate stack size?
109 return TFI->hasFP(MF);
113 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
117 // This function eliminates ADJCALLSTACKDOWN,
118 // ADJCALLSTACKUP pseudo instructions
119 void XCoreRegisterInfo::
120 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator I) const {
122 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
124 if (!TFI->hasReservedCallFrame(MF)) {
125 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
126 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
127 MachineInstr *Old = I;
128 uint64_t Amount = Old->getOperand(0).getImm();
130 // We need to keep the stack aligned properly. To do this, we round the
131 // amount of space needed for the outgoing arguments up to the next
132 // alignment boundary.
133 unsigned Align = TFI->getStackAlignment();
134 Amount = (Amount+Align-1)/Align*Align;
136 assert(Amount%4 == 0);
139 bool isU6 = isImmU6(Amount);
140 if (!isU6 && !isImmU16(Amount)) {
141 // FIX could emit multiple instructions in this case.
143 errs() << "eliminateCallFramePseudoInstr size too big: "
150 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
151 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
152 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
155 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
156 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
157 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
161 // Replace the pseudo instruction with a new instruction...
170 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
171 int SPAdj, RegScavenger *RS) const {
172 assert(SPAdj == 0 && "Unexpected");
173 MachineInstr &MI = *II;
174 DebugLoc dl = MI.getDebugLoc();
177 while (!MI.getOperand(i).isFI()) {
179 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
182 MachineOperand &FrameOp = MI.getOperand(i);
183 int FrameIndex = FrameOp.getIndex();
185 MachineFunction &MF = *MI.getParent()->getParent();
186 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
187 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
188 int StackSize = MF.getFrameInfo()->getStackSize();
191 DEBUG(errs() << "\nFunction : "
192 << MF.getFunction()->getName() << "\n");
193 DEBUG(errs() << "<--------->\n");
194 DEBUG(MI.print(errs()));
195 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
196 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
197 DEBUG(errs() << "StackSize : " << StackSize << "\n");
202 // fold constant into offset.
203 Offset += MI.getOperand(i + 1).getImm();
204 MI.getOperand(i + 1).ChangeToImmediate(0);
206 assert(Offset%4 == 0 && "Misaligned stack offset");
208 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
212 bool FP = TFI->hasFP(MF);
214 unsigned Reg = MI.getOperand(0).getReg();
215 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
217 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
218 "Unexpected register operand");
220 MachineBasicBlock &MBB = *MI.getParent();
223 bool isUs = isImmUs(Offset);
224 unsigned FramePtr = XCore::R10;
228 report_fatal_error("eliminateFrameIndex Frame size too big: " +
230 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
232 loadConstant(MBB, II, ScratchReg, Offset, dl);
233 switch (MI.getOpcode()) {
235 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
237 .addReg(ScratchReg, RegState::Kill);
240 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
241 .addReg(Reg, getKillRegState(isKill))
243 .addReg(ScratchReg, RegState::Kill);
246 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
248 .addReg(ScratchReg, RegState::Kill);
251 llvm_unreachable("Unexpected Opcode");
254 switch (MI.getOpcode()) {
256 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
261 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
262 .addReg(Reg, getKillRegState(isKill))
267 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
272 llvm_unreachable("Unexpected Opcode");
276 bool isU6 = isImmU6(Offset);
277 if (!isU6 && !isImmU16(Offset))
278 report_fatal_error("eliminateFrameIndex Frame size too big: " +
281 switch (MI.getOpcode()) {
284 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
285 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
289 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
290 BuildMI(MBB, II, dl, TII.get(NewOpcode))
291 .addReg(Reg, getKillRegState(isKill))
295 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
296 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
300 llvm_unreachable("Unexpected Opcode");
303 // Erase old instruction.
307 void XCoreRegisterInfo::
308 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
309 unsigned DstReg, int64_t Value, DebugLoc dl) const {
310 // TODO use mkmsk if possible.
311 if (!isImmU16(Value)) {
312 // TODO use constant pool.
313 report_fatal_error("loadConstant value too big " + Twine(Value));
315 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
316 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
319 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
320 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
323 int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
324 return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
327 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
328 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
330 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
333 unsigned XCoreRegisterInfo::getRARegister() const {