1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
68 // getDwarfRegNum - This function maps LLVM register identifiers to the
69 // Dwarf specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
74 if (!Subtarget->is64Bit()) {
75 if (Subtarget->isTargetDarwin()) {
77 Flavour = DWARFFlavour::X86_32_DarwinEH;
79 Flavour = DWARFFlavour::X86_32_Generic;
80 } else if (Subtarget->isTargetCygMing()) {
81 // Unsupported by now, just quick fallback
82 Flavour = DWARFFlavour::X86_32_Generic;
84 Flavour = DWARFFlavour::X86_32_Generic;
88 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
91 // getX86RegNum - This function maps LLVM register identifiers to their X86
92 // specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
148 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
154 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
155 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
156 if (Subtarget->is64Bit())
157 return &X86::GR64RegClass;
159 return &X86::GR32RegClass;
162 const TargetRegisterClass *
163 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
164 if (RC == &X86::CCRRegClass) {
166 return &X86::GR64RegClass;
168 return &X86::GR32RegClass;
174 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
175 bool callsEHReturn = false;
178 const MachineFrameInfo *MFI = MF->getFrameInfo();
179 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
180 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
183 static const unsigned CalleeSavedRegs32Bit[] = {
184 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
187 static const unsigned CalleeSavedRegs32EHRet[] = {
188 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
191 static const unsigned CalleeSavedRegs64Bit[] = {
192 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
195 static const unsigned CalleeSavedRegs64EHRet[] = {
196 X86::RAX, X86::RDX, X86::RBX, X86::R12,
197 X86::R13, X86::R14, X86::R15, X86::RBP, 0
200 static const unsigned CalleeSavedRegsWin64[] = {
201 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
202 X86::R12, X86::R13, X86::R14, X86::R15,
203 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
204 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
205 X86::XMM14, X86::XMM15, 0
210 return CalleeSavedRegsWin64;
212 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
214 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
218 const TargetRegisterClass* const*
219 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
220 bool callsEHReturn = false;
223 const MachineFrameInfo *MFI = MF->getFrameInfo();
224 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
228 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
229 &X86::GR32RegClass, &X86::GR32RegClass,
230 &X86::GR32RegClass, &X86::GR32RegClass, 0
232 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
233 &X86::GR32RegClass, &X86::GR32RegClass,
234 &X86::GR32RegClass, &X86::GR32RegClass,
235 &X86::GR32RegClass, &X86::GR32RegClass, 0
237 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
238 &X86::GR64RegClass, &X86::GR64RegClass,
239 &X86::GR64RegClass, &X86::GR64RegClass,
240 &X86::GR64RegClass, &X86::GR64RegClass, 0
242 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
243 &X86::GR64RegClass, &X86::GR64RegClass,
244 &X86::GR64RegClass, &X86::GR64RegClass,
245 &X86::GR64RegClass, &X86::GR64RegClass,
246 &X86::GR64RegClass, &X86::GR64RegClass, 0
248 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
249 &X86::GR64RegClass, &X86::GR64RegClass,
250 &X86::GR64RegClass, &X86::GR64RegClass,
251 &X86::GR64RegClass, &X86::GR64RegClass,
252 &X86::GR64RegClass, &X86::GR64RegClass,
253 &X86::VR128RegClass, &X86::VR128RegClass,
254 &X86::VR128RegClass, &X86::VR128RegClass,
255 &X86::VR128RegClass, &X86::VR128RegClass,
256 &X86::VR128RegClass, &X86::VR128RegClass,
257 &X86::VR128RegClass, &X86::VR128RegClass, 0
262 return CalleeSavedRegClassesWin64;
264 return (callsEHReturn ?
265 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
267 return (callsEHReturn ?
268 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
272 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
273 BitVector Reserved(getNumRegs());
274 // Set the stack-pointer register and its aliases as reserved.
275 Reserved.set(X86::RSP);
276 Reserved.set(X86::ESP);
277 Reserved.set(X86::SP);
278 Reserved.set(X86::SPL);
279 // Set the frame-pointer register and its aliases as reserved if needed.
281 Reserved.set(X86::RBP);
282 Reserved.set(X86::EBP);
283 Reserved.set(X86::BP);
284 Reserved.set(X86::BPL);
286 // Mark the x87 stack registers as reserved, since they don't
287 // behave normally with respect to liveness. We don't fully
288 // model the effects of x87 stack pushes and pops after
290 Reserved.set(X86::ST0);
291 Reserved.set(X86::ST1);
292 Reserved.set(X86::ST2);
293 Reserved.set(X86::ST3);
294 Reserved.set(X86::ST4);
295 Reserved.set(X86::ST5);
296 Reserved.set(X86::ST6);
297 Reserved.set(X86::ST7);
301 //===----------------------------------------------------------------------===//
302 // Stack Frame Processing methods
303 //===----------------------------------------------------------------------===//
305 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
306 unsigned MaxAlign = 0;
307 for (int i = FFI->getObjectIndexBegin(),
308 e = FFI->getObjectIndexEnd(); i != e; ++i) {
309 if (FFI->isDeadObjectIndex(i))
311 unsigned Align = FFI->getObjectAlignment(i);
312 MaxAlign = std::max(MaxAlign, Align);
318 // hasFP - Return true if the specified function should have a dedicated frame
319 // pointer register. This is true if the function has variable sized allocas or
320 // if frame pointer elimination is disabled.
322 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
323 const MachineFrameInfo *MFI = MF.getFrameInfo();
324 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
326 return (NoFramePointerElim ||
327 needsStackRealignment(MF) ||
328 MFI->hasVarSizedObjects() ||
329 MFI->isFrameAddressTaken() ||
330 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
331 (MMI && MMI->callsUnwindInit()));
334 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
335 const MachineFrameInfo *MFI = MF.getFrameInfo();
337 // FIXME: Currently we don't support stack realignment for functions with
338 // variable-sized allocas
339 return (RealignStack &&
340 (MFI->getMaxAlignment() > StackAlign &&
341 !MFI->hasVarSizedObjects()));
344 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
345 return !MF.getFrameInfo()->hasVarSizedObjects();
348 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
349 int &FrameIdx) const {
350 if (Reg == FramePtr && hasFP(MF)) {
351 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
359 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
360 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
361 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
363 if (needsStackRealignment(MF)) {
365 // Skip the saved EBP
368 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
369 assert( (-(Offset + StackSize)) % Align == 0);
371 return Offset + StackSize;
374 // FIXME: Support tail calls
377 return Offset + StackSize;
379 // Skip the saved EBP
382 // Skip the RETADDR move area
383 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
384 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
385 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
391 void X86RegisterInfo::
392 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator I) const {
394 if (!hasReservedCallFrame(MF)) {
395 // If the stack pointer can be changed after prologue, turn the
396 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
397 // adjcallstackdown instruction into 'add ESP, <amt>'
398 // TODO: consider using push / pop instead of sub + store / add
399 MachineInstr *Old = I;
400 uint64_t Amount = Old->getOperand(0).getImm();
402 // We need to keep the stack aligned properly. To do this, we round the
403 // amount of space needed for the outgoing arguments up to the next
404 // alignment boundary.
405 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
407 MachineInstr *New = 0;
408 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
409 New = BuildMI(MF, Old->getDebugLoc(),
410 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
411 StackPtr).addReg(StackPtr).addImm(Amount);
413 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
414 // factor out the amount the callee already popped.
415 uint64_t CalleeAmt = Old->getOperand(1).getImm();
418 unsigned Opc = (Amount < 128) ?
419 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
420 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
421 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
422 .addReg(StackPtr).addImm(Amount);
427 // The EFLAGS implicit def is dead.
428 New->getOperand(3).setIsDead();
430 // Replace the pseudo instruction with a new instruction...
434 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
435 // If we are performing frame pointer elimination and if the callee pops
436 // something off the stack pointer, add it back. We do this until we have
437 // more advanced stack pointer tracking ability.
438 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
439 unsigned Opc = (CalleeAmt < 128) ?
440 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
441 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
442 MachineInstr *Old = I;
444 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
445 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
446 // The EFLAGS implicit def is dead.
447 New->getOperand(3).setIsDead();
456 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
457 int SPAdj, RegScavenger *RS) const{
458 assert(SPAdj == 0 && "Unexpected");
461 MachineInstr &MI = *II;
462 MachineFunction &MF = *MI.getParent()->getParent();
463 while (!MI.getOperand(i).isFI()) {
465 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
468 int FrameIndex = MI.getOperand(i).getIndex();
471 if (needsStackRealignment(MF))
472 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
474 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
476 // This must be part of a four operand memory reference. Replace the
477 // FrameIndex with base register with EBP. Add an offset to the offset.
478 MI.getOperand(i).ChangeToRegister(BasePtr, false);
480 // Now add the frame object offset to the offset from EBP.
481 if (MI.getOperand(i+3).isImm()) {
482 // Offset is a 32-bit integer.
483 int Offset = getFrameIndexOffset(MF, FrameIndex) +
484 (int)(MI.getOperand(i+3).getImm());
486 MI.getOperand(i+3).ChangeToImmediate(Offset);
488 // Offset is symbolic. This is extremely rare.
489 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
490 (uint64_t)MI.getOperand(i+3).getOffset();
491 MI.getOperand(i+3).setOffset(Offset);
496 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
497 RegScavenger *RS) const {
498 MachineFrameInfo *FFI = MF.getFrameInfo();
500 // Calculate and set max stack object alignment early, so we can decide
501 // whether we will need stack realignment (and thus FP).
502 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
503 calculateMaxStackAlignment(FFI));
505 FFI->setMaxAlignment(MaxAlign);
507 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
508 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
509 if (TailCallReturnAddrDelta < 0) {
510 // create RETURNADDR area
520 CreateFixedObject(-TailCallReturnAddrDelta,
521 (-1*SlotSize)+TailCallReturnAddrDelta);
524 assert((TailCallReturnAddrDelta <= 0) &&
525 "The Delta should always be zero or negative");
526 // Create a frame entry for the EBP register that must be saved.
527 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
529 TailCallReturnAddrDelta);
530 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
531 "Slot for EBP register must be last in order to be found!");
536 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
537 /// stack pointer by a constant value.
539 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
540 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
541 const TargetInstrInfo &TII) {
542 bool isSub = NumBytes < 0;
543 uint64_t Offset = isSub ? -NumBytes : NumBytes;
546 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
547 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
549 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
550 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
551 uint64_t Chunk = (1LL << 31) - 1;
552 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
553 DebugLoc::getUnknownLoc());
556 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
558 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
559 .addReg(StackPtr).addImm(ThisVal);
560 // The EFLAGS implicit def is dead.
561 MI->getOperand(3).setIsDead();
566 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
568 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
569 unsigned StackPtr, uint64_t *NumBytes = NULL) {
570 if (MBBI == MBB.begin()) return;
572 MachineBasicBlock::iterator PI = prior(MBBI);
573 unsigned Opc = PI->getOpcode();
574 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
575 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
576 PI->getOperand(0).getReg() == StackPtr) {
578 *NumBytes += PI->getOperand(2).getImm();
580 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
581 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
582 PI->getOperand(0).getReg() == StackPtr) {
584 *NumBytes -= PI->getOperand(2).getImm();
589 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
591 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
592 MachineBasicBlock::iterator &MBBI,
593 unsigned StackPtr, uint64_t *NumBytes = NULL) {
596 if (MBBI == MBB.end()) return;
598 MachineBasicBlock::iterator NI = next(MBBI);
599 if (NI == MBB.end()) return;
601 unsigned Opc = NI->getOpcode();
602 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
603 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
604 NI->getOperand(0).getReg() == StackPtr) {
606 *NumBytes -= NI->getOperand(2).getImm();
609 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
610 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
611 NI->getOperand(0).getReg() == StackPtr) {
613 *NumBytes += NI->getOperand(2).getImm();
619 /// mergeSPUpdates - Checks the instruction before/after the passed
620 /// instruction. If it is an ADD/SUB instruction it is deleted
621 /// argument and the stack adjustment is returned as a positive value for ADD
622 /// and a negative for SUB.
623 static int mergeSPUpdates(MachineBasicBlock &MBB,
624 MachineBasicBlock::iterator &MBBI,
626 bool doMergeWithPrevious) {
628 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
629 (!doMergeWithPrevious && MBBI == MBB.end()))
634 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
635 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
636 unsigned Opc = PI->getOpcode();
637 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
638 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
639 PI->getOperand(0).getReg() == StackPtr){
640 Offset += PI->getOperand(2).getImm();
642 if (!doMergeWithPrevious) MBBI = NI;
643 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
644 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
645 PI->getOperand(0).getReg() == StackPtr) {
646 Offset -= PI->getOperand(2).getImm();
648 if (!doMergeWithPrevious) MBBI = NI;
654 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
656 unsigned FramePtr) const {
657 MachineFrameInfo *MFI = MF.getFrameInfo();
658 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
661 // Add callee saved registers to move list.
662 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
663 if (CSI.empty()) return;
665 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
666 const TargetData *TD = MF.getTarget().getTargetData();
667 bool HasFP = hasFP(MF);
669 // Calculate amount of bytes used for return address storing
671 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
672 TargetFrameInfo::StackGrowsUp ?
673 TD->getPointerSize() : -TD->getPointerSize());
675 // FIXME: This is dirty hack. The code itself is pretty mess right now.
676 // It should be rewritten from scratch and generalized sometimes.
678 // Determine maximum offset (minumum due to stack growth)
679 int64_t MaxOffset = 0;
680 for (std::vector<CalleeSavedInfo>::const_iterator
681 I = CSI.begin(), E = CSI.end(); I != E; ++I)
682 MaxOffset = std::min(MaxOffset,
683 MFI->getObjectOffset(I->getFrameIdx()));
685 // Calculate offsets.
686 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
687 for (std::vector<CalleeSavedInfo>::const_iterator
688 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
689 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
690 unsigned Reg = I->getReg();
691 Offset = MaxOffset - Offset + saveAreaOffset;
693 // Don't output a new machine move if we're re-saving the frame
694 // pointer. This happens when the PrologEpilogInserter has inserted an extra
695 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
696 // generates one when frame pointers are used. If we generate a "machine
697 // move" for this extra "PUSH", the linker will lose track of the fact that
698 // the frame pointer should have the value of the first "PUSH" when it's
701 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
702 // another bug. I.e., one where we generate a prolog like this:
710 // The immediate re-push of EBP is unnecessary. At the least, it's an
711 // optimization bug. EBP can be used as a scratch register in certain
712 // cases, but probably not when we have a frame pointer.
713 if (HasFP && FramePtr == Reg)
716 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
717 MachineLocation CSSrc(Reg);
718 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
722 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
723 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
724 MachineFrameInfo *MFI = MF.getFrameInfo();
725 const Function* Fn = MF.getFunction();
726 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
727 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
728 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
729 MachineBasicBlock::iterator MBBI = MBB.begin();
730 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
731 !Fn->doesNotThrow() ||
732 UnwindTablesMandatory;
733 bool HasFP = hasFP(MF);
736 // Get the number of bytes to allocate from the FrameInfo.
737 uint64_t StackSize = MFI->getStackSize();
739 // Get desired stack alignment
740 uint64_t MaxAlign = MFI->getMaxAlignment();
742 // Add RETADDR move area to callee saved frame size.
743 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
744 if (TailCallReturnAddrDelta < 0)
745 X86FI->setCalleeSavedFrameSize(
746 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
748 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
749 // function, and use up to 128 bytes of stack space, don't have a frame
750 // pointer, calls, or dynamic alloca then we do not need to adjust the
751 // stack pointer (we fit in the Red Zone).
752 bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
753 if (Is64Bit && !DisableRedZone &&
754 !needsStackRealignment(MF) &&
755 !MFI->hasVarSizedObjects() && // No dynamic alloca.
756 !MFI->hasCalls() && // No calls.
757 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
758 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
759 if (HasFP) MinSize += SlotSize;
760 StackSize = std::max(MinSize,
761 StackSize > 128 ? StackSize - 128 : 0);
762 MFI->setStackSize(StackSize);
765 // Insert stack pointer adjustment for later moving of return addr. Only
766 // applies to tail call optimized functions where the callee argument stack
767 // size is bigger than the callers.
768 if (TailCallReturnAddrDelta < 0) {
770 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
771 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
772 // The EFLAGS implicit def is dead.
773 MI->getOperand(3).setIsDead();
776 // uint64_t StackSize = MFI->getStackSize();
777 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
778 const TargetData *TD = MF.getTarget().getTargetData();
780 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
781 TargetFrameInfo::StackGrowsUp ?
782 TD->getPointerSize() : -TD->getPointerSize());
784 uint64_t NumBytes = 0;
786 // Calculate required stack adjustment
787 uint64_t FrameSize = StackSize - SlotSize;
788 if (needsStackRealignment(MF))
789 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
791 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
793 // Get the offset of the stack slot for the EBP register, which is
794 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
795 // Update the frame offset adjustment.
796 MFI->setOffsetAdjustment(-NumBytes);
798 // Save EBP/RBP into the appropriate stack slot...
799 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
800 .addReg(FramePtr, RegState::Kill);
802 if (needsFrameMoves) {
803 // Mark effective beginning of when frame pointer becomes valid.
804 unsigned FrameLabelId = MMI->NextLabelID();
805 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
807 // Define the current CFA rule to use the provided offset.
809 MachineLocation SPDst(MachineLocation::VirtualFP);
810 MachineLocation SPSrc(MachineLocation::VirtualFP,
811 HasFP ? 2 * stackGrowth :
812 -StackSize + stackGrowth);
813 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
815 // FIXME: Verify & implement for FP
816 MachineLocation SPDst(StackPtr);
817 MachineLocation SPSrc(StackPtr, stackGrowth);
818 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
821 // Change the rule for the FramePtr to be an "offset" rule.
822 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
823 MachineLocation FPSrc(FramePtr);
824 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
827 // Update EBP with the new base value...
828 BuildMI(MBB, MBBI, DL,
829 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
832 if (needsFrameMoves) {
833 unsigned FrameLabelId = MMI->NextLabelID();
834 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
836 // Define the current CFA to use the EBP/RBP register.
837 MachineLocation FPDst(FramePtr);
838 MachineLocation FPSrc(MachineLocation::VirtualFP);
839 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
842 // Mark the FramePtr as live-in in every block except the entry.
843 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
845 I->addLiveIn(FramePtr);
848 if (needsStackRealignment(MF)) {
850 BuildMI(MBB, MBBI, DL,
851 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
852 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
854 // The EFLAGS implicit def is dead.
855 MI->getOperand(3).setIsDead();
858 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
861 // Skip the callee-saved push instructions.
862 bool RegsSaved = false;
863 while (MBBI != MBB.end() &&
864 (MBBI->getOpcode() == X86::PUSH32r ||
865 MBBI->getOpcode() == X86::PUSH64r)) {
870 if (RegsSaved && needsFrameMoves) {
871 // Mark end of callee-saved push instructions.
872 unsigned LabelId = MMI->NextLabelID();
873 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
875 // Emit DWARF info specifying the offsets of the callee-saved registers.
876 emitCalleeSavedFrameMoves(MF, LabelId, FramePtr);
879 if (MBBI != MBB.end())
880 DL = MBBI->getDebugLoc();
882 // Adjust stack pointer: ESP -= numbytes.
883 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
884 // Check, whether EAX is livein for this function.
885 bool isEAXAlive = false;
886 for (MachineRegisterInfo::livein_iterator
887 II = MF.getRegInfo().livein_begin(),
888 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
889 unsigned Reg = II->first;
890 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
891 Reg == X86::AH || Reg == X86::AL);
894 // Function prologue calls _alloca to probe the stack when allocating more
895 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
896 // to ensure that the guard pages used by the OS virtual memory manager are
897 // allocated in correct sequence.
899 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
901 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
902 .addExternalSymbol("_alloca");
905 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
906 .addReg(X86::EAX, RegState::Kill);
908 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
909 // allocated bytes for EAX.
910 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
911 .addImm(NumBytes - 4);
912 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
913 .addExternalSymbol("_alloca");
916 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
918 StackPtr, false, NumBytes - 4);
919 MBB.insert(MBBI, MI);
921 } else if (NumBytes) {
922 // If there is an SUB32ri of ESP immediately before this instruction, merge
923 // the two. This can be the case when tail call elimination is enabled and
924 // the callee has more arguments then the caller.
925 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
927 // If there is an ADD32ri or SUB32ri of ESP immediately after this
928 // instruction, merge the two instructions.
929 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
932 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
936 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
937 MachineBasicBlock &MBB) const {
938 const MachineFrameInfo *MFI = MF.getFrameInfo();
939 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
940 MachineBasicBlock::iterator MBBI = prior(MBB.end());
941 unsigned RetOpcode = MBBI->getOpcode();
942 DebugLoc DL = MBBI->getDebugLoc();
947 case X86::TCRETURNdi:
948 case X86::TCRETURNri:
949 case X86::TCRETURNri64:
950 case X86::TCRETURNdi64:
952 case X86::EH_RETURN64:
955 case X86::TAILJMPm: break; // These are ok
957 assert(0 && "Can only insert epilog into returning blocks");
960 // Get the number of bytes to allocate from the FrameInfo
961 uint64_t StackSize = MFI->getStackSize();
962 uint64_t MaxAlign = MFI->getMaxAlignment();
963 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
964 uint64_t NumBytes = 0;
967 // Calculate required stack adjustment
968 uint64_t FrameSize = StackSize - SlotSize;
969 if (needsStackRealignment(MF))
970 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
972 NumBytes = FrameSize - CSSize;
975 BuildMI(MBB, MBBI, DL,
976 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
978 NumBytes = StackSize - CSSize;
981 // Skip the callee-saved pop instructions.
982 MachineBasicBlock::iterator LastCSPop = MBBI;
983 while (MBBI != MBB.begin()) {
984 MachineBasicBlock::iterator PI = prior(MBBI);
985 unsigned Opc = PI->getOpcode();
986 if (Opc != X86::POP32r && Opc != X86::POP64r &&
987 !PI->getDesc().isTerminator())
992 DL = MBBI->getDebugLoc();
994 // If there is an ADD32ri or SUB32ri of ESP immediately before this
995 // instruction, merge the two instructions.
996 if (NumBytes || MFI->hasVarSizedObjects())
997 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
999 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1000 // slot before popping them off! Same applies for the case, when stack was
1002 if (needsStackRealignment(MF)) {
1003 // We cannot use LEA here, because stack pointer was realigned. We need to
1004 // deallocate local frame back
1006 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1007 MBBI = prior(LastCSPop);
1010 BuildMI(MBB, MBBI, DL,
1011 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1012 StackPtr).addReg(FramePtr);
1013 } else if (MFI->hasVarSizedObjects()) {
1015 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1016 MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1017 FramePtr, false, -CSSize);
1018 MBB.insert(MBBI, MI);
1020 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1021 StackPtr).addReg(FramePtr);
1024 // adjust stack pointer back: ESP += numbytes
1026 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1029 // We're returning from function via eh_return.
1030 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1031 MBBI = prior(MBB.end());
1032 MachineOperand &DestAddr = MBBI->getOperand(0);
1033 assert(DestAddr.isReg() && "Offset should be in register!");
1034 BuildMI(MBB, MBBI, DL,
1035 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1036 StackPtr).addReg(DestAddr.getReg());
1037 // Tail call return: adjust the stack pointer and jump to callee
1038 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1039 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1040 MBBI = prior(MBB.end());
1041 MachineOperand &JumpTarget = MBBI->getOperand(0);
1042 MachineOperand &StackAdjust = MBBI->getOperand(1);
1043 assert(StackAdjust.isImm() && "Expecting immediate value.");
1045 // Adjust stack pointer.
1046 int StackAdj = StackAdjust.getImm();
1047 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1049 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1050 // Incoporate the retaddr area.
1051 Offset = StackAdj-MaxTCDelta;
1052 assert(Offset >= 0 && "Offset should never be negative");
1055 // Check for possible merge with preceeding ADD instruction.
1056 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1057 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1060 // Jump to label or value in register.
1061 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1062 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1063 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1064 else if (RetOpcode== X86::TCRETURNri64)
1065 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1067 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1069 // Delete the pseudo instruction TCRETURN.
1071 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1072 (X86FI->getTCReturnAddrDelta() < 0)) {
1073 // Add the return addr area delta back since we are not tail calling.
1074 int delta = -1*X86FI->getTCReturnAddrDelta();
1075 MBBI = prior(MBB.end());
1076 // Check for possible merge with preceeding ADD instruction.
1077 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1078 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1082 unsigned X86RegisterInfo::getRARegister() const {
1084 return X86::RIP; // Should have dwarf #16
1086 return X86::EIP; // Should have dwarf #8
1089 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1090 return hasFP(MF) ? FramePtr : StackPtr;
1093 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1095 // Calculate amount of bytes used for return address storing
1096 int stackGrowth = (Is64Bit ? -8 : -4);
1098 // Initial state of the frame pointer is esp+4.
1099 MachineLocation Dst(MachineLocation::VirtualFP);
1100 MachineLocation Src(StackPtr, stackGrowth);
1101 Moves.push_back(MachineMove(0, Dst, Src));
1103 // Add return address to move list
1104 MachineLocation CSDst(StackPtr, stackGrowth);
1105 MachineLocation CSSrc(getRARegister());
1106 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1109 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1110 assert(0 && "What is the exception register");
1114 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1115 assert(0 && "What is the exception handler register");
1120 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1121 switch (VT.getSimpleVT()) {
1122 default: return Reg;
1127 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1129 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1131 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1133 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1139 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1141 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1143 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1145 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1147 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1149 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1151 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1153 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1155 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1157 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1159 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1161 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1163 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1165 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1167 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1169 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1175 default: return Reg;
1176 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1178 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1180 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1182 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1184 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1186 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1188 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1190 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1192 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1194 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1196 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1198 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1200 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1202 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1204 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1206 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1211 default: return Reg;
1212 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1214 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1216 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1218 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1220 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1222 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1224 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1226 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1228 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1230 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1232 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1234 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1236 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1238 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1240 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1242 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1247 default: return Reg;
1248 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1250 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1252 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1254 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1256 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1258 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1260 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1262 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1264 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1266 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1268 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1270 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1272 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1274 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1276 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1278 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1287 #include "X86GenRegisterInfo.inc"
1290 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1292 MSAC() : MachineFunctionPass(&ID) {}
1294 virtual bool runOnMachineFunction(MachineFunction &MF) {
1295 MachineFrameInfo *FFI = MF.getFrameInfo();
1296 MachineRegisterInfo &RI = MF.getRegInfo();
1298 // Calculate max stack alignment of all already allocated stack objects.
1299 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1301 // Be over-conservative: scan over all vreg defs and find, whether vector
1302 // registers are used. If yes - there is probability, that vector register
1303 // will be spilled and thus stack needs to be aligned properly.
1304 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1305 RegNum < RI.getLastVirtReg(); ++RegNum)
1306 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1308 FFI->setMaxAlignment(MaxAlign);
1313 virtual const char *getPassName() const {
1314 return "X86 Maximal Stack Alignment Calculator";
1322 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }