1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
551 string asm_opr, Domain d = GenericDomain> {
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr,
569 Domain d = GenericDomain> {
571 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
572 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
575 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
576 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
577 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
578 VEX, VEX_LIG, Sched<[WriteStore]>;
580 let Constraints = "$src1 = $dst" in {
581 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
582 "\t{$src2, $dst|$dst, $src2}", d>;
585 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
587 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
591 // Loading from memory automatically zeroing upper bits.
592 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
593 PatFrag mem_pat, string OpcodeStr,
594 Domain d = GenericDomain> {
595 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
597 [(set RC:$dst, (mem_pat addr:$src))],
598 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
599 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
601 [(set RC:$dst, (mem_pat addr:$src))],
602 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
605 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
606 SSEPackedSingle>, XS;
607 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
608 SSEPackedDouble>, XD;
610 let canFoldAsLoad = 1, isReMaterializable = 1 in {
611 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
612 SSEPackedSingle>, XS;
614 let AddedComplexity = 20 in
615 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
616 SSEPackedDouble>, XD;
620 let Predicates = [UseAVX] in {
621 let AddedComplexity = 20 in {
622 // MOVSSrm zeros the high parts of the register; represent this
623 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
624 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
628 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
629 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
631 // MOVSDrm zeros the high parts of the register; represent this
632 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
633 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
641 def : Pat<(v2f64 (X86vzload addr:$src)),
642 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
644 // Represent the same patterns above but in the form they appear for
646 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
647 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
649 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
650 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
651 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
652 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
653 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
654 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
656 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
657 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
658 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
660 // Extract and store.
661 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
663 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
664 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
666 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
668 // Shuffle with VMOVSS
669 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
670 (VMOVSSrr (v4i32 VR128:$src1),
671 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
672 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
673 (VMOVSSrr (v4f32 VR128:$src1),
674 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
677 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
678 (SUBREG_TO_REG (i32 0),
679 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
680 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
682 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
683 (SUBREG_TO_REG (i32 0),
684 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
685 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
688 // Shuffle with VMOVSD
689 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
692 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
694 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
695 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
696 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
699 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
700 (SUBREG_TO_REG (i32 0),
701 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
702 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
704 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
705 (SUBREG_TO_REG (i32 0),
706 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
707 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
710 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
711 // is during lowering, where it's not possible to recognize the fold cause
712 // it has two uses through a bitcast. One use disappears at isel time and the
713 // fold opportunity reappears.
714 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
717 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
719 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
720 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
721 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
724 let Predicates = [UseSSE1] in {
725 let Predicates = [NoSSE41], AddedComplexity = 15 in {
726 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
727 // MOVSS to the lower bits.
728 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
729 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
730 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
731 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
732 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
733 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
736 let AddedComplexity = 20 in {
737 // MOVSSrm already zeros the high parts of the register.
738 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
739 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
741 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
742 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
743 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
746 // Extract and store.
747 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
749 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
751 // Shuffle with MOVSS
752 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
753 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
754 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
755 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
758 let Predicates = [UseSSE2] in {
759 let Predicates = [NoSSE41], AddedComplexity = 15 in {
760 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
761 // MOVSD to the lower bits.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
763 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
766 let AddedComplexity = 20 in {
767 // MOVSDrm already zeros the high parts of the register.
768 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
773 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
775 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
776 def : Pat<(v2f64 (X86vzload addr:$src)),
777 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
780 // Extract and store.
781 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
783 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
785 // Shuffle with MOVSD
786 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
790 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
791 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
792 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
793 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
796 // is during lowering, where it's not possible to recognize the fold cause
797 // it has two uses through a bitcast. One use disappears at isel time and the
798 // fold opportunity reappears.
799 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
802 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
804 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
805 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
806 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
809 //===----------------------------------------------------------------------===//
810 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
811 //===----------------------------------------------------------------------===//
813 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
814 X86MemOperand x86memop, PatFrag ld_frag,
815 string asm, Domain d,
817 bit IsReMaterializable = 1> {
818 let hasSideEffects = 0 in
819 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
820 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
821 Sched<[WriteFShuffle]>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
829 let Predicates = [HasAVX, NoVLX] in {
830 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
831 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
833 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
834 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
836 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
837 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
839 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
840 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
843 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
844 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
846 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
847 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
849 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
850 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
852 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
853 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
857 let Predicates = [UseSSE1] in {
858 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
859 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
861 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
862 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
865 let Predicates = [UseSSE2] in {
866 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
867 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
869 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
870 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
874 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
875 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movaps\t{$src, $dst|$dst, $src}",
877 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVA_P_MR>, VEX;
879 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movapd\t{$src, $dst|$dst, $src}",
881 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVA_P_MR>, VEX;
883 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
884 "movups\t{$src, $dst|$dst, $src}",
885 [(store (v4f32 VR128:$src), addr:$dst)],
886 IIC_SSE_MOVU_P_MR>, VEX;
887 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
888 "movupd\t{$src, $dst|$dst, $src}",
889 [(store (v2f64 VR128:$src), addr:$dst)],
890 IIC_SSE_MOVU_P_MR>, VEX;
891 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movaps\t{$src, $dst|$dst, $src}",
893 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
895 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movapd\t{$src, $dst|$dst, $src}",
897 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
899 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
900 "movups\t{$src, $dst|$dst, $src}",
901 [(store (v8f32 VR256:$src), addr:$dst)],
902 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
903 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
904 "movupd\t{$src, $dst|$dst, $src}",
905 [(store (v4f64 VR256:$src), addr:$dst)],
906 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
910 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
911 SchedRW = [WriteFShuffle] in {
912 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
914 "movaps\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVA_P_RR>, VEX;
916 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
918 "movapd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVA_P_RR>, VEX;
920 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
922 "movups\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVU_P_RR>, VEX;
924 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
926 "movupd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVU_P_RR>, VEX;
928 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
930 "movaps\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
932 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
934 "movapd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
936 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
938 "movups\t{$src, $dst|$dst, $src}", [],
939 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
942 "movupd\t{$src, $dst|$dst, $src}", [],
943 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
946 let Predicates = [HasAVX] in {
947 def : Pat<(v8i32 (X86vzmovl
948 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
949 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
950 def : Pat<(v4i64 (X86vzmovl
951 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
952 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
953 def : Pat<(v8f32 (X86vzmovl
954 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
955 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
956 def : Pat<(v4f64 (X86vzmovl
957 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
958 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
962 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
963 (VMOVUPSYmr addr:$dst, VR256:$src)>;
964 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
965 (VMOVUPDYmr addr:$dst, VR256:$src)>;
967 let SchedRW = [WriteStore] in {
968 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movaps\t{$src, $dst|$dst, $src}",
970 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
972 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movapd\t{$src, $dst|$dst, $src}",
974 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
976 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
977 "movups\t{$src, $dst|$dst, $src}",
978 [(store (v4f32 VR128:$src), addr:$dst)],
980 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
981 "movupd\t{$src, $dst|$dst, $src}",
982 [(store (v2f64 VR128:$src), addr:$dst)],
987 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
988 SchedRW = [WriteFShuffle] in {
989 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
990 "movaps\t{$src, $dst|$dst, $src}", [],
992 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
993 "movapd\t{$src, $dst|$dst, $src}", [],
995 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
996 "movups\t{$src, $dst|$dst, $src}", [],
998 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
999 "movupd\t{$src, $dst|$dst, $src}", [],
1003 let Predicates = [HasAVX] in {
1004 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1005 (VMOVUPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (VMOVUPDmr addr:$dst, VR128:$src)>;
1010 let Predicates = [UseSSE1] in
1011 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1012 (MOVUPSmr addr:$dst, VR128:$src)>;
1013 let Predicates = [UseSSE2] in
1014 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1015 (MOVUPDmr addr:$dst, VR128:$src)>;
1017 // Use vmovaps/vmovups for AVX integer load/store.
1018 let Predicates = [HasAVX, NoVLX] in {
1019 // 128-bit load/store
1020 def : Pat<(alignedloadv2i64 addr:$src),
1021 (VMOVAPSrm addr:$src)>;
1022 def : Pat<(loadv2i64 addr:$src),
1023 (VMOVUPSrm addr:$src)>;
1025 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1026 (VMOVAPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1028 (VMOVAPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1030 (VMOVAPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1032 (VMOVAPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1034 (VMOVUPSmr addr:$dst, VR128:$src)>;
1035 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1036 (VMOVUPSmr addr:$dst, VR128:$src)>;
1037 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1038 (VMOVUPSmr addr:$dst, VR128:$src)>;
1039 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1040 (VMOVUPSmr addr:$dst, VR128:$src)>;
1042 // 256-bit load/store
1043 def : Pat<(alignedloadv4i64 addr:$src),
1044 (VMOVAPSYrm addr:$src)>;
1045 def : Pat<(loadv4i64 addr:$src),
1046 (VMOVUPSYrm addr:$src)>;
1047 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1050 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1052 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1054 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1055 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1056 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1057 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1058 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1059 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1060 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1061 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1062 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1064 // Special patterns for storing subvector extracts of lower 128-bits
1065 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1066 def : Pat<(alignedstore (v2f64 (extract_subvector
1067 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(alignedstore (v4f32 (extract_subvector
1070 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(alignedstore (v2i64 (extract_subvector
1073 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(alignedstore (v4i32 (extract_subvector
1076 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 def : Pat<(alignedstore (v8i16 (extract_subvector
1079 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1080 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1081 def : Pat<(alignedstore (v16i8 (extract_subvector
1082 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1083 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1085 def : Pat<(store (v2f64 (extract_subvector
1086 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1087 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1088 def : Pat<(store (v4f32 (extract_subvector
1089 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1090 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1091 def : Pat<(store (v2i64 (extract_subvector
1092 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1093 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1094 def : Pat<(store (v4i32 (extract_subvector
1095 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1096 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 def : Pat<(store (v8i16 (extract_subvector
1098 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1099 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1100 def : Pat<(store (v16i8 (extract_subvector
1101 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1102 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1105 // Use movaps / movups for SSE integer load / store (one byte shorter).
1106 // The instructions selected below are then converted to MOVDQA/MOVDQU
1107 // during the SSE domain pass.
1108 let Predicates = [UseSSE1] in {
1109 def : Pat<(alignedloadv2i64 addr:$src),
1110 (MOVAPSrm addr:$src)>;
1111 def : Pat<(loadv2i64 addr:$src),
1112 (MOVUPSrm addr:$src)>;
1114 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1115 (MOVAPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1117 (MOVAPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1119 (MOVAPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1121 (MOVAPSmr addr:$dst, VR128:$src)>;
1122 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1123 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1125 (MOVUPSmr addr:$dst, VR128:$src)>;
1126 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1127 (MOVUPSmr addr:$dst, VR128:$src)>;
1128 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1129 (MOVUPSmr addr:$dst, VR128:$src)>;
1132 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1133 // bits are disregarded. FIXME: Set encoding to pseudo!
1134 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1135 let isCodeGenOnly = 1 in {
1136 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1139 IIC_SSE_MOVA_P_RM>, VEX;
1140 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1143 IIC_SSE_MOVA_P_RM>, VEX;
1144 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1145 "movaps\t{$src, $dst|$dst, $src}",
1146 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1148 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1149 "movapd\t{$src, $dst|$dst, $src}",
1150 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1155 //===----------------------------------------------------------------------===//
1156 // SSE 1 & 2 - Move Low packed FP Instructions
1157 //===----------------------------------------------------------------------===//
1159 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1160 string base_opc, string asm_opr,
1161 InstrItinClass itin> {
1162 def PSrm : PI<opc, MRMSrcMem,
1163 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1164 !strconcat(base_opc, "s", asm_opr),
1166 (psnode VR128:$src1,
1167 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1168 itin, SSEPackedSingle>, PS,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1171 def PDrm : PI<opc, MRMSrcMem,
1172 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1173 !strconcat(base_opc, "d", asm_opr),
1174 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1175 (scalar_to_vector (loadf64 addr:$src2)))))],
1176 itin, SSEPackedDouble>, PD,
1177 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1181 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1182 string base_opc, InstrItinClass itin> {
1183 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1187 let Constraints = "$src1 = $dst" in
1188 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1189 "\t{$src2, $dst|$dst, $src2}",
1193 let AddedComplexity = 20 in {
1194 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1198 let SchedRW = [WriteStore] in {
1199 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1200 "movlps\t{$src, $dst|$dst, $src}",
1201 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1202 (iPTR 0))), addr:$dst)],
1203 IIC_SSE_MOV_LH>, VEX;
1204 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1205 "movlpd\t{$src, $dst|$dst, $src}",
1206 [(store (f64 (vector_extract (v2f64 VR128:$src),
1207 (iPTR 0))), addr:$dst)],
1208 IIC_SSE_MOV_LH>, VEX;
1209 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1210 "movlps\t{$src, $dst|$dst, $src}",
1211 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1212 (iPTR 0))), addr:$dst)],
1214 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1215 "movlpd\t{$src, $dst|$dst, $src}",
1216 [(store (f64 (vector_extract (v2f64 VR128:$src),
1217 (iPTR 0))), addr:$dst)],
1221 let Predicates = [HasAVX] in {
1222 // Shuffle with VMOVLPS
1223 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1224 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1226 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1228 // Shuffle with VMOVLPD
1229 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1230 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1231 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1232 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1233 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1234 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1235 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1238 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1240 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v4i32 (X86Movlps
1242 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1243 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1244 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1246 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1247 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1252 let Predicates = [UseSSE1] in {
1253 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1254 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1255 (iPTR 0))), addr:$src1),
1256 (MOVLPSmr addr:$src1, VR128:$src2)>;
1258 // Shuffle with MOVLPS
1259 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1260 (MOVLPSrm VR128:$src1, addr:$src2)>;
1261 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1262 (MOVLPSrm VR128:$src1, addr:$src2)>;
1263 def : Pat<(X86Movlps VR128:$src1,
1264 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1265 (MOVLPSrm VR128:$src1, addr:$src2)>;
1268 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1270 (MOVLPSmr addr:$src1, VR128:$src2)>;
1271 def : Pat<(store (v4i32 (X86Movlps
1272 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1274 (MOVLPSmr addr:$src1, VR128:$src2)>;
1277 let Predicates = [UseSSE2] in {
1278 // Shuffle with MOVLPD
1279 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1280 (MOVLPDrm VR128:$src1, addr:$src2)>;
1281 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1282 (MOVLPDrm VR128:$src1, addr:$src2)>;
1283 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1284 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1285 (MOVLPDrm VR128:$src1, addr:$src2)>;
1288 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1290 (MOVLPDmr addr:$src1, VR128:$src2)>;
1291 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1293 (MOVLPDmr addr:$src1, VR128:$src2)>;
1296 //===----------------------------------------------------------------------===//
1297 // SSE 1 & 2 - Move Hi packed FP Instructions
1298 //===----------------------------------------------------------------------===//
1300 let AddedComplexity = 20 in {
1301 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1305 let SchedRW = [WriteStore] in {
1306 // v2f64 extract element 1 is always custom lowered to unpack high to low
1307 // and extract element 0 so the non-store version isn't too horrible.
1308 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhps\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (vector_extract
1311 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1312 (bc_v2f64 (v4f32 VR128:$src))),
1313 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1314 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1315 "movhpd\t{$src, $dst|$dst, $src}",
1316 [(store (f64 (vector_extract
1317 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1319 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1320 "movhps\t{$src, $dst|$dst, $src}",
1321 [(store (f64 (vector_extract
1322 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1323 (bc_v2f64 (v4f32 VR128:$src))),
1324 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1325 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1326 "movhpd\t{$src, $dst|$dst, $src}",
1327 [(store (f64 (vector_extract
1328 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1329 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1332 let Predicates = [HasAVX] in {
1334 def : Pat<(X86Movlhps VR128:$src1,
1335 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1336 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1337 def : Pat<(X86Movlhps VR128:$src1,
1338 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1339 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1343 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1344 // is during lowering, where it's not possible to recognize the load fold
1345 // cause it has two uses through a bitcast. One use disappears at isel time
1346 // and the fold opportunity reappears.
1347 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1348 (scalar_to_vector (loadf64 addr:$src2)))),
1349 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1350 // Also handle an i64 load because that may get selected as a faster way to
1352 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1353 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1354 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1356 def : Pat<(store (f64 (vector_extract
1357 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1358 (iPTR 0))), addr:$dst),
1359 (VMOVHPDmr addr:$dst, VR128:$src)>;
1362 let Predicates = [UseSSE1] in {
1364 def : Pat<(X86Movlhps VR128:$src1,
1365 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1366 (MOVHPSrm VR128:$src1, addr:$src2)>;
1367 def : Pat<(X86Movlhps VR128:$src1,
1368 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1369 (MOVHPSrm VR128:$src1, addr:$src2)>;
1372 let Predicates = [UseSSE2] in {
1375 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1376 // is during lowering, where it's not possible to recognize the load fold
1377 // cause it has two uses through a bitcast. One use disappears at isel time
1378 // and the fold opportunity reappears.
1379 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1380 (scalar_to_vector (loadf64 addr:$src2)))),
1381 (MOVHPDrm VR128:$src1, addr:$src2)>;
1382 // Also handle an i64 load because that may get selected as a faster way to
1384 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1385 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1386 (MOVHPDrm VR128:$src1, addr:$src2)>;
1388 def : Pat<(store (f64 (vector_extract
1389 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1390 (iPTR 0))), addr:$dst),
1391 (MOVHPDmr addr:$dst, VR128:$src)>;
1394 //===----------------------------------------------------------------------===//
1395 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1396 //===----------------------------------------------------------------------===//
1398 let AddedComplexity = 20, Predicates = [UseAVX] in {
1399 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1400 (ins VR128:$src1, VR128:$src2),
1401 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1403 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1405 VEX_4V, Sched<[WriteFShuffle]>;
1406 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1407 (ins VR128:$src1, VR128:$src2),
1408 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1410 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1412 VEX_4V, Sched<[WriteFShuffle]>;
1414 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1415 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1416 (ins VR128:$src1, VR128:$src2),
1417 "movlhps\t{$src2, $dst|$dst, $src2}",
1419 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1420 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1422 (ins VR128:$src1, VR128:$src2),
1423 "movhlps\t{$src2, $dst|$dst, $src2}",
1425 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1426 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1429 let Predicates = [UseAVX] in {
1431 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1432 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1433 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1434 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1437 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1438 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1441 let Predicates = [UseSSE1] in {
1443 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1444 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1445 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1446 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1449 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1450 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1453 //===----------------------------------------------------------------------===//
1454 // SSE 1 & 2 - Conversion Instructions
1455 //===----------------------------------------------------------------------===//
1457 def SSE_CVT_PD : OpndItins<
1458 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1461 let Sched = WriteCvtI2F in
1462 def SSE_CVT_PS : OpndItins<
1463 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1466 let Sched = WriteCvtI2F in
1467 def SSE_CVT_Scalar : OpndItins<
1468 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1471 let Sched = WriteCvtF2I in
1472 def SSE_CVT_SS2SI_32 : OpndItins<
1473 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1476 let Sched = WriteCvtF2I in
1477 def SSE_CVT_SS2SI_64 : OpndItins<
1478 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1481 let Sched = WriteCvtF2I in
1482 def SSE_CVT_SD2SI : OpndItins<
1483 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1486 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1487 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1488 string asm, OpndItins itins> {
1489 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1490 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1491 itins.rr>, Sched<[itins.Sched]>;
1492 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1493 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1494 itins.rm>, Sched<[itins.Sched.Folded]>;
1497 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1498 X86MemOperand x86memop, string asm, Domain d,
1500 let hasSideEffects = 0 in {
1501 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1502 [], itins.rr, d>, Sched<[itins.Sched]>;
1504 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1505 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1509 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1510 X86MemOperand x86memop, string asm> {
1511 let hasSideEffects = 0, Predicates = [UseAVX] in {
1512 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1513 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1514 Sched<[WriteCvtI2F]>;
1516 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1517 (ins DstRC:$src1, x86memop:$src),
1518 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1519 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1520 } // hasSideEffects = 0
1523 let Predicates = [UseAVX] in {
1524 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1525 "cvttss2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1529 "cvttss2si\t{$src, $dst|$dst, $src}",
1531 XS, VEX, VEX_W, VEX_LIG;
1532 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1533 "cvttsd2si\t{$src, $dst|$dst, $src}",
1536 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1537 "cvttsd2si\t{$src, $dst|$dst, $src}",
1539 XD, VEX, VEX_W, VEX_LIG;
1541 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1549 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1550 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1551 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1552 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1553 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1554 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1555 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1556 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1558 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1559 // register, but the same isn't true when only using memory operands,
1560 // provide other assembly "l" and "q" forms to address this explicitly
1561 // where appropriate to do so.
1562 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1563 XS, VEX_4V, VEX_LIG;
1564 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1565 XS, VEX_4V, VEX_W, VEX_LIG;
1566 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1567 XD, VEX_4V, VEX_LIG;
1568 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1569 XD, VEX_4V, VEX_W, VEX_LIG;
1571 let Predicates = [UseAVX] in {
1572 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1573 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1574 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1575 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1577 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1578 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1579 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1580 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1581 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1582 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1583 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1584 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1586 def : Pat<(f32 (sint_to_fp GR32:$src)),
1587 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1588 def : Pat<(f32 (sint_to_fp GR64:$src)),
1589 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1590 def : Pat<(f64 (sint_to_fp GR32:$src)),
1591 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1592 def : Pat<(f64 (sint_to_fp GR64:$src)),
1593 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1596 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1597 "cvttss2si\t{$src, $dst|$dst, $src}",
1598 SSE_CVT_SS2SI_32>, XS;
1599 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1600 "cvttss2si\t{$src, $dst|$dst, $src}",
1601 SSE_CVT_SS2SI_64>, XS, REX_W;
1602 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1603 "cvttsd2si\t{$src, $dst|$dst, $src}",
1605 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1606 "cvttsd2si\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_SD2SI>, XD, REX_W;
1608 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1609 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_Scalar>, XS;
1611 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1612 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1613 SSE_CVT_Scalar>, XS, REX_W;
1614 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1615 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1616 SSE_CVT_Scalar>, XD;
1617 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1618 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1619 SSE_CVT_Scalar>, XD, REX_W;
1621 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1629 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1630 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1631 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1632 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1633 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1634 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1635 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1636 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1638 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1639 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1640 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1641 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1643 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1644 // and/or XMM operand(s).
1646 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1647 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1648 string asm, OpndItins itins> {
1649 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1650 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1651 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1652 Sched<[itins.Sched]>;
1653 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1654 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1655 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1656 Sched<[itins.Sched.Folded]>;
1659 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1660 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1661 PatFrag ld_frag, string asm, OpndItins itins,
1663 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1665 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1666 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1667 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1668 itins.rr>, Sched<[itins.Sched]>;
1669 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1670 (ins DstRC:$src1, x86memop:$src2),
1672 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1673 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1674 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1675 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1678 let Predicates = [UseAVX] in {
1679 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1680 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1681 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1682 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1683 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1684 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1686 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1687 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1688 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1689 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1692 let isCodeGenOnly = 1 in {
1693 let Predicates = [UseAVX] in {
1694 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1695 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1696 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1697 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1698 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1699 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1701 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1702 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1703 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1704 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1705 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1706 SSE_CVT_Scalar, 0>, XD,
1709 let Constraints = "$src1 = $dst" in {
1710 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1711 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1712 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1713 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1714 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1715 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1716 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1717 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1718 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1719 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1720 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1721 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1723 } // isCodeGenOnly = 1
1727 // Aliases for intrinsics
1728 let isCodeGenOnly = 1 in {
1729 let Predicates = [UseAVX] in {
1730 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1731 ssmem, sse_load_f32, "cvttss2si",
1732 SSE_CVT_SS2SI_32>, XS, VEX;
1733 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1734 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1735 "cvttss2si", SSE_CVT_SS2SI_64>,
1737 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1738 sdmem, sse_load_f64, "cvttsd2si",
1739 SSE_CVT_SD2SI>, XD, VEX;
1740 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1742 "cvttsd2si", SSE_CVT_SD2SI>,
1745 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1746 ssmem, sse_load_f32, "cvttss2si",
1747 SSE_CVT_SS2SI_32>, XS;
1748 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1749 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1750 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1751 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1752 sdmem, sse_load_f64, "cvttsd2si",
1754 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1755 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1756 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1757 } // isCodeGenOnly = 1
1759 let Predicates = [UseAVX] in {
1760 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1761 ssmem, sse_load_f32, "cvtss2si",
1762 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1763 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1764 ssmem, sse_load_f32, "cvtss2si",
1765 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1767 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1768 ssmem, sse_load_f32, "cvtss2si",
1769 SSE_CVT_SS2SI_32>, XS;
1770 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1771 ssmem, sse_load_f32, "cvtss2si",
1772 SSE_CVT_SS2SI_64>, XS, REX_W;
1774 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1775 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1776 SSEPackedSingle, SSE_CVT_PS>,
1777 PS, VEX, Requires<[HasAVX]>;
1778 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1779 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1780 SSEPackedSingle, SSE_CVT_PS>,
1781 PS, VEX, VEX_L, Requires<[HasAVX]>;
1783 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1784 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1785 SSEPackedSingle, SSE_CVT_PS>,
1786 PS, Requires<[UseSSE2]>;
1788 let Predicates = [UseAVX] in {
1789 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1797 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1798 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1799 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1800 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1801 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1802 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1803 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1804 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1815 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1816 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1817 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1818 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1819 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1820 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1821 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1822 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1826 // Convert scalar double to scalar single
1827 let hasSideEffects = 0, Predicates = [UseAVX] in {
1828 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1829 (ins FR64:$src1, FR64:$src2),
1830 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1831 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1832 Sched<[WriteCvtF2F]>;
1834 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1835 (ins FR64:$src1, f64mem:$src2),
1836 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1837 [], IIC_SSE_CVT_Scalar_RM>,
1838 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1839 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1842 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1845 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1846 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1847 [(set FR32:$dst, (fround FR64:$src))],
1848 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1849 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1850 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1851 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1852 IIC_SSE_CVT_Scalar_RM>,
1854 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1856 let isCodeGenOnly = 1 in {
1857 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1858 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1859 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1861 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1862 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1863 Sched<[WriteCvtF2F]>;
1864 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1865 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1866 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1867 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1868 VR128:$src1, sse_load_f64:$src2))],
1869 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1870 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1872 let Constraints = "$src1 = $dst" in {
1873 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1874 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1875 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1877 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1878 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1879 Sched<[WriteCvtF2F]>;
1880 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1881 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1882 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1883 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1884 VR128:$src1, sse_load_f64:$src2))],
1885 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1886 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1888 } // isCodeGenOnly = 1
1890 // Convert scalar single to scalar double
1891 // SSE2 instructions with XS prefix
1892 let hasSideEffects = 0, Predicates = [UseAVX] in {
1893 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1894 (ins FR32:$src1, FR32:$src2),
1895 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1896 [], IIC_SSE_CVT_Scalar_RR>,
1897 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1898 Sched<[WriteCvtF2F]>;
1900 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1901 (ins FR32:$src1, f32mem:$src2),
1902 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1903 [], IIC_SSE_CVT_Scalar_RM>,
1904 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1905 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1908 def : Pat<(f64 (fextend FR32:$src)),
1909 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1910 def : Pat<(fextend (loadf32 addr:$src)),
1911 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1913 def : Pat<(extloadf32 addr:$src),
1914 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1915 Requires<[UseAVX, OptForSize]>;
1916 def : Pat<(extloadf32 addr:$src),
1917 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1918 Requires<[UseAVX, OptForSpeed]>;
1920 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1921 "cvtss2sd\t{$src, $dst|$dst, $src}",
1922 [(set FR64:$dst, (fextend FR32:$src))],
1923 IIC_SSE_CVT_Scalar_RR>, XS,
1924 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1925 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1926 "cvtss2sd\t{$src, $dst|$dst, $src}",
1927 [(set FR64:$dst, (extloadf32 addr:$src))],
1928 IIC_SSE_CVT_Scalar_RM>, XS,
1929 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1931 // extload f32 -> f64. This matches load+fextend because we have a hack in
1932 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1934 // Since these loads aren't folded into the fextend, we have to match it
1936 def : Pat<(fextend (loadf32 addr:$src)),
1937 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1938 def : Pat<(extloadf32 addr:$src),
1939 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1941 let isCodeGenOnly = 1 in {
1942 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1943 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1944 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1946 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1947 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1948 Sched<[WriteCvtF2F]>;
1949 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1950 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1951 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1954 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1955 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1956 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1957 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1958 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1959 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1961 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1962 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1963 Sched<[WriteCvtF2F]>;
1964 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1965 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1966 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1968 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1969 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1970 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1972 } // isCodeGenOnly = 1
1974 // Convert packed single/double fp to doubleword
1975 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1976 "cvtps2dq\t{$src, $dst|$dst, $src}",
1977 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1978 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1979 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1980 "cvtps2dq\t{$src, $dst|$dst, $src}",
1982 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1983 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1984 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1985 "cvtps2dq\t{$src, $dst|$dst, $src}",
1987 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1988 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1989 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1990 "cvtps2dq\t{$src, $dst|$dst, $src}",
1992 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1993 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1994 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1995 "cvtps2dq\t{$src, $dst|$dst, $src}",
1996 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1997 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1998 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1999 "cvtps2dq\t{$src, $dst|$dst, $src}",
2001 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
2002 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2005 // Convert Packed Double FP to Packed DW Integers
2006 let Predicates = [HasAVX] in {
2007 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2008 // register, but the same isn't true when using memory operands instead.
2009 // Provide other assembly rr and rm forms to address this explicitly.
2010 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2011 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2012 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2013 VEX, Sched<[WriteCvtF2I]>;
2016 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2017 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2018 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2019 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2021 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2022 Sched<[WriteCvtF2ILd]>;
2025 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2026 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2028 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2029 Sched<[WriteCvtF2I]>;
2030 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2031 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2033 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2034 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2035 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2036 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2039 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2040 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2042 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2043 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2044 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2045 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2046 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2047 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2049 // Convert with truncation packed single/double fp to doubleword
2050 // SSE2 packed instructions with XS prefix
2051 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2052 "cvttps2dq\t{$src, $dst|$dst, $src}",
2054 (int_x86_sse2_cvttps2dq VR128:$src))],
2055 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2056 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2057 "cvttps2dq\t{$src, $dst|$dst, $src}",
2058 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2059 (loadv4f32 addr:$src)))],
2060 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2061 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2062 "cvttps2dq\t{$src, $dst|$dst, $src}",
2064 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2065 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2066 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2067 "cvttps2dq\t{$src, $dst|$dst, $src}",
2068 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2069 (loadv8f32 addr:$src)))],
2070 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2071 Sched<[WriteCvtF2ILd]>;
2073 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2074 "cvttps2dq\t{$src, $dst|$dst, $src}",
2075 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2076 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2077 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2078 "cvttps2dq\t{$src, $dst|$dst, $src}",
2080 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2081 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2083 let Predicates = [HasAVX] in {
2084 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2085 (VCVTDQ2PSrr VR128:$src)>;
2086 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2087 (VCVTDQ2PSrm addr:$src)>;
2089 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2090 (VCVTDQ2PSrr VR128:$src)>;
2091 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2092 (VCVTDQ2PSrm addr:$src)>;
2094 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2095 (VCVTTPS2DQrr VR128:$src)>;
2096 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2097 (VCVTTPS2DQrm addr:$src)>;
2099 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2100 (VCVTDQ2PSYrr VR256:$src)>;
2101 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2102 (VCVTDQ2PSYrm addr:$src)>;
2104 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2105 (VCVTTPS2DQYrr VR256:$src)>;
2106 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2107 (VCVTTPS2DQYrm addr:$src)>;
2110 let Predicates = [UseSSE2] in {
2111 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2112 (CVTDQ2PSrr VR128:$src)>;
2113 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2114 (CVTDQ2PSrm addr:$src)>;
2116 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2117 (CVTDQ2PSrr VR128:$src)>;
2118 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2119 (CVTDQ2PSrm addr:$src)>;
2121 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2122 (CVTTPS2DQrr VR128:$src)>;
2123 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2124 (CVTTPS2DQrm addr:$src)>;
2127 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2128 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2130 (int_x86_sse2_cvttpd2dq VR128:$src))],
2131 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2133 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2134 // register, but the same isn't true when using memory operands instead.
2135 // Provide other assembly rr and rm forms to address this explicitly.
2138 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2139 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2140 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2141 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2142 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2143 (loadv2f64 addr:$src)))],
2144 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2147 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2148 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2150 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2151 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2152 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2153 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2155 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2156 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2157 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2158 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2160 let Predicates = [HasAVX] in {
2161 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2162 (VCVTTPD2DQYrr VR256:$src)>;
2163 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2164 (VCVTTPD2DQYrm addr:$src)>;
2165 } // Predicates = [HasAVX]
2167 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2168 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2169 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2170 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2171 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2172 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2173 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2174 (memopv2f64 addr:$src)))],
2176 Sched<[WriteCvtF2ILd]>;
2178 // Convert packed single to packed double
2179 let Predicates = [HasAVX] in {
2180 // SSE2 instructions without OpSize prefix
2181 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2182 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2183 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2184 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2185 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2186 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2187 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2188 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2189 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2190 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2192 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2193 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2194 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2195 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2197 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2198 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2201 let Predicates = [UseSSE2] in {
2202 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2203 "cvtps2pd\t{$src, $dst|$dst, $src}",
2204 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2205 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2206 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2207 "cvtps2pd\t{$src, $dst|$dst, $src}",
2208 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2209 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2212 // Convert Packed DW Integers to Packed Double FP
2213 let Predicates = [HasAVX] in {
2214 let hasSideEffects = 0, mayLoad = 1 in
2215 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2216 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2217 []>, VEX, Sched<[WriteCvtI2FLd]>;
2218 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2219 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2221 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2222 Sched<[WriteCvtI2F]>;
2223 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256
2227 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2228 Sched<[WriteCvtI2FLd]>;
2229 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2230 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2232 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2233 Sched<[WriteCvtI2F]>;
2236 let hasSideEffects = 0, mayLoad = 1 in
2237 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2238 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2239 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2240 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2241 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2242 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2243 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2245 // AVX 256-bit register conversion intrinsics
2246 let Predicates = [HasAVX] in {
2247 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2248 (VCVTDQ2PDYrr VR128:$src)>;
2249 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2250 (VCVTDQ2PDYrm addr:$src)>;
2251 } // Predicates = [HasAVX]
2253 // Convert packed double to packed single
2254 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2255 // register, but the same isn't true when using memory operands instead.
2256 // Provide other assembly rr and rm forms to address this explicitly.
2257 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2258 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2259 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2260 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2263 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2264 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2265 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2266 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2268 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2269 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2272 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2273 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2275 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2276 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2277 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2278 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2280 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2281 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2282 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2283 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2285 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2286 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2287 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2288 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2289 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2290 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2292 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2293 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2296 // AVX 256-bit register conversion intrinsics
2297 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2298 // whenever possible to avoid declaring two versions of each one.
2299 let Predicates = [HasAVX] in {
2300 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2301 (VCVTDQ2PSYrr VR256:$src)>;
2302 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2303 (VCVTDQ2PSYrm addr:$src)>;
2305 // Match fround and fextend for 128/256-bit conversions
2306 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2307 (VCVTPD2PSrr VR128:$src)>;
2308 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2309 (VCVTPD2PSXrm addr:$src)>;
2310 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2311 (VCVTPD2PSYrr VR256:$src)>;
2312 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2313 (VCVTPD2PSYrm addr:$src)>;
2315 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2316 (VCVTPS2PDrr VR128:$src)>;
2317 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2318 (VCVTPS2PDYrr VR128:$src)>;
2319 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2320 (VCVTPS2PDYrm addr:$src)>;
2323 let Predicates = [UseSSE2] in {
2324 // Match fround and fextend for 128 conversions
2325 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2326 (CVTPD2PSrr VR128:$src)>;
2327 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2328 (CVTPD2PSrm addr:$src)>;
2330 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2331 (CVTPS2PDrr VR128:$src)>;
2334 //===----------------------------------------------------------------------===//
2335 // SSE 1 & 2 - Compare Instructions
2336 //===----------------------------------------------------------------------===//
2338 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2339 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2340 Operand CC, SDNode OpNode, ValueType VT,
2341 PatFrag ld_frag, string asm, string asm_alt,
2342 OpndItins itins, ImmLeaf immLeaf> {
2343 def rr : SIi8<0xC2, MRMSrcReg,
2344 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2345 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2346 itins.rr>, Sched<[itins.Sched]>;
2347 def rm : SIi8<0xC2, MRMSrcMem,
2348 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2349 [(set RC:$dst, (OpNode (VT RC:$src1),
2350 (ld_frag addr:$src2), immLeaf:$cc))],
2352 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2354 // Accept explicit immediate argument form instead of comparison code.
2355 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2356 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2357 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2358 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2360 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2361 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2362 IIC_SSE_ALU_F32S_RM>,
2363 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2367 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2368 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2369 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2370 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2371 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2372 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2373 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2374 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2375 XD, VEX_4V, VEX_LIG;
2377 let Constraints = "$src1 = $dst" in {
2378 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2379 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2380 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2382 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2383 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2384 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2385 SSE_ALU_F64S, i8immZExt3>, XD;
2388 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2389 Intrinsic Int, string asm, OpndItins itins,
2391 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2392 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2393 [(set VR128:$dst, (Int VR128:$src1,
2394 VR128:$src, immLeaf:$cc))],
2396 Sched<[itins.Sched]>;
2397 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2398 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2399 [(set VR128:$dst, (Int VR128:$src1,
2400 (load addr:$src), immLeaf:$cc))],
2402 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2405 let isCodeGenOnly = 1 in {
2406 // Aliases to match intrinsics which expect XMM operand(s).
2407 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2408 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2409 SSE_ALU_F32S, i8immZExt5>,
2411 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2412 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2413 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2415 let Constraints = "$src1 = $dst" in {
2416 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2417 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2418 SSE_ALU_F32S, i8immZExt3>, XS;
2419 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2420 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2421 SSE_ALU_F64S, i8immZExt3>,
2427 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2428 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2429 ValueType vt, X86MemOperand x86memop,
2430 PatFrag ld_frag, string OpcodeStr> {
2431 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2432 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2433 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2436 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2437 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2438 [(set EFLAGS, (OpNode (vt RC:$src1),
2439 (ld_frag addr:$src2)))],
2441 Sched<[WriteFAddLd, ReadAfterLd]>;
2444 let Defs = [EFLAGS] in {
2445 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2446 "ucomiss">, PS, VEX, VEX_LIG;
2447 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2448 "ucomisd">, PD, VEX, VEX_LIG;
2449 let Pattern = []<dag> in {
2450 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2451 "comiss">, PS, VEX, VEX_LIG;
2452 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2453 "comisd">, PD, VEX, VEX_LIG;
2456 let isCodeGenOnly = 1 in {
2457 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2458 load, "ucomiss">, PS, VEX;
2459 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2460 load, "ucomisd">, PD, VEX;
2462 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2463 load, "comiss">, PS, VEX;
2464 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2465 load, "comisd">, PD, VEX;
2467 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2469 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2472 let Pattern = []<dag> in {
2473 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2475 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2479 let isCodeGenOnly = 1 in {
2480 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2481 load, "ucomiss">, PS;
2482 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2483 load, "ucomisd">, PD;
2485 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2487 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2490 } // Defs = [EFLAGS]
2492 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2493 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2494 Operand CC, Intrinsic Int, string asm,
2495 string asm_alt, Domain d, ImmLeaf immLeaf,
2496 OpndItins itins = SSE_ALU_F32P> {
2497 let isCommutable = 1 in
2498 def rri : PIi8<0xC2, MRMSrcReg,
2499 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2500 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2503 def rmi : PIi8<0xC2, MRMSrcMem,
2504 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2505 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), immLeaf:$cc))],
2507 Sched<[WriteFAddLd, ReadAfterLd]>;
2509 // Accept explicit immediate argument form instead of comparison code.
2510 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2511 def rri_alt : PIi8<0xC2, MRMSrcReg,
2512 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2513 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2515 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2516 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2517 asm_alt, [], itins.rm, d>,
2518 Sched<[WriteFAddLd, ReadAfterLd]>;
2522 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2523 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2525 SSEPackedSingle, i8immZExt5>, PS, VEX_4V;
2526 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2527 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2528 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2529 SSEPackedDouble, i8immZExt5>, PD, VEX_4V;
2530 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2531 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2532 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2533 SSEPackedSingle, i8immZExt5>, PS, VEX_4V, VEX_L;
2534 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2535 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2536 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2537 SSEPackedDouble, i8immZExt5>, PD, VEX_4V, VEX_L;
2538 let Constraints = "$src1 = $dst" in {
2539 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2540 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2541 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2542 SSEPackedSingle, i8immZExt5, SSE_ALU_F32P>, PS;
2543 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2544 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2545 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2546 SSEPackedDouble, i8immZExt5, SSE_ALU_F64P>, PD;
2549 let Predicates = [HasAVX] in {
2550 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2551 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2552 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2553 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2554 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2555 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2556 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2557 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2559 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2560 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2561 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2562 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2563 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2564 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2565 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2566 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2569 let Predicates = [UseSSE1] in {
2570 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2571 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2572 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2573 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2576 let Predicates = [UseSSE2] in {
2577 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2578 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2579 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2580 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2583 //===----------------------------------------------------------------------===//
2584 // SSE 1 & 2 - Shuffle Instructions
2585 //===----------------------------------------------------------------------===//
2587 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2588 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2589 ValueType vt, string asm, PatFrag mem_frag,
2591 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2592 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2593 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2594 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2595 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2596 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2597 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2598 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2599 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2600 Sched<[WriteFShuffle]>;
2603 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2604 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2605 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2606 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2607 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2608 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2609 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2610 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2611 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2612 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2613 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2614 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2616 let Constraints = "$src1 = $dst" in {
2617 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2618 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2619 memopv4f32, SSEPackedSingle>, PS;
2620 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2621 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2622 memopv2f64, SSEPackedDouble>, PD;
2625 let Predicates = [HasAVX] in {
2626 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2627 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2628 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2629 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2630 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2632 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2633 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2634 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2635 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2636 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2639 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2640 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2641 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2642 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2643 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2645 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2646 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2647 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2648 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2649 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2652 let Predicates = [UseSSE1] in {
2653 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2654 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2655 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2656 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2657 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2660 let Predicates = [UseSSE2] in {
2661 // Generic SHUFPD patterns
2662 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2663 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2664 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2665 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2666 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2669 //===----------------------------------------------------------------------===//
2670 // SSE 1 & 2 - Unpack FP Instructions
2671 //===----------------------------------------------------------------------===//
2673 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2674 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2675 PatFrag mem_frag, RegisterClass RC,
2676 X86MemOperand x86memop, string asm,
2678 def rr : PI<opc, MRMSrcReg,
2679 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2681 (vt (OpNode RC:$src1, RC:$src2)))],
2682 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2683 def rm : PI<opc, MRMSrcMem,
2684 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2686 (vt (OpNode RC:$src1,
2687 (mem_frag addr:$src2))))],
2689 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2692 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2693 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2694 SSEPackedSingle>, PS, VEX_4V;
2695 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2696 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2697 SSEPackedDouble>, PD, VEX_4V;
2698 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2699 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2700 SSEPackedSingle>, PS, VEX_4V;
2701 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2702 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedDouble>, PD, VEX_4V;
2705 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2706 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2707 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2708 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2709 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2710 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2711 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2712 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2713 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2714 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2715 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2716 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2718 let Constraints = "$src1 = $dst" in {
2719 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2720 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2721 SSEPackedSingle>, PS;
2722 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2723 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2724 SSEPackedDouble>, PD;
2725 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2726 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2727 SSEPackedSingle>, PS;
2728 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2729 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2730 SSEPackedDouble>, PD;
2731 } // Constraints = "$src1 = $dst"
2733 let Predicates = [HasAVX1Only] in {
2734 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2735 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2736 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2737 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2738 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2739 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2740 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2741 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2743 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2744 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2745 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2746 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2747 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2748 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2749 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2750 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2753 //===----------------------------------------------------------------------===//
2754 // SSE 1 & 2 - Extract Floating-Point Sign mask
2755 //===----------------------------------------------------------------------===//
2757 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2758 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2760 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2761 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2762 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2763 Sched<[WriteVecLogic]>;
2766 let Predicates = [HasAVX] in {
2767 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2768 "movmskps", SSEPackedSingle>, PS, VEX;
2769 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2770 "movmskpd", SSEPackedDouble>, PD, VEX;
2771 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2772 "movmskps", SSEPackedSingle>, PS,
2774 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2775 "movmskpd", SSEPackedDouble>, PD,
2778 def : Pat<(i32 (X86fgetsign FR32:$src)),
2779 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2780 def : Pat<(i64 (X86fgetsign FR32:$src)),
2781 (SUBREG_TO_REG (i64 0),
2782 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2783 def : Pat<(i32 (X86fgetsign FR64:$src)),
2784 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2785 def : Pat<(i64 (X86fgetsign FR64:$src)),
2786 (SUBREG_TO_REG (i64 0),
2787 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2790 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2791 SSEPackedSingle>, PS;
2792 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2793 SSEPackedDouble>, PD;
2795 def : Pat<(i32 (X86fgetsign FR32:$src)),
2796 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2797 Requires<[UseSSE1]>;
2798 def : Pat<(i64 (X86fgetsign FR32:$src)),
2799 (SUBREG_TO_REG (i64 0),
2800 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2801 Requires<[UseSSE1]>;
2802 def : Pat<(i32 (X86fgetsign FR64:$src)),
2803 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2804 Requires<[UseSSE2]>;
2805 def : Pat<(i64 (X86fgetsign FR64:$src)),
2806 (SUBREG_TO_REG (i64 0),
2807 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2808 Requires<[UseSSE2]>;
2810 //===---------------------------------------------------------------------===//
2811 // SSE2 - Packed Integer Logical Instructions
2812 //===---------------------------------------------------------------------===//
2814 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2816 /// PDI_binop_rm - Simple SSE2 binary operator.
2817 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2818 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2819 X86MemOperand x86memop, OpndItins itins,
2820 bit IsCommutable, bit Is2Addr> {
2821 let isCommutable = IsCommutable in
2822 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2823 (ins RC:$src1, RC:$src2),
2825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2826 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2827 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2828 Sched<[itins.Sched]>;
2829 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2830 (ins RC:$src1, x86memop:$src2),
2832 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2834 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2835 (bitconvert (memop_frag addr:$src2)))))],
2837 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2839 } // ExeDomain = SSEPackedInt
2841 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2842 ValueType OpVT128, ValueType OpVT256,
2843 OpndItins itins, bit IsCommutable = 0> {
2844 let Predicates = [HasAVX, NoVLX] in
2845 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2846 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2848 let Constraints = "$src1 = $dst" in
2849 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2850 memopv2i64, i128mem, itins, IsCommutable, 1>;
2852 let Predicates = [HasAVX2, NoVLX] in
2853 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2854 OpVT256, VR256, loadv4i64, i256mem, itins,
2855 IsCommutable, 0>, VEX_4V, VEX_L;
2858 // These are ordered here for pattern ordering requirements with the fp versions
2860 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2861 SSE_VEC_BIT_ITINS_P, 1>;
2862 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2863 SSE_VEC_BIT_ITINS_P, 1>;
2864 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2865 SSE_VEC_BIT_ITINS_P, 1>;
2866 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2867 SSE_VEC_BIT_ITINS_P, 0>;
2869 //===----------------------------------------------------------------------===//
2870 // SSE 1 & 2 - Logical Instructions
2871 //===----------------------------------------------------------------------===//
2873 // Multiclass for scalars using the X86 logical operation aliases for FP.
2874 multiclass sse12_fp_packed_scalar_logical_alias<
2875 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2876 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2877 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2880 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2881 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2884 let Constraints = "$src1 = $dst" in {
2885 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2886 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2889 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2890 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2895 let isCodeGenOnly = 1 in {
2896 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2898 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2900 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2903 let isCommutable = 0 in
2904 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2908 // Multiclass for vectors using the X86 logical operation aliases for FP.
2909 multiclass sse12_fp_packed_vector_logical_alias<
2910 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2911 let Predicates = [HasAVX, NoVLX] in {
2912 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2913 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle, itins, 0>,
2916 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2917 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble, itins, 0>,
2921 let Constraints = "$src1 = $dst" in {
2922 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2923 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2926 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2927 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2932 let isCodeGenOnly = 1 in {
2933 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2935 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2937 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2940 let isCommutable = 0 in
2941 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2945 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2947 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2949 let Predicates = [HasAVX, NoVLX] in {
2950 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2951 !strconcat(OpcodeStr, "ps"), f256mem,
2952 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2953 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2954 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2956 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2957 !strconcat(OpcodeStr, "pd"), f256mem,
2958 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2959 (bc_v4i64 (v4f64 VR256:$src2))))],
2960 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2961 (loadv4i64 addr:$src2)))], 0>,
2964 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2965 // are all promoted to v2i64, and the patterns are covered by the int
2966 // version. This is needed in SSE only, because v2i64 isn't supported on
2967 // SSE1, but only on SSE2.
2968 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2969 !strconcat(OpcodeStr, "ps"), f128mem, [],
2970 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2971 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2973 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2974 !strconcat(OpcodeStr, "pd"), f128mem,
2975 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2976 (bc_v2i64 (v2f64 VR128:$src2))))],
2977 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2978 (loadv2i64 addr:$src2)))], 0>,
2982 let Constraints = "$src1 = $dst" in {
2983 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2984 !strconcat(OpcodeStr, "ps"), f128mem,
2985 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2986 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2987 (memopv2i64 addr:$src2)))]>, PS;
2989 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2990 !strconcat(OpcodeStr, "pd"), f128mem,
2991 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2992 (bc_v2i64 (v2f64 VR128:$src2))))],
2993 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2994 (memopv2i64 addr:$src2)))]>, PD;
2998 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2999 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3000 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3001 let isCommutable = 0 in
3002 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3004 // AVX1 requires type coercions in order to fold loads directly into logical
3006 let Predicates = [HasAVX1Only] in {
3007 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3008 (VANDPSYrm VR256:$src1, addr:$src2)>;
3009 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3010 (VORPSYrm VR256:$src1, addr:$src2)>;
3011 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3012 (VXORPSYrm VR256:$src1, addr:$src2)>;
3013 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3014 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3017 //===----------------------------------------------------------------------===//
3018 // SSE 1 & 2 - Arithmetic Instructions
3019 //===----------------------------------------------------------------------===//
3021 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3024 /// In addition, we also have a special variant of the scalar form here to
3025 /// represent the associated intrinsic operation. This form is unlike the
3026 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3027 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3029 /// These three forms can each be reg+reg or reg+mem.
3032 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3034 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3035 SDNode OpNode, SizeItins itins> {
3036 let Predicates = [HasAVX, NoVLX] in {
3037 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3038 VR128, v4f32, f128mem, loadv4f32,
3039 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3040 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3041 VR128, v2f64, f128mem, loadv2f64,
3042 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3044 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3045 OpNode, VR256, v8f32, f256mem, loadv8f32,
3046 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3047 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3048 OpNode, VR256, v4f64, f256mem, loadv4f64,
3049 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3052 let Constraints = "$src1 = $dst" in {
3053 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3054 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3056 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3057 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3062 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3064 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3065 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3066 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3067 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3069 let Constraints = "$src1 = $dst" in {
3070 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3071 OpNode, FR32, f32mem, itins.s>, XS;
3072 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3073 OpNode, FR64, f64mem, itins.d>, XD;
3077 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3079 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3080 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3081 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3082 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3083 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3084 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3086 let Constraints = "$src1 = $dst" in {
3087 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3088 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3090 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3091 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3096 // Binary Arithmetic instructions
3097 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3098 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3099 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3100 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3101 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3102 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3103 let isCommutable = 0 in {
3104 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3105 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3106 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3107 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3109 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3110 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3111 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3112 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3113 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3114 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3115 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3118 let isCodeGenOnly = 1 in {
3119 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3120 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3121 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3122 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3125 // Patterns used to select SSE scalar fp arithmetic instructions from
3126 // a scalar fp operation followed by a blend.
3128 // These patterns know, for example, how to select an ADDSS from a
3129 // float add plus vector insert.
3131 // The effect is that the backend no longer emits unnecessary vector
3132 // insert instructions immediately after SSE scalar fp instructions
3133 // like addss or mulss.
3135 // For example, given the following code:
3136 // __m128 foo(__m128 A, __m128 B) {
3141 // previously we generated:
3142 // addss %xmm0, %xmm1
3143 // movss %xmm1, %xmm0
3146 // addss %xmm1, %xmm0
3148 let Predicates = [UseSSE1] in {
3149 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3150 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3152 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3153 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3154 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3156 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3157 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3158 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3160 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3161 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3162 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3164 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3167 let Predicates = [UseSSE2] in {
3168 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3169 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3170 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3172 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3173 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3174 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3176 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3177 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3178 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3180 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3181 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3182 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3184 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3187 let Predicates = [UseSSE41] in {
3188 // If the subtarget has SSE4.1 but not AVX, the vector insert instruction is
3189 // lowered into a X86insertps or a X86Blendi rather than a X86Movss. When
3190 // selecting SSE scalar single-precision fp arithmetic instructions, make
3191 // sure that we correctly match them.
3193 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3194 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3195 FR32:$src))), (iPTR 0))),
3196 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3197 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3198 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3199 FR32:$src))), (iPTR 0))),
3200 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3201 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3202 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3203 FR32:$src))), (iPTR 0))),
3204 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3205 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3206 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3207 FR32:$src))), (iPTR 0))),
3208 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3210 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3211 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3212 FR32:$src))), (i8 1))),
3213 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3214 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3215 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3216 FR32:$src))), (i8 1))),
3217 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3218 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3219 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3220 FR32:$src))), (i8 1))),
3221 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3222 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3223 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3224 FR32:$src))), (i8 1))),
3225 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3227 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3228 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3229 FR64:$src))), (i8 1))),
3230 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3231 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3232 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3233 FR64:$src))), (i8 1))),
3234 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3235 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3236 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3237 FR64:$src))), (i8 1))),
3238 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3239 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3240 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3241 FR64:$src))), (i8 1))),
3242 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3244 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3245 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3246 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3247 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3248 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3249 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3250 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3251 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3252 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3253 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3254 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3255 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3256 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3257 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3258 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3259 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3262 let Predicates = [HasAVX] in {
3263 // The following patterns select AVX Scalar single/double precision fp
3264 // arithmetic instructions.
3266 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3267 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3269 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3270 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3271 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3273 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3274 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3275 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3277 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3278 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3279 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3281 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3282 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3283 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3284 FR32:$src))), (iPTR 0))),
3285 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3286 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3287 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3288 FR32:$src))), (iPTR 0))),
3289 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3290 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3291 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3292 FR32:$src))), (iPTR 0))),
3293 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3294 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3295 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3296 FR32:$src))), (iPTR 0))),
3297 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3299 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3300 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3301 FR32:$src))), (i8 1))),
3302 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3303 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3304 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3305 FR32:$src))), (i8 1))),
3306 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3307 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3308 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3309 FR32:$src))), (i8 1))),
3310 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3311 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3312 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3313 FR32:$src))), (i8 1))),
3314 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3316 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3317 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3318 FR64:$src))), (i8 1))),
3319 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3320 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3321 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3322 FR64:$src))), (i8 1))),
3323 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3324 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3325 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3326 FR64:$src))), (i8 1))),
3327 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3328 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3329 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3330 FR64:$src))), (i8 1))),
3331 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3333 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3334 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3335 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3336 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3337 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3338 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3339 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3340 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3341 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3342 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3343 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3344 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3345 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3346 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3347 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3348 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3351 // Patterns used to select SSE scalar fp arithmetic instructions from
3352 // a vector packed single/double fp operation followed by a vector insert.
3354 // The effect is that the backend converts the packed fp instruction
3355 // followed by a vector insert into a single SSE scalar fp instruction.
3357 // For example, given the following code:
3358 // __m128 foo(__m128 A, __m128 B) {
3359 // __m128 C = A + B;
3360 // return (__m128) {c[0], a[1], a[2], a[3]};
3363 // previously we generated:
3364 // addps %xmm0, %xmm1
3365 // movss %xmm1, %xmm0
3368 // addss %xmm1, %xmm0
3370 let Predicates = [UseSSE1] in {
3371 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3372 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3373 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3374 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3375 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3376 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3377 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3378 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3379 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3380 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3381 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3382 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3385 let Predicates = [UseSSE2] in {
3386 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3387 // from a packed double-precision fp instruction plus movsd.
3389 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3390 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3391 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3392 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3393 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3394 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3395 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3396 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3397 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3398 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3399 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3400 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3403 let Predicates = [UseSSE41] in {
3404 // With SSE4.1 we may see these operations using X86Blendi rather than
3406 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3407 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3408 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3409 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3410 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3411 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3412 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3413 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3414 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3415 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3416 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3417 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3419 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3420 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3421 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3422 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3423 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3424 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3425 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3426 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3427 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3428 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3429 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3430 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3432 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3433 (v2f64 VR128:$dst), (i8 2))),
3434 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3435 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3436 (v2f64 VR128:$dst), (i8 2))),
3437 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3438 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3439 (v2f64 VR128:$dst), (i8 2))),
3440 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3441 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3442 (v2f64 VR128:$dst), (i8 2))),
3443 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3446 let Predicates = [HasAVX] in {
3447 // The following patterns select AVX Scalar single/double precision fp
3448 // arithmetic instructions from a packed single precision fp instruction
3449 // plus movss/movsd.
3451 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3452 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3453 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3454 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3455 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3456 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3457 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3458 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3459 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3460 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3461 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3462 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3463 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3464 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3465 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3466 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3467 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3468 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3469 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3470 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3471 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3472 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3473 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3474 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3476 // Also handle X86Blendi-based patterns.
3477 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3478 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3479 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3480 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3481 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3482 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3483 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3484 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3485 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3486 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3487 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3488 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3490 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3491 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3492 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3493 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3494 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3495 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3496 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3497 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3498 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3499 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3500 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3501 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3503 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3504 (v2f64 VR128:$dst), (i8 2))),
3505 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3506 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3507 (v2f64 VR128:$dst), (i8 2))),
3508 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3509 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3510 (v2f64 VR128:$dst), (i8 2))),
3511 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3512 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3513 (v2f64 VR128:$dst), (i8 2))),
3514 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3518 /// In addition, we also have a special variant of the scalar form here to
3519 /// represent the associated intrinsic operation. This form is unlike the
3520 /// plain scalar form, in that it takes an entire vector (instead of a
3521 /// scalar) and leaves the top elements undefined.
3523 /// And, we have a special variant form for a full-vector intrinsic form.
3525 let Sched = WriteFSqrt in {
3526 def SSE_SQRTPS : OpndItins<
3527 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3530 def SSE_SQRTSS : OpndItins<
3531 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3534 def SSE_SQRTPD : OpndItins<
3535 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3538 def SSE_SQRTSD : OpndItins<
3539 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3543 let Sched = WriteFRsqrt in {
3544 def SSE_RSQRTPS : OpndItins<
3545 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3548 def SSE_RSQRTSS : OpndItins<
3549 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3553 let Sched = WriteFRcp in {
3554 def SSE_RCPP : OpndItins<
3555 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3558 def SSE_RCPS : OpndItins<
3559 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3563 /// sse1_fp_unop_s - SSE1 unops in scalar form
3564 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3565 /// the HW instructions are 2 operand / destructive.
3566 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3568 let Predicates = [HasAVX], hasSideEffects = 0 in {
3569 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3570 (ins FR32:$src1, FR32:$src2),
3571 !strconcat("v", OpcodeStr,
3572 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3573 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3574 let mayLoad = 1 in {
3575 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3576 (ins FR32:$src1,f32mem:$src2),
3577 !strconcat("v", OpcodeStr,
3578 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3579 []>, VEX_4V, VEX_LIG,
3580 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3581 let isCodeGenOnly = 1 in
3582 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3583 (ins VR128:$src1, ssmem:$src2),
3584 !strconcat("v", OpcodeStr,
3585 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3586 []>, VEX_4V, VEX_LIG,
3587 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3591 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3592 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3593 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3594 // For scalar unary operations, fold a load into the operation
3595 // only in OptForSize mode. It eliminates an instruction, but it also
3596 // eliminates a whole-register clobber (the load), so it introduces a
3597 // partial register update condition.
3598 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3599 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3600 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3601 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3602 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3603 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3604 (ins VR128:$src1, VR128:$src2),
3605 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3606 [], itins.rr>, Sched<[itins.Sched]>;
3607 let mayLoad = 1, hasSideEffects = 0 in
3608 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3609 (ins VR128:$src1, ssmem:$src2),
3610 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3611 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3615 /// sse1_fp_unop_p - SSE1 unops in packed form.
3616 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3618 let Predicates = [HasAVX] in {
3619 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3620 !strconcat("v", OpcodeStr,
3621 "ps\t{$src, $dst|$dst, $src}"),
3622 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3623 itins.rr>, VEX, Sched<[itins.Sched]>;
3624 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3625 !strconcat("v", OpcodeStr,
3626 "ps\t{$src, $dst|$dst, $src}"),
3627 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3628 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3629 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3630 !strconcat("v", OpcodeStr,
3631 "ps\t{$src, $dst|$dst, $src}"),
3632 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3633 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3634 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3635 !strconcat("v", OpcodeStr,
3636 "ps\t{$src, $dst|$dst, $src}"),
3637 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3638 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3641 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3642 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3643 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3644 Sched<[itins.Sched]>;
3645 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3646 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3647 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3648 Sched<[itins.Sched.Folded]>;
3651 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3652 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3653 Intrinsic V4F32Int, Intrinsic V8F32Int,
3655 let isCodeGenOnly = 1 in {
3656 let Predicates = [HasAVX] in {
3657 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3658 !strconcat("v", OpcodeStr,
3659 "ps\t{$src, $dst|$dst, $src}"),
3660 [(set VR128:$dst, (V4F32Int VR128:$src))],
3661 itins.rr>, VEX, Sched<[itins.Sched]>;
3662 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3663 !strconcat("v", OpcodeStr,
3664 "ps\t{$src, $dst|$dst, $src}"),
3665 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3666 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3667 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3668 !strconcat("v", OpcodeStr,
3669 "ps\t{$src, $dst|$dst, $src}"),
3670 [(set VR256:$dst, (V8F32Int VR256:$src))],
3671 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3672 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3674 !strconcat("v", OpcodeStr,
3675 "ps\t{$src, $dst|$dst, $src}"),
3676 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3677 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3680 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3681 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3682 [(set VR128:$dst, (V4F32Int VR128:$src))],
3683 itins.rr>, Sched<[itins.Sched]>;
3684 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3685 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3686 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3687 itins.rm>, Sched<[itins.Sched.Folded]>;
3688 } // isCodeGenOnly = 1
3691 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3692 // FIXME: Combine the following sse2 classes with the sse1 classes above.
3693 // The only usage of these is for SQRT[S/P]D. See sse12_fp_binop* for example.
3694 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3695 SDNode OpNode, OpndItins itins> {
3696 let Predicates = [HasAVX], hasSideEffects = 0 in {
3697 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3698 (ins FR64:$src1, FR64:$src2),
3699 !strconcat("v", OpcodeStr,
3700 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3701 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3702 let mayLoad = 1 in {
3703 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3704 (ins FR64:$src1,f64mem:$src2),
3705 !strconcat("v", OpcodeStr,
3706 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3707 []>, VEX_4V, VEX_LIG,
3708 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3709 let isCodeGenOnly = 1 in
3710 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3711 (ins VR128:$src1, sdmem:$src2),
3712 !strconcat("v", OpcodeStr,
3713 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3714 []>, VEX_4V, VEX_LIG,
3715 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3719 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3720 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3721 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3722 Sched<[itins.Sched]>;
3723 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3724 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3725 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3726 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3727 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3728 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3730 SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3731 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
3732 [], itins.rr>, Sched<[itins.Sched]>;
3734 let mayLoad = 1, hasSideEffects = 0 in
3736 SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
3737 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
3738 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3739 } // isCodeGenOnly, Constraints
3742 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3743 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3744 SDNode OpNode, OpndItins itins> {
3745 let Predicates = [HasAVX] in {
3746 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3747 !strconcat("v", OpcodeStr,
3748 "pd\t{$src, $dst|$dst, $src}"),
3749 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3750 itins.rr>, VEX, Sched<[itins.Sched]>;
3751 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3752 !strconcat("v", OpcodeStr,
3753 "pd\t{$src, $dst|$dst, $src}"),
3754 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3755 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3756 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3757 !strconcat("v", OpcodeStr,
3758 "pd\t{$src, $dst|$dst, $src}"),
3759 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3760 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3761 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3762 !strconcat("v", OpcodeStr,
3763 "pd\t{$src, $dst|$dst, $src}"),
3764 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3765 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3768 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3769 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3770 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3771 Sched<[itins.Sched]>;
3772 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3773 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3774 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3775 Sched<[itins.Sched.Folded]>;
3779 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3780 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3781 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3782 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3784 // Reciprocal approximations. Note that these typically require refinement
3785 // in order to obtain suitable precision.
3786 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3787 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3788 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3789 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3790 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3791 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3792 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3793 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3795 let Predicates = [UseAVX] in {
3796 def : Pat<(f32 (fsqrt FR32:$src)),
3797 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3798 def : Pat<(f32 (fsqrt (load addr:$src))),
3799 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3800 Requires<[HasAVX, OptForSize]>;
3801 def : Pat<(f64 (fsqrt FR64:$src)),
3802 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3803 def : Pat<(f64 (fsqrt (load addr:$src))),
3804 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3805 Requires<[HasAVX, OptForSize]>;
3807 def : Pat<(f32 (X86frsqrt FR32:$src)),
3808 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3809 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3810 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3811 Requires<[HasAVX, OptForSize]>;
3813 def : Pat<(f32 (X86frcp FR32:$src)),
3814 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3815 def : Pat<(f32 (X86frcp (load addr:$src))),
3816 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3817 Requires<[HasAVX, OptForSize]>;
3819 let Predicates = [UseAVX] in {
3820 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3821 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3822 (COPY_TO_REGCLASS VR128:$src, FR32)),
3824 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3825 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3827 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3828 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3829 (COPY_TO_REGCLASS VR128:$src, FR64)),
3831 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3832 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3835 let Predicates = [HasAVX] in {
3836 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3837 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3838 (COPY_TO_REGCLASS VR128:$src, FR32)),
3840 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3841 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3843 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3844 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3845 (COPY_TO_REGCLASS VR128:$src, FR32)),
3847 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3848 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3851 // These are unary operations, but they are modeled as having 2 source operands
3852 // because the high elements of the destination are unchanged in SSE.
3853 let Predicates = [UseSSE1] in {
3854 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3855 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3856 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3857 (RCPSSr_Int VR128:$src, VR128:$src)>;
3858 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3859 (SQRTSSr_Int VR128:$src, VR128:$src)>;
3860 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3861 (SQRTSDr_Int VR128:$src, VR128:$src)>;
3864 // There is no f64 version of the reciprocal approximation instructions.
3866 //===----------------------------------------------------------------------===//
3867 // SSE 1 & 2 - Non-temporal stores
3868 //===----------------------------------------------------------------------===//
3870 let AddedComplexity = 400 in { // Prefer non-temporal versions
3871 let SchedRW = [WriteStore] in {
3872 let Predicates = [HasAVX, NoVLX] in {
3873 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3874 (ins f128mem:$dst, VR128:$src),
3875 "movntps\t{$src, $dst|$dst, $src}",
3876 [(alignednontemporalstore (v4f32 VR128:$src),
3878 IIC_SSE_MOVNT>, VEX;
3879 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3880 (ins f128mem:$dst, VR128:$src),
3881 "movntpd\t{$src, $dst|$dst, $src}",
3882 [(alignednontemporalstore (v2f64 VR128:$src),
3884 IIC_SSE_MOVNT>, VEX;
3886 let ExeDomain = SSEPackedInt in
3887 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3888 (ins f128mem:$dst, VR128:$src),
3889 "movntdq\t{$src, $dst|$dst, $src}",
3890 [(alignednontemporalstore (v2i64 VR128:$src),
3892 IIC_SSE_MOVNT>, VEX;
3894 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3895 (ins f256mem:$dst, VR256:$src),
3896 "movntps\t{$src, $dst|$dst, $src}",
3897 [(alignednontemporalstore (v8f32 VR256:$src),
3899 IIC_SSE_MOVNT>, VEX, VEX_L;
3900 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3901 (ins f256mem:$dst, VR256:$src),
3902 "movntpd\t{$src, $dst|$dst, $src}",
3903 [(alignednontemporalstore (v4f64 VR256:$src),
3905 IIC_SSE_MOVNT>, VEX, VEX_L;
3906 let ExeDomain = SSEPackedInt in
3907 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3908 (ins f256mem:$dst, VR256:$src),
3909 "movntdq\t{$src, $dst|$dst, $src}",
3910 [(alignednontemporalstore (v4i64 VR256:$src),
3912 IIC_SSE_MOVNT>, VEX, VEX_L;
3915 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3916 "movntps\t{$src, $dst|$dst, $src}",
3917 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3919 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3920 "movntpd\t{$src, $dst|$dst, $src}",
3921 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3924 let ExeDomain = SSEPackedInt in
3925 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3926 "movntdq\t{$src, $dst|$dst, $src}",
3927 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3930 // There is no AVX form for instructions below this point
3931 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3932 "movnti{l}\t{$src, $dst|$dst, $src}",
3933 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3935 PS, Requires<[HasSSE2]>;
3936 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3937 "movnti{q}\t{$src, $dst|$dst, $src}",
3938 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3940 PS, Requires<[HasSSE2]>;
3941 } // SchedRW = [WriteStore]
3943 let Predicates = [HasAVX, NoVLX] in {
3944 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3945 (VMOVNTPSmr addr:$dst, VR128:$src)>;
3948 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3949 (MOVNTPSmr addr:$dst, VR128:$src)>;
3951 } // AddedComplexity
3953 //===----------------------------------------------------------------------===//
3954 // SSE 1 & 2 - Prefetch and memory fence
3955 //===----------------------------------------------------------------------===//
3957 // Prefetch intrinsic.
3958 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3959 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3960 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3961 IIC_SSE_PREFETCH>, TB;
3962 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3963 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3964 IIC_SSE_PREFETCH>, TB;
3965 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3966 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3967 IIC_SSE_PREFETCH>, TB;
3968 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3969 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3970 IIC_SSE_PREFETCH>, TB;
3973 // FIXME: How should flush instruction be modeled?
3974 let SchedRW = [WriteLoad] in {
3976 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3977 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3978 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3981 let SchedRW = [WriteNop] in {
3982 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3983 // was introduced with SSE2, it's backward compatible.
3984 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3985 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3986 OBXS, Requires<[HasSSE2]>;
3989 let SchedRW = [WriteFence] in {
3990 // Load, store, and memory fence
3991 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3992 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3993 PS, Requires<[HasSSE1]>;
3994 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3995 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3996 TB, Requires<[HasSSE2]>;
3997 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3998 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3999 TB, Requires<[HasSSE2]>;
4002 def : Pat<(X86SFence), (SFENCE)>;
4003 def : Pat<(X86LFence), (LFENCE)>;
4004 def : Pat<(X86MFence), (MFENCE)>;
4006 //===----------------------------------------------------------------------===//
4007 // SSE 1 & 2 - Load/Store XCSR register
4008 //===----------------------------------------------------------------------===//
4010 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
4011 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4012 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
4013 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4014 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4015 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
4017 let Predicates = [UseSSE1] in {
4018 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
4019 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4020 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
4021 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4022 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4023 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
4026 //===---------------------------------------------------------------------===//
4027 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
4028 //===---------------------------------------------------------------------===//
4030 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4032 let hasSideEffects = 0, SchedRW = [WriteMove] in {
4033 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4034 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4036 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4037 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4039 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4040 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4042 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4043 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4048 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4049 SchedRW = [WriteMove] in {
4050 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4051 "movdqa\t{$src, $dst|$dst, $src}", [],
4054 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4055 "movdqa\t{$src, $dst|$dst, $src}", [],
4056 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
4057 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4058 "movdqu\t{$src, $dst|$dst, $src}", [],
4061 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4062 "movdqu\t{$src, $dst|$dst, $src}", [],
4063 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
4066 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4067 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4068 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4069 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4071 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4072 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4074 let Predicates = [HasAVX] in {
4075 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4076 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4078 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4079 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4084 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4085 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
4086 (ins i128mem:$dst, VR128:$src),
4087 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4089 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
4090 (ins i256mem:$dst, VR256:$src),
4091 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4093 let Predicates = [HasAVX] in {
4094 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4095 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4097 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
4098 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4103 let SchedRW = [WriteMove] in {
4104 let hasSideEffects = 0 in
4105 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4106 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
4108 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4109 "movdqu\t{$src, $dst|$dst, $src}",
4110 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4113 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
4114 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4115 "movdqa\t{$src, $dst|$dst, $src}", [],
4118 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4119 "movdqu\t{$src, $dst|$dst, $src}",
4120 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4124 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4125 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4126 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4127 "movdqa\t{$src, $dst|$dst, $src}",
4128 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
4130 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4131 "movdqu\t{$src, $dst|$dst, $src}",
4132 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
4134 XS, Requires<[UseSSE2]>;
4137 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4138 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4139 "movdqa\t{$src, $dst|$dst, $src}",
4140 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
4142 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4143 "movdqu\t{$src, $dst|$dst, $src}",
4144 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
4146 XS, Requires<[UseSSE2]>;
4149 } // ExeDomain = SSEPackedInt
4151 let Predicates = [HasAVX] in {
4152 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4153 (VMOVDQUmr addr:$dst, VR128:$src)>;
4154 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
4155 (VMOVDQUYmr addr:$dst, VR256:$src)>;
4157 let Predicates = [UseSSE2] in
4158 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4159 (MOVDQUmr addr:$dst, VR128:$src)>;
4161 //===---------------------------------------------------------------------===//
4162 // SSE2 - Packed Integer Arithmetic Instructions
4163 //===---------------------------------------------------------------------===//
4165 let Sched = WriteVecIMul in
4166 def SSE_PMADD : OpndItins<
4167 IIC_SSE_PMADD, IIC_SSE_PMADD
4170 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4172 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4173 RegisterClass RC, PatFrag memop_frag,
4174 X86MemOperand x86memop,
4176 bit IsCommutable = 0,
4178 let isCommutable = IsCommutable in
4179 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4180 (ins RC:$src1, RC:$src2),
4182 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4183 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4184 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4185 Sched<[itins.Sched]>;
4186 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4187 (ins RC:$src1, x86memop:$src2),
4189 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4190 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4191 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4192 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4195 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4196 Intrinsic IntId256, OpndItins itins,
4197 bit IsCommutable = 0> {
4198 let Predicates = [HasAVX] in
4199 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4200 VR128, loadv2i64, i128mem, itins,
4201 IsCommutable, 0>, VEX_4V;
4203 let Constraints = "$src1 = $dst" in
4204 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4205 i128mem, itins, IsCommutable, 1>;
4207 let Predicates = [HasAVX2] in
4208 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4209 VR256, loadv4i64, i256mem, itins,
4210 IsCommutable, 0>, VEX_4V, VEX_L;
4213 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4214 string OpcodeStr, SDNode OpNode,
4215 SDNode OpNode2, RegisterClass RC,
4216 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4217 ShiftOpndItins itins,
4219 // src2 is always 128-bit
4220 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4221 (ins RC:$src1, VR128:$src2),
4223 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4224 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4225 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4226 itins.rr>, Sched<[WriteVecShift]>;
4227 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4228 (ins RC:$src1, i128mem:$src2),
4230 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4231 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4232 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4233 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4234 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4235 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4236 (ins RC:$src1, u8imm:$src2),
4238 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4240 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4241 Sched<[WriteVecShift]>;
4244 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4245 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4246 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4247 PatFrag memop_frag, X86MemOperand x86memop,
4249 bit IsCommutable = 0, bit Is2Addr = 1> {
4250 let isCommutable = IsCommutable in
4251 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4252 (ins RC:$src1, RC:$src2),
4254 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4255 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4256 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4257 Sched<[itins.Sched]>;
4258 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4259 (ins RC:$src1, x86memop:$src2),
4261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4263 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4264 (bitconvert (memop_frag addr:$src2)))))]>,
4265 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4267 } // ExeDomain = SSEPackedInt
4269 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4270 SSE_INTALU_ITINS_P, 1>;
4271 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4272 SSE_INTALU_ITINS_P, 1>;
4273 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4274 SSE_INTALU_ITINS_P, 1>;
4275 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4276 SSE_INTALUQ_ITINS_P, 1>;
4277 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4278 SSE_INTMUL_ITINS_P, 1>;
4279 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4280 SSE_INTMUL_ITINS_P, 1>;
4281 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4282 SSE_INTMUL_ITINS_P, 1>;
4283 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4284 SSE_INTALU_ITINS_P, 0>;
4285 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4286 SSE_INTALU_ITINS_P, 0>;
4287 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4288 SSE_INTALU_ITINS_P, 0>;
4289 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4290 SSE_INTALUQ_ITINS_P, 0>;
4291 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4292 SSE_INTALU_ITINS_P, 0>;
4293 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4294 SSE_INTALU_ITINS_P, 0>;
4295 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4296 SSE_INTALU_ITINS_P, 1>;
4297 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4298 SSE_INTALU_ITINS_P, 1>;
4299 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4300 SSE_INTALU_ITINS_P, 1>;
4301 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4302 SSE_INTALU_ITINS_P, 1>;
4305 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4306 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4307 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4308 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4309 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4310 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4311 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4312 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4313 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4314 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4315 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4316 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4317 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4318 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4319 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4320 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4321 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4322 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4323 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4324 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4326 let Predicates = [HasAVX] in
4327 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4328 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4330 let Predicates = [HasAVX2] in
4331 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4332 VR256, loadv4i64, i256mem,
4333 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4334 let Constraints = "$src1 = $dst" in
4335 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4336 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4338 //===---------------------------------------------------------------------===//
4339 // SSE2 - Packed Integer Logical Instructions
4340 //===---------------------------------------------------------------------===//
4342 let Predicates = [HasAVX] in {
4343 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4344 VR128, v8i16, v8i16, bc_v8i16,
4345 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4346 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4347 VR128, v4i32, v4i32, bc_v4i32,
4348 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4349 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4350 VR128, v2i64, v2i64, bc_v2i64,
4351 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4353 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4354 VR128, v8i16, v8i16, bc_v8i16,
4355 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4356 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4357 VR128, v4i32, v4i32, bc_v4i32,
4358 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4359 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4360 VR128, v2i64, v2i64, bc_v2i64,
4361 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4363 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4364 VR128, v8i16, v8i16, bc_v8i16,
4365 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4366 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4367 VR128, v4i32, v4i32, bc_v4i32,
4368 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4370 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4371 // 128-bit logical shifts.
4372 def VPSLLDQri : PDIi8<0x73, MRM7r,
4373 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4374 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4376 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4378 def VPSRLDQri : PDIi8<0x73, MRM3r,
4379 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4380 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4382 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4384 // PSRADQri doesn't exist in SSE[1-3].
4386 } // Predicates = [HasAVX]
4388 let Predicates = [HasAVX2] in {
4389 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4390 VR256, v16i16, v8i16, bc_v8i16,
4391 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4392 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4393 VR256, v8i32, v4i32, bc_v4i32,
4394 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4395 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4396 VR256, v4i64, v2i64, bc_v2i64,
4397 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4399 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4400 VR256, v16i16, v8i16, bc_v8i16,
4401 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4402 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4403 VR256, v8i32, v4i32, bc_v4i32,
4404 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4405 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4406 VR256, v4i64, v2i64, bc_v2i64,
4407 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4409 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4410 VR256, v16i16, v8i16, bc_v8i16,
4411 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4412 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4413 VR256, v8i32, v4i32, bc_v4i32,
4414 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4416 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4417 // 256-bit logical shifts.
4418 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4419 (outs VR256:$dst), (ins VR256:$src1, i32u8imm:$src2),
4420 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4422 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4424 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4425 (outs VR256:$dst), (ins VR256:$src1, i32u8imm:$src2),
4426 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4428 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4430 // PSRADQYri doesn't exist in SSE[1-3].
4432 } // Predicates = [HasAVX2]
4434 let Constraints = "$src1 = $dst" in {
4435 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4436 VR128, v8i16, v8i16, bc_v8i16,
4437 SSE_INTSHIFT_ITINS_P>;
4438 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4439 VR128, v4i32, v4i32, bc_v4i32,
4440 SSE_INTSHIFT_ITINS_P>;
4441 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4442 VR128, v2i64, v2i64, bc_v2i64,
4443 SSE_INTSHIFT_ITINS_P>;
4445 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4446 VR128, v8i16, v8i16, bc_v8i16,
4447 SSE_INTSHIFT_ITINS_P>;
4448 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4449 VR128, v4i32, v4i32, bc_v4i32,
4450 SSE_INTSHIFT_ITINS_P>;
4451 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4452 VR128, v2i64, v2i64, bc_v2i64,
4453 SSE_INTSHIFT_ITINS_P>;
4455 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4456 VR128, v8i16, v8i16, bc_v8i16,
4457 SSE_INTSHIFT_ITINS_P>;
4458 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4459 VR128, v4i32, v4i32, bc_v4i32,
4460 SSE_INTSHIFT_ITINS_P>;
4462 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4463 // 128-bit logical shifts.
4464 def PSLLDQri : PDIi8<0x73, MRM7r,
4465 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4466 "pslldq\t{$src2, $dst|$dst, $src2}",
4468 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4469 IIC_SSE_INTSHDQ_P_RI>;
4470 def PSRLDQri : PDIi8<0x73, MRM3r,
4471 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4472 "psrldq\t{$src2, $dst|$dst, $src2}",
4474 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4475 IIC_SSE_INTSHDQ_P_RI>;
4476 // PSRADQri doesn't exist in SSE[1-3].
4478 } // Constraints = "$src1 = $dst"
4480 let Predicates = [HasAVX] in {
4481 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4482 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4483 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4484 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4485 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4486 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4488 // Shift up / down and insert zero's.
4489 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4490 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4491 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4492 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4495 let Predicates = [HasAVX2] in {
4496 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4497 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4498 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4499 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4502 let Predicates = [UseSSE2] in {
4503 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4504 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4505 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4506 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4507 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4508 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4510 // Shift up / down and insert zero's.
4511 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4512 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4513 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4514 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4517 //===---------------------------------------------------------------------===//
4518 // SSE2 - Packed Integer Comparison Instructions
4519 //===---------------------------------------------------------------------===//
4521 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4522 SSE_INTALU_ITINS_P, 1>;
4523 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4524 SSE_INTALU_ITINS_P, 1>;
4525 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4526 SSE_INTALU_ITINS_P, 1>;
4527 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4528 SSE_INTALU_ITINS_P, 0>;
4529 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4530 SSE_INTALU_ITINS_P, 0>;
4531 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4532 SSE_INTALU_ITINS_P, 0>;
4534 //===---------------------------------------------------------------------===//
4535 // SSE2 - Packed Integer Shuffle Instructions
4536 //===---------------------------------------------------------------------===//
4538 let ExeDomain = SSEPackedInt in {
4539 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4541 let Predicates = [HasAVX] in {
4542 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4543 (ins VR128:$src1, u8imm:$src2),
4544 !strconcat("v", OpcodeStr,
4545 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4547 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4548 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4549 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4550 (ins i128mem:$src1, u8imm:$src2),
4551 !strconcat("v", OpcodeStr,
4552 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4554 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4555 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4556 Sched<[WriteShuffleLd]>;
4559 let Predicates = [HasAVX2] in {
4560 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4561 (ins VR256:$src1, u8imm:$src2),
4562 !strconcat("v", OpcodeStr,
4563 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4565 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4566 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4567 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4568 (ins i256mem:$src1, u8imm:$src2),
4569 !strconcat("v", OpcodeStr,
4570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4572 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4573 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4574 Sched<[WriteShuffleLd]>;
4577 let Predicates = [UseSSE2] in {
4578 def ri : Ii8<0x70, MRMSrcReg,
4579 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4580 !strconcat(OpcodeStr,
4581 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4583 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4584 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4585 def mi : Ii8<0x70, MRMSrcMem,
4586 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4587 !strconcat(OpcodeStr,
4588 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4590 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4591 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4592 Sched<[WriteShuffleLd, ReadAfterLd]>;
4595 } // ExeDomain = SSEPackedInt
4597 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4598 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4599 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4601 let Predicates = [HasAVX] in {
4602 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4603 (VPSHUFDmi addr:$src1, imm:$imm)>;
4604 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4605 (VPSHUFDri VR128:$src1, imm:$imm)>;
4608 let Predicates = [UseSSE2] in {
4609 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4610 (PSHUFDmi addr:$src1, imm:$imm)>;
4611 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4612 (PSHUFDri VR128:$src1, imm:$imm)>;
4615 //===---------------------------------------------------------------------===//
4616 // Packed Integer Pack Instructions (SSE & AVX)
4617 //===---------------------------------------------------------------------===//
4619 let ExeDomain = SSEPackedInt in {
4620 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4621 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4623 def rr : PDI<opc, MRMSrcReg,
4624 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4626 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4627 !strconcat(OpcodeStr,
4628 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4630 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4631 Sched<[WriteShuffle]>;
4632 def rm : PDI<opc, MRMSrcMem,
4633 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4635 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4636 !strconcat(OpcodeStr,
4637 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4639 (OutVT (OpNode VR128:$src1,
4640 (bc_frag (memopv2i64 addr:$src2)))))]>,
4641 Sched<[WriteShuffleLd, ReadAfterLd]>;
4644 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4645 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4646 def Yrr : PDI<opc, MRMSrcReg,
4647 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4648 !strconcat(OpcodeStr,
4649 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4651 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4652 Sched<[WriteShuffle]>;
4653 def Yrm : PDI<opc, MRMSrcMem,
4654 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4655 !strconcat(OpcodeStr,
4656 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4658 (OutVT (OpNode VR256:$src1,
4659 (bc_frag (memopv4i64 addr:$src2)))))]>,
4660 Sched<[WriteShuffleLd, ReadAfterLd]>;
4663 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4664 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4666 def rr : SS48I<opc, MRMSrcReg,
4667 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4669 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4670 !strconcat(OpcodeStr,
4671 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4673 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4674 Sched<[WriteShuffle]>;
4675 def rm : SS48I<opc, MRMSrcMem,
4676 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4678 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4679 !strconcat(OpcodeStr,
4680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4682 (OutVT (OpNode VR128:$src1,
4683 (bc_frag (memopv2i64 addr:$src2)))))]>,
4684 Sched<[WriteShuffleLd, ReadAfterLd]>;
4687 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4688 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4689 def Yrr : SS48I<opc, MRMSrcReg,
4690 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4691 !strconcat(OpcodeStr,
4692 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4694 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4695 Sched<[WriteShuffle]>;
4696 def Yrm : SS48I<opc, MRMSrcMem,
4697 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4698 !strconcat(OpcodeStr,
4699 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4701 (OutVT (OpNode VR256:$src1,
4702 (bc_frag (memopv4i64 addr:$src2)))))]>,
4703 Sched<[WriteShuffleLd, ReadAfterLd]>;
4706 let Predicates = [HasAVX] in {
4707 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4708 bc_v8i16, 0>, VEX_4V;
4709 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4710 bc_v4i32, 0>, VEX_4V;
4712 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4713 bc_v8i16, 0>, VEX_4V;
4714 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4715 bc_v4i32, 0>, VEX_4V;
4718 let Predicates = [HasAVX2] in {
4719 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4720 bc_v16i16>, VEX_4V, VEX_L;
4721 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4722 bc_v8i32>, VEX_4V, VEX_L;
4724 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4725 bc_v16i16>, VEX_4V, VEX_L;
4726 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4727 bc_v8i32>, VEX_4V, VEX_L;
4730 let Constraints = "$src1 = $dst" in {
4731 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4733 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4736 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4739 let Predicates = [HasSSE41] in
4740 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4743 } // ExeDomain = SSEPackedInt
4745 //===---------------------------------------------------------------------===//
4746 // SSE2 - Packed Integer Unpack Instructions
4747 //===---------------------------------------------------------------------===//
4749 let ExeDomain = SSEPackedInt in {
4750 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4751 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4752 def rr : PDI<opc, MRMSrcReg,
4753 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4755 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4756 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4757 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4758 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4759 def rm : PDI<opc, MRMSrcMem,
4760 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4762 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4763 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4764 [(set VR128:$dst, (OpNode VR128:$src1,
4765 (bc_frag (memopv2i64
4768 Sched<[WriteShuffleLd, ReadAfterLd]>;
4771 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4772 SDNode OpNode, PatFrag bc_frag> {
4773 def Yrr : PDI<opc, MRMSrcReg,
4774 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4775 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4776 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4777 Sched<[WriteShuffle]>;
4778 def Yrm : PDI<opc, MRMSrcMem,
4779 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4780 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4781 [(set VR256:$dst, (OpNode VR256:$src1,
4782 (bc_frag (memopv4i64 addr:$src2))))]>,
4783 Sched<[WriteShuffleLd, ReadAfterLd]>;
4786 let Predicates = [HasAVX] in {
4787 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4788 bc_v16i8, 0>, VEX_4V;
4789 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4790 bc_v8i16, 0>, VEX_4V;
4791 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4792 bc_v4i32, 0>, VEX_4V;
4793 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4794 bc_v2i64, 0>, VEX_4V;
4796 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4797 bc_v16i8, 0>, VEX_4V;
4798 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4799 bc_v8i16, 0>, VEX_4V;
4800 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4801 bc_v4i32, 0>, VEX_4V;
4802 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4803 bc_v2i64, 0>, VEX_4V;
4806 let Predicates = [HasAVX2] in {
4807 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4808 bc_v32i8>, VEX_4V, VEX_L;
4809 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4810 bc_v16i16>, VEX_4V, VEX_L;
4811 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4812 bc_v8i32>, VEX_4V, VEX_L;
4813 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4814 bc_v4i64>, VEX_4V, VEX_L;
4816 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4817 bc_v32i8>, VEX_4V, VEX_L;
4818 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4819 bc_v16i16>, VEX_4V, VEX_L;
4820 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4821 bc_v8i32>, VEX_4V, VEX_L;
4822 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4823 bc_v4i64>, VEX_4V, VEX_L;
4826 let Constraints = "$src1 = $dst" in {
4827 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4829 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4831 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4833 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4836 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4838 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4840 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4842 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4845 } // ExeDomain = SSEPackedInt
4847 //===---------------------------------------------------------------------===//
4848 // SSE2 - Packed Integer Extract and Insert
4849 //===---------------------------------------------------------------------===//
4851 let ExeDomain = SSEPackedInt in {
4852 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4853 def rri : Ii8<0xC4, MRMSrcReg,
4854 (outs VR128:$dst), (ins VR128:$src1,
4855 GR32orGR64:$src2, u8imm:$src3),
4857 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4858 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4860 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4861 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4862 def rmi : Ii8<0xC4, MRMSrcMem,
4863 (outs VR128:$dst), (ins VR128:$src1,
4864 i16mem:$src2, u8imm:$src3),
4866 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4867 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4869 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4870 imm:$src3))], IIC_SSE_PINSRW>,
4871 Sched<[WriteShuffleLd, ReadAfterLd]>;
4875 let Predicates = [HasAVX] in
4876 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4877 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4878 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4879 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4880 imm:$src2))]>, PD, VEX,
4881 Sched<[WriteShuffle]>;
4882 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4883 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4884 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4885 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4886 imm:$src2))], IIC_SSE_PEXTRW>,
4887 Sched<[WriteShuffleLd, ReadAfterLd]>;
4890 let Predicates = [HasAVX] in
4891 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4893 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4894 defm PINSRW : sse2_pinsrw, PD;
4896 } // ExeDomain = SSEPackedInt
4898 //===---------------------------------------------------------------------===//
4899 // SSE2 - Packed Mask Creation
4900 //===---------------------------------------------------------------------===//
4902 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4904 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4906 "pmovmskb\t{$src, $dst|$dst, $src}",
4907 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4908 IIC_SSE_MOVMSK>, VEX;
4910 let Predicates = [HasAVX2] in {
4911 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4913 "pmovmskb\t{$src, $dst|$dst, $src}",
4914 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4918 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4919 "pmovmskb\t{$src, $dst|$dst, $src}",
4920 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4923 } // ExeDomain = SSEPackedInt
4925 //===---------------------------------------------------------------------===//
4926 // SSE2 - Conditional Store
4927 //===---------------------------------------------------------------------===//
4929 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4931 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4932 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4933 (ins VR128:$src, VR128:$mask),
4934 "maskmovdqu\t{$mask, $src|$src, $mask}",
4935 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4936 IIC_SSE_MASKMOV>, VEX;
4937 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4938 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4939 (ins VR128:$src, VR128:$mask),
4940 "maskmovdqu\t{$mask, $src|$src, $mask}",
4941 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4942 IIC_SSE_MASKMOV>, VEX;
4944 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4945 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4946 "maskmovdqu\t{$mask, $src|$src, $mask}",
4947 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4949 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4950 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4951 "maskmovdqu\t{$mask, $src|$src, $mask}",
4952 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4955 } // ExeDomain = SSEPackedInt
4957 //===---------------------------------------------------------------------===//
4958 // SSE2 - Move Doubleword
4959 //===---------------------------------------------------------------------===//
4961 //===---------------------------------------------------------------------===//
4962 // Move Int Doubleword to Packed Double Int
4964 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4965 "movd\t{$src, $dst|$dst, $src}",
4967 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4968 VEX, Sched<[WriteMove]>;
4969 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4970 "movd\t{$src, $dst|$dst, $src}",
4972 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4974 VEX, Sched<[WriteLoad]>;
4975 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4976 "movq\t{$src, $dst|$dst, $src}",
4978 (v2i64 (scalar_to_vector GR64:$src)))],
4979 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4980 let isCodeGenOnly = 1 in
4981 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4982 "movq\t{$src, $dst|$dst, $src}",
4983 [(set FR64:$dst, (bitconvert GR64:$src))],
4984 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4986 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4987 "movd\t{$src, $dst|$dst, $src}",
4989 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4991 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4992 "movd\t{$src, $dst|$dst, $src}",
4994 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4995 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4996 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4997 "mov{d|q}\t{$src, $dst|$dst, $src}",
4999 (v2i64 (scalar_to_vector GR64:$src)))],
5000 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5001 let isCodeGenOnly = 1 in
5002 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
5003 "mov{d|q}\t{$src, $dst|$dst, $src}",
5004 [(set FR64:$dst, (bitconvert GR64:$src))],
5005 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5007 //===---------------------------------------------------------------------===//
5008 // Move Int Doubleword to Single Scalar
5010 let isCodeGenOnly = 1 in {
5011 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5012 "movd\t{$src, $dst|$dst, $src}",
5013 [(set FR32:$dst, (bitconvert GR32:$src))],
5014 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5016 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5017 "movd\t{$src, $dst|$dst, $src}",
5018 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5020 VEX, Sched<[WriteLoad]>;
5021 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5022 "movd\t{$src, $dst|$dst, $src}",
5023 [(set FR32:$dst, (bitconvert GR32:$src))],
5024 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5026 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5027 "movd\t{$src, $dst|$dst, $src}",
5028 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5029 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5032 //===---------------------------------------------------------------------===//
5033 // Move Packed Doubleword Int to Packed Double Int
5035 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5036 "movd\t{$src, $dst|$dst, $src}",
5037 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5038 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
5040 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
5041 (ins i32mem:$dst, VR128:$src),
5042 "movd\t{$src, $dst|$dst, $src}",
5043 [(store (i32 (vector_extract (v4i32 VR128:$src),
5044 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
5045 VEX, Sched<[WriteStore]>;
5046 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5047 "movd\t{$src, $dst|$dst, $src}",
5048 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5049 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
5051 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
5052 "movd\t{$src, $dst|$dst, $src}",
5053 [(store (i32 (vector_extract (v4i32 VR128:$src),
5054 (iPTR 0))), addr:$dst)],
5055 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5057 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
5058 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5060 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
5061 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5063 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
5064 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5066 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
5067 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5069 //===---------------------------------------------------------------------===//
5070 // Move Packed Doubleword Int first element to Doubleword Int
5072 let SchedRW = [WriteMove] in {
5073 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5074 "movq\t{$src, $dst|$dst, $src}",
5075 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5080 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5081 "mov{d|q}\t{$src, $dst|$dst, $src}",
5082 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5087 //===---------------------------------------------------------------------===//
5088 // Bitcast FR64 <-> GR64
5090 let isCodeGenOnly = 1 in {
5091 let Predicates = [UseAVX] in
5092 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5093 "movq\t{$src, $dst|$dst, $src}",
5094 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
5095 VEX, Sched<[WriteLoad]>;
5096 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5097 "movq\t{$src, $dst|$dst, $src}",
5098 [(set GR64:$dst, (bitconvert FR64:$src))],
5099 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5100 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5101 "movq\t{$src, $dst|$dst, $src}",
5102 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5103 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5105 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5106 "movq\t{$src, $dst|$dst, $src}",
5107 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
5108 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5109 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5110 "mov{d|q}\t{$src, $dst|$dst, $src}",
5111 [(set GR64:$dst, (bitconvert FR64:$src))],
5112 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5113 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5114 "movq\t{$src, $dst|$dst, $src}",
5115 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5116 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5119 //===---------------------------------------------------------------------===//
5120 // Move Scalar Single to Double Int
5122 let isCodeGenOnly = 1 in {
5123 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5124 "movd\t{$src, $dst|$dst, $src}",
5125 [(set GR32:$dst, (bitconvert FR32:$src))],
5126 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
5127 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5128 "movd\t{$src, $dst|$dst, $src}",
5129 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5130 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5131 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5132 "movd\t{$src, $dst|$dst, $src}",
5133 [(set GR32:$dst, (bitconvert FR32:$src))],
5134 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5135 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5136 "movd\t{$src, $dst|$dst, $src}",
5137 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5138 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5141 //===---------------------------------------------------------------------===//
5142 // Patterns and instructions to describe movd/movq to XMM register zero-extends
5144 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
5145 let AddedComplexity = 15 in {
5146 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5147 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
5148 [(set VR128:$dst, (v2i64 (X86vzmovl
5149 (v2i64 (scalar_to_vector GR64:$src)))))],
5152 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5153 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
5154 [(set VR128:$dst, (v2i64 (X86vzmovl
5155 (v2i64 (scalar_to_vector GR64:$src)))))],
5158 } // isCodeGenOnly, SchedRW
5160 let Predicates = [UseAVX] in {
5161 let AddedComplexity = 15 in
5162 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5163 (VMOVDI2PDIrr GR32:$src)>;
5165 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5166 let AddedComplexity = 20 in {
5167 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5168 (VMOVDI2PDIrm addr:$src)>;
5169 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5170 (VMOVDI2PDIrm addr:$src)>;
5171 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5172 (VMOVDI2PDIrm addr:$src)>;
5174 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5175 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5176 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5177 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5178 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5179 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5180 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5183 let Predicates = [UseSSE2] in {
5184 let AddedComplexity = 15 in
5185 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5186 (MOVDI2PDIrr GR32:$src)>;
5188 let AddedComplexity = 20 in {
5189 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5190 (MOVDI2PDIrm addr:$src)>;
5191 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5192 (MOVDI2PDIrm addr:$src)>;
5193 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5194 (MOVDI2PDIrm addr:$src)>;
5198 // These are the correct encodings of the instructions so that we know how to
5199 // read correct assembly, even though we continue to emit the wrong ones for
5200 // compatibility with Darwin's buggy assembler.
5201 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5202 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5203 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5204 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5205 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5206 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5207 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5208 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5209 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5211 //===---------------------------------------------------------------------===//
5212 // SSE2 - Move Quadword
5213 //===---------------------------------------------------------------------===//
5215 //===---------------------------------------------------------------------===//
5216 // Move Quadword Int to Packed Quadword Int
5219 let SchedRW = [WriteLoad] in {
5220 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5221 "vmovq\t{$src, $dst|$dst, $src}",
5223 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5224 VEX, Requires<[UseAVX]>;
5225 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5226 "movq\t{$src, $dst|$dst, $src}",
5228 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5230 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5233 //===---------------------------------------------------------------------===//
5234 // Move Packed Quadword Int to Quadword Int
5236 let SchedRW = [WriteStore] in {
5237 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5238 "movq\t{$src, $dst|$dst, $src}",
5239 [(store (i64 (vector_extract (v2i64 VR128:$src),
5240 (iPTR 0))), addr:$dst)],
5241 IIC_SSE_MOVDQ>, VEX;
5242 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5243 "movq\t{$src, $dst|$dst, $src}",
5244 [(store (i64 (vector_extract (v2i64 VR128:$src),
5245 (iPTR 0))), addr:$dst)],
5249 // For disassembler only
5250 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5251 SchedRW = [WriteVecLogic] in {
5252 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5253 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5254 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5255 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5258 //===---------------------------------------------------------------------===//
5259 // Store / copy lower 64-bits of a XMM register.
5261 let Predicates = [UseAVX] in
5262 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5263 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5264 let Predicates = [UseSSE2] in
5265 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5266 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5268 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5269 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5270 "vmovq\t{$src, $dst|$dst, $src}",
5272 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5273 (loadi64 addr:$src))))))],
5275 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5277 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5278 "movq\t{$src, $dst|$dst, $src}",
5280 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5281 (loadi64 addr:$src))))))],
5283 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5286 let Predicates = [UseAVX], AddedComplexity = 20 in {
5287 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5288 (VMOVZQI2PQIrm addr:$src)>;
5289 def : Pat<(v2i64 (X86vzload addr:$src)),
5290 (VMOVZQI2PQIrm addr:$src)>;
5293 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5294 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5295 (MOVZQI2PQIrm addr:$src)>;
5296 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5299 let Predicates = [HasAVX] in {
5300 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5301 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5302 def : Pat<(v4i64 (X86vzload addr:$src)),
5303 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5306 //===---------------------------------------------------------------------===//
5307 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5308 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5310 let SchedRW = [WriteVecLogic] in {
5311 let AddedComplexity = 15 in
5312 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5313 "vmovq\t{$src, $dst|$dst, $src}",
5314 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5316 XS, VEX, Requires<[UseAVX]>;
5317 let AddedComplexity = 15 in
5318 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5319 "movq\t{$src, $dst|$dst, $src}",
5320 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5322 XS, Requires<[UseSSE2]>;
5325 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5326 let AddedComplexity = 20 in
5327 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5328 "vmovq\t{$src, $dst|$dst, $src}",
5329 [(set VR128:$dst, (v2i64 (X86vzmovl
5330 (loadv2i64 addr:$src))))],
5332 XS, VEX, Requires<[UseAVX]>;
5333 let AddedComplexity = 20 in {
5334 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5335 "movq\t{$src, $dst|$dst, $src}",
5336 [(set VR128:$dst, (v2i64 (X86vzmovl
5337 (loadv2i64 addr:$src))))],
5339 XS, Requires<[UseSSE2]>;
5341 } // isCodeGenOnly, SchedRW
5343 let AddedComplexity = 20 in {
5344 let Predicates = [UseAVX] in {
5345 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5346 (VMOVZPQILo2PQIrr VR128:$src)>;
5348 let Predicates = [UseSSE2] in {
5349 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5350 (MOVZPQILo2PQIrr VR128:$src)>;
5354 //===---------------------------------------------------------------------===//
5355 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5356 //===---------------------------------------------------------------------===//
5357 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5358 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5359 X86MemOperand x86memop> {
5360 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5361 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5362 [(set RC:$dst, (vt (OpNode RC:$src)))],
5363 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5364 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5366 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5367 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5370 let Predicates = [HasAVX] in {
5371 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5372 v4f32, VR128, loadv4f32, f128mem>, VEX;
5373 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5374 v4f32, VR128, loadv4f32, f128mem>, VEX;
5375 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5376 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5377 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5378 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5380 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5381 memopv4f32, f128mem>;
5382 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5383 memopv4f32, f128mem>;
5385 let Predicates = [HasAVX] in {
5386 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5387 (VMOVSHDUPrr VR128:$src)>;
5388 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5389 (VMOVSHDUPrm addr:$src)>;
5390 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5391 (VMOVSLDUPrr VR128:$src)>;
5392 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5393 (VMOVSLDUPrm addr:$src)>;
5394 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5395 (VMOVSHDUPYrr VR256:$src)>;
5396 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5397 (VMOVSHDUPYrm addr:$src)>;
5398 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5399 (VMOVSLDUPYrr VR256:$src)>;
5400 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5401 (VMOVSLDUPYrm addr:$src)>;
5404 let Predicates = [UseSSE3] in {
5405 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5406 (MOVSHDUPrr VR128:$src)>;
5407 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5408 (MOVSHDUPrm addr:$src)>;
5409 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5410 (MOVSLDUPrr VR128:$src)>;
5411 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5412 (MOVSLDUPrm addr:$src)>;
5415 //===---------------------------------------------------------------------===//
5416 // SSE3 - Replicate Double FP - MOVDDUP
5417 //===---------------------------------------------------------------------===//
5419 multiclass sse3_replicate_dfp<string OpcodeStr> {
5420 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5421 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5422 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5423 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5424 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5425 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5428 (scalar_to_vector (loadf64 addr:$src)))))],
5429 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5432 // FIXME: Merge with above classe when there're patterns for the ymm version
5433 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5434 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5435 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5436 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5437 Sched<[WriteFShuffle]>;
5438 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5439 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5442 (scalar_to_vector (loadf64 addr:$src)))))]>,
5446 let Predicates = [HasAVX] in {
5447 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5448 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5451 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5453 let Predicates = [HasAVX] in {
5454 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5455 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5456 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5457 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5458 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5459 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5460 def : Pat<(X86Movddup (bc_v2f64
5461 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5462 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5465 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5466 (VMOVDDUPYrm addr:$src)>;
5467 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5468 (VMOVDDUPYrm addr:$src)>;
5469 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5470 (VMOVDDUPYrm addr:$src)>;
5471 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5472 (VMOVDDUPYrr VR256:$src)>;
5475 let Predicates = [UseAVX, OptForSize] in {
5476 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5477 (VMOVDDUPrm addr:$src)>;
5478 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5479 (VMOVDDUPrm addr:$src)>;
5482 let Predicates = [UseSSE3] in {
5483 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5484 (MOVDDUPrm addr:$src)>;
5485 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5486 (MOVDDUPrm addr:$src)>;
5487 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5488 (MOVDDUPrm addr:$src)>;
5489 def : Pat<(X86Movddup (bc_v2f64
5490 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5491 (MOVDDUPrm addr:$src)>;
5494 //===---------------------------------------------------------------------===//
5495 // SSE3 - Move Unaligned Integer
5496 //===---------------------------------------------------------------------===//
5498 let SchedRW = [WriteLoad] in {
5499 let Predicates = [HasAVX] in {
5500 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5501 "vlddqu\t{$src, $dst|$dst, $src}",
5502 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5503 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5504 "vlddqu\t{$src, $dst|$dst, $src}",
5505 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5508 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5509 "lddqu\t{$src, $dst|$dst, $src}",
5510 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5514 //===---------------------------------------------------------------------===//
5515 // SSE3 - Arithmetic
5516 //===---------------------------------------------------------------------===//
5518 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5519 X86MemOperand x86memop, OpndItins itins,
5521 def rr : I<0xD0, MRMSrcReg,
5522 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5524 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5526 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5527 Sched<[itins.Sched]>;
5528 def rm : I<0xD0, MRMSrcMem,
5529 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5531 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5532 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5533 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5534 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5537 let Predicates = [HasAVX] in {
5538 let ExeDomain = SSEPackedSingle in {
5539 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5540 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5541 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5542 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5544 let ExeDomain = SSEPackedDouble in {
5545 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5546 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5547 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5548 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5551 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5552 let ExeDomain = SSEPackedSingle in
5553 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5554 f128mem, SSE_ALU_F32P>, XD;
5555 let ExeDomain = SSEPackedDouble in
5556 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5557 f128mem, SSE_ALU_F64P>, PD;
5560 // Patterns used to select 'addsub' instructions.
5561 let Predicates = [HasAVX] in {
5562 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5563 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5564 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5565 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5566 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5567 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5568 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5569 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5571 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5572 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5573 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5574 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5575 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5576 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5577 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5578 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5581 let Predicates = [UseSSE3] in {
5582 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5583 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5584 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5585 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5586 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5587 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5588 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5589 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5592 //===---------------------------------------------------------------------===//
5593 // SSE3 Instructions
5594 //===---------------------------------------------------------------------===//
5597 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5598 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5599 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5601 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5602 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5603 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5606 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5608 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5609 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5610 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5611 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5613 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5614 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5615 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5617 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5618 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5619 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5622 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5624 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5626 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5627 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5630 let Predicates = [HasAVX] in {
5631 let ExeDomain = SSEPackedSingle in {
5632 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5633 X86fhadd, 0>, VEX_4V;
5634 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5635 X86fhsub, 0>, VEX_4V;
5636 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5637 X86fhadd, 0>, VEX_4V, VEX_L;
5638 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5639 X86fhsub, 0>, VEX_4V, VEX_L;
5641 let ExeDomain = SSEPackedDouble in {
5642 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5643 X86fhadd, 0>, VEX_4V;
5644 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5645 X86fhsub, 0>, VEX_4V;
5646 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5647 X86fhadd, 0>, VEX_4V, VEX_L;
5648 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5649 X86fhsub, 0>, VEX_4V, VEX_L;
5653 let Constraints = "$src1 = $dst" in {
5654 let ExeDomain = SSEPackedSingle in {
5655 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5656 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5658 let ExeDomain = SSEPackedDouble in {
5659 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5660 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5664 //===---------------------------------------------------------------------===//
5665 // SSSE3 - Packed Absolute Instructions
5666 //===---------------------------------------------------------------------===//
5669 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5670 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5671 Intrinsic IntId128> {
5672 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5674 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5675 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5676 Sched<[WriteVecALU]>;
5678 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5680 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5683 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5684 Sched<[WriteVecALULd]>;
5687 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5688 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5689 Intrinsic IntId256> {
5690 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5692 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5693 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5694 Sched<[WriteVecALU]>;
5696 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5698 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5701 (bitconvert (memopv4i64 addr:$src))))]>,
5702 Sched<[WriteVecALULd]>;
5705 // Helper fragments to match sext vXi1 to vXiY.
5706 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5708 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5709 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5710 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5712 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5713 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5715 let Predicates = [HasAVX] in {
5716 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5717 int_x86_ssse3_pabs_b_128>, VEX;
5718 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5719 int_x86_ssse3_pabs_w_128>, VEX;
5720 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5721 int_x86_ssse3_pabs_d_128>, VEX;
5724 (bc_v2i64 (v16i1sextv16i8)),
5725 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5726 (VPABSBrr128 VR128:$src)>;
5728 (bc_v2i64 (v8i1sextv8i16)),
5729 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5730 (VPABSWrr128 VR128:$src)>;
5732 (bc_v2i64 (v4i1sextv4i32)),
5733 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5734 (VPABSDrr128 VR128:$src)>;
5737 let Predicates = [HasAVX2] in {
5738 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5739 int_x86_avx2_pabs_b>, VEX, VEX_L;
5740 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5741 int_x86_avx2_pabs_w>, VEX, VEX_L;
5742 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5743 int_x86_avx2_pabs_d>, VEX, VEX_L;
5746 (bc_v4i64 (v32i1sextv32i8)),
5747 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5748 (VPABSBrr256 VR256:$src)>;
5750 (bc_v4i64 (v16i1sextv16i16)),
5751 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5752 (VPABSWrr256 VR256:$src)>;
5754 (bc_v4i64 (v8i1sextv8i32)),
5755 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5756 (VPABSDrr256 VR256:$src)>;
5759 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5760 int_x86_ssse3_pabs_b_128>;
5761 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5762 int_x86_ssse3_pabs_w_128>;
5763 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5764 int_x86_ssse3_pabs_d_128>;
5766 let Predicates = [HasSSSE3] in {
5768 (bc_v2i64 (v16i1sextv16i8)),
5769 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5770 (PABSBrr128 VR128:$src)>;
5772 (bc_v2i64 (v8i1sextv8i16)),
5773 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5774 (PABSWrr128 VR128:$src)>;
5776 (bc_v2i64 (v4i1sextv4i32)),
5777 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5778 (PABSDrr128 VR128:$src)>;
5781 //===---------------------------------------------------------------------===//
5782 // SSSE3 - Packed Binary Operator Instructions
5783 //===---------------------------------------------------------------------===//
5785 let Sched = WriteVecALU in {
5786 def SSE_PHADDSUBD : OpndItins<
5787 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5789 def SSE_PHADDSUBSW : OpndItins<
5790 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5792 def SSE_PHADDSUBW : OpndItins<
5793 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5796 let Sched = WriteShuffle in
5797 def SSE_PSHUFB : OpndItins<
5798 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5800 let Sched = WriteVecALU in
5801 def SSE_PSIGN : OpndItins<
5802 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5804 let Sched = WriteVecIMul in
5805 def SSE_PMULHRSW : OpndItins<
5806 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5809 /// SS3I_binop_rm - Simple SSSE3 bin op
5810 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5811 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5812 X86MemOperand x86memop, OpndItins itins,
5814 let isCommutable = 1 in
5815 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5816 (ins RC:$src1, RC:$src2),
5818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5820 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5821 Sched<[itins.Sched]>;
5822 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5823 (ins RC:$src1, x86memop:$src2),
5825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5826 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5828 (OpVT (OpNode RC:$src1,
5829 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5830 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5833 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5834 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5835 Intrinsic IntId128, OpndItins itins,
5837 let isCommutable = 1 in
5838 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5839 (ins VR128:$src1, VR128:$src2),
5841 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5843 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5844 Sched<[itins.Sched]>;
5845 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5846 (ins VR128:$src1, i128mem:$src2),
5848 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5849 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5851 (IntId128 VR128:$src1,
5852 (bitconvert (memopv2i64 addr:$src2))))]>,
5853 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5856 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5858 X86FoldableSchedWrite Sched> {
5859 let isCommutable = 1 in
5860 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5861 (ins VR256:$src1, VR256:$src2),
5862 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5863 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5865 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5866 (ins VR256:$src1, i256mem:$src2),
5867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5869 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5870 Sched<[Sched.Folded, ReadAfterLd]>;
5873 let ImmT = NoImm, Predicates = [HasAVX] in {
5874 let isCommutable = 0 in {
5875 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5877 SSE_PHADDSUBW, 0>, VEX_4V;
5878 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5880 SSE_PHADDSUBD, 0>, VEX_4V;
5881 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5883 SSE_PHADDSUBW, 0>, VEX_4V;
5884 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5886 SSE_PHADDSUBD, 0>, VEX_4V;
5887 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5889 SSE_PSIGN, 0>, VEX_4V;
5890 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5892 SSE_PSIGN, 0>, VEX_4V;
5893 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5895 SSE_PSIGN, 0>, VEX_4V;
5896 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5898 SSE_PSHUFB, 0>, VEX_4V;
5899 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5900 int_x86_ssse3_phadd_sw_128,
5901 SSE_PHADDSUBSW, 0>, VEX_4V;
5902 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5903 int_x86_ssse3_phsub_sw_128,
5904 SSE_PHADDSUBSW, 0>, VEX_4V;
5905 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5906 int_x86_ssse3_pmadd_ub_sw_128,
5907 SSE_PMADD, 0>, VEX_4V;
5909 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5910 int_x86_ssse3_pmul_hr_sw_128,
5911 SSE_PMULHRSW, 0>, VEX_4V;
5914 let ImmT = NoImm, Predicates = [HasAVX2] in {
5915 let isCommutable = 0 in {
5916 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5918 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5919 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5921 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5922 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5924 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5925 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5927 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5928 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5930 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5931 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5933 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5934 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5936 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5937 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5939 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5940 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5941 int_x86_avx2_phadd_sw,
5942 WriteVecALU>, VEX_4V, VEX_L;
5943 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5944 int_x86_avx2_phsub_sw,
5945 WriteVecALU>, VEX_4V, VEX_L;
5946 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5947 int_x86_avx2_pmadd_ub_sw,
5948 WriteVecIMul>, VEX_4V, VEX_L;
5950 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5951 int_x86_avx2_pmul_hr_sw,
5952 WriteVecIMul>, VEX_4V, VEX_L;
5955 // None of these have i8 immediate fields.
5956 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5957 let isCommutable = 0 in {
5958 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5959 memopv2i64, i128mem, SSE_PHADDSUBW>;
5960 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5961 memopv2i64, i128mem, SSE_PHADDSUBD>;
5962 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5963 memopv2i64, i128mem, SSE_PHADDSUBW>;
5964 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5965 memopv2i64, i128mem, SSE_PHADDSUBD>;
5966 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5967 memopv2i64, i128mem, SSE_PSIGN>;
5968 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5969 memopv2i64, i128mem, SSE_PSIGN>;
5970 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5971 memopv2i64, i128mem, SSE_PSIGN>;
5972 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5973 memopv2i64, i128mem, SSE_PSHUFB>;
5974 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5975 int_x86_ssse3_phadd_sw_128,
5977 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5978 int_x86_ssse3_phsub_sw_128,
5980 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5981 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5983 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5984 int_x86_ssse3_pmul_hr_sw_128,
5988 //===---------------------------------------------------------------------===//
5989 // SSSE3 - Packed Align Instruction Patterns
5990 //===---------------------------------------------------------------------===//
5992 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5993 let hasSideEffects = 0 in {
5994 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5995 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5997 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5999 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6000 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
6002 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
6003 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
6005 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6007 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6008 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6012 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
6013 let hasSideEffects = 0 in {
6014 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
6015 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
6017 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6018 []>, Sched<[WriteShuffle]>;
6020 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
6021 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
6023 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6024 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6028 let Predicates = [HasAVX] in
6029 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
6030 let Predicates = [HasAVX2] in
6031 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
6032 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
6033 defm PALIGN : ssse3_palignr<"palignr">;
6035 let Predicates = [HasAVX2] in {
6036 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6037 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6038 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6039 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6040 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6041 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6042 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6043 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6046 let Predicates = [HasAVX] in {
6047 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6048 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6049 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6050 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6051 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6052 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6053 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6054 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6057 let Predicates = [UseSSSE3] in {
6058 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6059 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6060 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6061 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6062 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6063 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6064 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6065 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6068 //===---------------------------------------------------------------------===//
6069 // SSSE3 - Thread synchronization
6070 //===---------------------------------------------------------------------===//
6072 let SchedRW = [WriteSystem] in {
6073 let usesCustomInserter = 1 in {
6074 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
6075 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
6076 Requires<[HasSSE3]>;
6079 let Uses = [EAX, ECX, EDX] in
6080 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
6081 TB, Requires<[HasSSE3]>;
6082 let Uses = [ECX, EAX] in
6083 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
6084 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
6085 TB, Requires<[HasSSE3]>;
6088 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
6089 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
6091 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
6092 Requires<[Not64BitMode]>;
6093 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
6094 Requires<[In64BitMode]>;
6096 //===----------------------------------------------------------------------===//
6097 // SSE4.1 - Packed Move with Sign/Zero Extend
6098 //===----------------------------------------------------------------------===//
6100 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
6101 RegisterClass OutRC, RegisterClass InRC,
6103 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
6104 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6106 Sched<[itins.Sched]>;
6108 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
6109 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6111 itins.rm>, Sched<[itins.Sched.Folded]>;
6114 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
6115 X86MemOperand MemOp, X86MemOperand MemYOp,
6116 OpndItins SSEItins, OpndItins AVXItins,
6117 OpndItins AVX2Itins> {
6118 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
6119 let Predicates = [HasAVX] in
6120 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
6121 VR128, VR128, AVXItins>, VEX;
6122 let Predicates = [HasAVX2] in
6123 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
6124 VR256, VR128, AVX2Itins>, VEX, VEX_L;
6127 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
6128 X86MemOperand MemOp, X86MemOperand MemYOp> {
6129 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
6131 SSE_INTALU_ITINS_SHUFF_P,
6132 DEFAULT_ITINS_SHUFFLESCHED,
6133 DEFAULT_ITINS_SHUFFLESCHED>;
6134 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
6135 !strconcat("pmovzx", OpcodeStr),
6137 SSE_INTALU_ITINS_SHUFF_P,
6138 DEFAULT_ITINS_SHUFFLESCHED,
6139 DEFAULT_ITINS_SHUFFLESCHED>;
6142 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
6143 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
6144 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
6146 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
6147 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
6149 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
6152 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
6153 // Register-Register patterns
6154 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
6155 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
6156 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
6157 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
6158 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
6159 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
6161 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
6162 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
6163 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
6164 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
6166 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
6167 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
6169 // On AVX2, we also support 256bit inputs.
6170 // FIXME: remove these patterns when the old shuffle lowering goes away.
6171 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
6172 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6173 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
6174 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6175 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
6176 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6178 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
6179 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6180 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
6181 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6183 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
6184 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6186 // Simple Register-Memory patterns
6187 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6188 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6189 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6190 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6191 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6192 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6194 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6195 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6196 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6197 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6199 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6200 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6202 // AVX2 Register-Memory patterns
6203 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6204 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6205 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6206 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6207 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6208 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6209 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6210 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6212 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6213 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6214 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6215 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6216 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6217 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6218 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6219 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6221 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6222 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6223 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6224 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6225 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6226 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6227 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6228 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6230 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6231 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6232 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6233 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6234 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6235 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6236 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6237 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6239 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6240 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6241 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6242 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6243 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6244 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6245 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6246 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6248 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6249 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6250 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6251 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6252 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6253 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6254 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6255 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6258 let Predicates = [HasAVX2] in {
6259 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6260 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6263 // SSE4.1/AVX patterns.
6264 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6265 SDNode ExtOp, PatFrag ExtLoad16> {
6266 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6267 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6268 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6269 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6270 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6271 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6273 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6274 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6275 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6276 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6278 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6279 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6281 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6282 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6283 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6284 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6285 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6286 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6288 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6289 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6290 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6291 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6293 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6294 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6296 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6297 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6298 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6299 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6300 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6301 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6302 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6303 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6304 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6305 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6307 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6308 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6309 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6310 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6311 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6312 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6313 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6314 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6316 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6317 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6318 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6319 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6320 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6321 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6322 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6323 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6325 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6326 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6327 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6328 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6329 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6330 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6331 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6332 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6333 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6334 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6336 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6337 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6338 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6339 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6340 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6341 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6342 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6343 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6345 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6346 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6347 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6348 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6349 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6350 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6351 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6352 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6353 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6354 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6357 let Predicates = [HasAVX] in {
6358 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6359 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6362 let Predicates = [UseSSE41] in {
6363 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6364 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6367 //===----------------------------------------------------------------------===//
6368 // SSE4.1 - Extract Instructions
6369 //===----------------------------------------------------------------------===//
6371 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6372 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6373 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6374 (ins VR128:$src1, u8imm:$src2),
6375 !strconcat(OpcodeStr,
6376 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6377 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6379 Sched<[WriteShuffle]>;
6380 let hasSideEffects = 0, mayStore = 1,
6381 SchedRW = [WriteShuffleLd, WriteRMW] in
6382 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6383 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6384 !strconcat(OpcodeStr,
6385 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6386 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6387 imm:$src2)))), addr:$dst)]>;
6390 let Predicates = [HasAVX] in
6391 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6393 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6396 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6397 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6398 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6399 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6400 (ins VR128:$src1, u8imm:$src2),
6401 !strconcat(OpcodeStr,
6402 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6403 []>, Sched<[WriteShuffle]>;
6405 let hasSideEffects = 0, mayStore = 1,
6406 SchedRW = [WriteShuffleLd, WriteRMW] in
6407 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6408 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6409 !strconcat(OpcodeStr,
6410 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6411 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6412 imm:$src2)))), addr:$dst)]>;
6415 let Predicates = [HasAVX] in
6416 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6418 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6421 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6422 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6423 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6424 (ins VR128:$src1, u8imm:$src2),
6425 !strconcat(OpcodeStr,
6426 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6428 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6429 Sched<[WriteShuffle]>;
6430 let SchedRW = [WriteShuffleLd, WriteRMW] in
6431 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6432 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6433 !strconcat(OpcodeStr,
6434 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6435 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6439 let Predicates = [HasAVX] in
6440 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6442 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6444 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6445 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6446 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6447 (ins VR128:$src1, u8imm:$src2),
6448 !strconcat(OpcodeStr,
6449 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6451 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6452 Sched<[WriteShuffle]>, REX_W;
6453 let SchedRW = [WriteShuffleLd, WriteRMW] in
6454 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6455 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6456 !strconcat(OpcodeStr,
6457 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6458 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6459 addr:$dst)]>, REX_W;
6462 let Predicates = [HasAVX] in
6463 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6465 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6467 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6469 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6470 OpndItins itins = DEFAULT_ITINS> {
6471 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6472 (ins VR128:$src1, u8imm:$src2),
6473 !strconcat(OpcodeStr,
6474 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6475 [(set GR32orGR64:$dst,
6476 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6477 itins.rr>, Sched<[WriteFBlend]>;
6478 let SchedRW = [WriteFBlendLd, WriteRMW] in
6479 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6480 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6481 !strconcat(OpcodeStr,
6482 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6483 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6484 addr:$dst)], itins.rm>;
6487 let ExeDomain = SSEPackedSingle in {
6488 let Predicates = [UseAVX] in
6489 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6490 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6493 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6494 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6497 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6499 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6502 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6503 Requires<[UseSSE41]>;
6505 //===----------------------------------------------------------------------===//
6506 // SSE4.1 - Insert Instructions
6507 //===----------------------------------------------------------------------===//
6509 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6510 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6511 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6513 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6515 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6517 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6518 Sched<[WriteShuffle]>;
6519 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6520 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6522 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6524 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6526 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6527 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6530 let Predicates = [HasAVX] in
6531 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6532 let Constraints = "$src1 = $dst" in
6533 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6535 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6536 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6537 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6539 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6541 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6543 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6544 Sched<[WriteShuffle]>;
6545 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6546 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6548 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6550 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6552 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6553 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6556 let Predicates = [HasAVX] in
6557 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6558 let Constraints = "$src1 = $dst" in
6559 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6561 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6562 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6563 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6565 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6567 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6569 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6570 Sched<[WriteShuffle]>;
6571 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6572 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6574 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6576 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6578 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6579 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6582 let Predicates = [HasAVX] in
6583 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6584 let Constraints = "$src1 = $dst" in
6585 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6587 // insertps has a few different modes, there's the first two here below which
6588 // are optimized inserts that won't zero arbitrary elements in the destination
6589 // vector. The next one matches the intrinsic and could zero arbitrary elements
6590 // in the target vector.
6591 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6592 OpndItins itins = DEFAULT_ITINS> {
6593 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6594 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6596 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6598 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6600 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6601 Sched<[WriteFShuffle]>;
6602 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6603 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6605 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6607 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6609 (X86insertps VR128:$src1,
6610 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6611 imm:$src3))], itins.rm>,
6612 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6615 let ExeDomain = SSEPackedSingle in {
6616 let Predicates = [UseAVX] in
6617 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6618 let Constraints = "$src1 = $dst" in
6619 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6622 let Predicates = [UseSSE41] in {
6623 // If we're inserting an element from a load or a null pshuf of a load,
6624 // fold the load into the insertps instruction.
6625 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6626 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6628 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6629 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6630 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6631 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6634 let Predicates = [UseAVX] in {
6635 // If we're inserting an element from a vbroadcast of a load, fold the
6636 // load into the X86insertps instruction.
6637 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6638 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6639 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6640 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6641 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6642 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6645 //===----------------------------------------------------------------------===//
6646 // SSE4.1 - Round Instructions
6647 //===----------------------------------------------------------------------===//
6649 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6650 X86MemOperand x86memop, RegisterClass RC,
6651 PatFrag mem_frag32, PatFrag mem_frag64,
6652 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6653 let ExeDomain = SSEPackedSingle in {
6654 // Intrinsic operation, reg.
6655 // Vector intrinsic operation, reg
6656 def PSr : SS4AIi8<opcps, MRMSrcReg,
6657 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6658 !strconcat(OpcodeStr,
6659 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6660 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6661 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6663 // Vector intrinsic operation, mem
6664 def PSm : SS4AIi8<opcps, MRMSrcMem,
6665 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6666 !strconcat(OpcodeStr,
6667 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6669 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6670 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6671 } // ExeDomain = SSEPackedSingle
6673 let ExeDomain = SSEPackedDouble in {
6674 // Vector intrinsic operation, reg
6675 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6676 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6677 !strconcat(OpcodeStr,
6678 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6679 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6680 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6682 // Vector intrinsic operation, mem
6683 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6684 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6685 !strconcat(OpcodeStr,
6686 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6688 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6689 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6690 } // ExeDomain = SSEPackedDouble
6693 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6696 Intrinsic F64Int, bit Is2Addr = 1> {
6697 let ExeDomain = GenericDomain in {
6699 let hasSideEffects = 0 in
6700 def SSr : SS4AIi8<opcss, MRMSrcReg,
6701 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6703 !strconcat(OpcodeStr,
6704 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6705 !strconcat(OpcodeStr,
6706 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6707 []>, Sched<[WriteFAdd]>;
6709 // Intrinsic operation, reg.
6710 let isCodeGenOnly = 1 in
6711 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6712 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6714 !strconcat(OpcodeStr,
6715 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6716 !strconcat(OpcodeStr,
6717 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6718 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6721 // Intrinsic operation, mem.
6722 def SSm : SS4AIi8<opcss, MRMSrcMem,
6723 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6725 !strconcat(OpcodeStr,
6726 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6727 !strconcat(OpcodeStr,
6728 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6730 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6731 Sched<[WriteFAddLd, ReadAfterLd]>;
6734 let hasSideEffects = 0 in
6735 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6736 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6738 !strconcat(OpcodeStr,
6739 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6740 !strconcat(OpcodeStr,
6741 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6742 []>, Sched<[WriteFAdd]>;
6744 // Intrinsic operation, reg.
6745 let isCodeGenOnly = 1 in
6746 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6747 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6749 !strconcat(OpcodeStr,
6750 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6751 !strconcat(OpcodeStr,
6752 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6753 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6756 // Intrinsic operation, mem.
6757 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6758 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6760 !strconcat(OpcodeStr,
6761 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6762 !strconcat(OpcodeStr,
6763 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6765 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6766 Sched<[WriteFAddLd, ReadAfterLd]>;
6767 } // ExeDomain = GenericDomain
6770 // FP round - roundss, roundps, roundsd, roundpd
6771 let Predicates = [HasAVX] in {
6773 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6774 loadv4f32, loadv2f64,
6775 int_x86_sse41_round_ps,
6776 int_x86_sse41_round_pd>, VEX;
6777 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6778 loadv8f32, loadv4f64,
6779 int_x86_avx_round_ps_256,
6780 int_x86_avx_round_pd_256>, VEX, VEX_L;
6781 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6782 int_x86_sse41_round_ss,
6783 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6786 let Predicates = [UseAVX] in {
6787 def : Pat<(ffloor FR32:$src),
6788 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6789 def : Pat<(f64 (ffloor FR64:$src)),
6790 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6791 def : Pat<(f32 (fnearbyint FR32:$src)),
6792 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6793 def : Pat<(f64 (fnearbyint FR64:$src)),
6794 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6795 def : Pat<(f32 (fceil FR32:$src)),
6796 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6797 def : Pat<(f64 (fceil FR64:$src)),
6798 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6799 def : Pat<(f32 (frint FR32:$src)),
6800 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6801 def : Pat<(f64 (frint FR64:$src)),
6802 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6803 def : Pat<(f32 (ftrunc FR32:$src)),
6804 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6805 def : Pat<(f64 (ftrunc FR64:$src)),
6806 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6809 let Predicates = [HasAVX] in {
6810 def : Pat<(v4f32 (ffloor VR128:$src)),
6811 (VROUNDPSr VR128:$src, (i32 0x1))>;
6812 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6813 (VROUNDPSr VR128:$src, (i32 0xC))>;
6814 def : Pat<(v4f32 (fceil VR128:$src)),
6815 (VROUNDPSr VR128:$src, (i32 0x2))>;
6816 def : Pat<(v4f32 (frint VR128:$src)),
6817 (VROUNDPSr VR128:$src, (i32 0x4))>;
6818 def : Pat<(v4f32 (ftrunc VR128:$src)),
6819 (VROUNDPSr VR128:$src, (i32 0x3))>;
6821 def : Pat<(v2f64 (ffloor VR128:$src)),
6822 (VROUNDPDr VR128:$src, (i32 0x1))>;
6823 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6824 (VROUNDPDr VR128:$src, (i32 0xC))>;
6825 def : Pat<(v2f64 (fceil VR128:$src)),
6826 (VROUNDPDr VR128:$src, (i32 0x2))>;
6827 def : Pat<(v2f64 (frint VR128:$src)),
6828 (VROUNDPDr VR128:$src, (i32 0x4))>;
6829 def : Pat<(v2f64 (ftrunc VR128:$src)),
6830 (VROUNDPDr VR128:$src, (i32 0x3))>;
6832 def : Pat<(v8f32 (ffloor VR256:$src)),
6833 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6834 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6835 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6836 def : Pat<(v8f32 (fceil VR256:$src)),
6837 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6838 def : Pat<(v8f32 (frint VR256:$src)),
6839 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6840 def : Pat<(v8f32 (ftrunc VR256:$src)),
6841 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6843 def : Pat<(v4f64 (ffloor VR256:$src)),
6844 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6845 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6846 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6847 def : Pat<(v4f64 (fceil VR256:$src)),
6848 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6849 def : Pat<(v4f64 (frint VR256:$src)),
6850 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6851 def : Pat<(v4f64 (ftrunc VR256:$src)),
6852 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6855 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6856 memopv4f32, memopv2f64,
6857 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6858 let Constraints = "$src1 = $dst" in
6859 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6860 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6862 let Predicates = [UseSSE41] in {
6863 def : Pat<(ffloor FR32:$src),
6864 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6865 def : Pat<(f64 (ffloor FR64:$src)),
6866 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6867 def : Pat<(f32 (fnearbyint FR32:$src)),
6868 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6869 def : Pat<(f64 (fnearbyint FR64:$src)),
6870 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6871 def : Pat<(f32 (fceil FR32:$src)),
6872 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6873 def : Pat<(f64 (fceil FR64:$src)),
6874 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6875 def : Pat<(f32 (frint FR32:$src)),
6876 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6877 def : Pat<(f64 (frint FR64:$src)),
6878 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6879 def : Pat<(f32 (ftrunc FR32:$src)),
6880 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6881 def : Pat<(f64 (ftrunc FR64:$src)),
6882 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6884 def : Pat<(v4f32 (ffloor VR128:$src)),
6885 (ROUNDPSr VR128:$src, (i32 0x1))>;
6886 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6887 (ROUNDPSr VR128:$src, (i32 0xC))>;
6888 def : Pat<(v4f32 (fceil VR128:$src)),
6889 (ROUNDPSr VR128:$src, (i32 0x2))>;
6890 def : Pat<(v4f32 (frint VR128:$src)),
6891 (ROUNDPSr VR128:$src, (i32 0x4))>;
6892 def : Pat<(v4f32 (ftrunc VR128:$src)),
6893 (ROUNDPSr VR128:$src, (i32 0x3))>;
6895 def : Pat<(v2f64 (ffloor VR128:$src)),
6896 (ROUNDPDr VR128:$src, (i32 0x1))>;
6897 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6898 (ROUNDPDr VR128:$src, (i32 0xC))>;
6899 def : Pat<(v2f64 (fceil VR128:$src)),
6900 (ROUNDPDr VR128:$src, (i32 0x2))>;
6901 def : Pat<(v2f64 (frint VR128:$src)),
6902 (ROUNDPDr VR128:$src, (i32 0x4))>;
6903 def : Pat<(v2f64 (ftrunc VR128:$src)),
6904 (ROUNDPDr VR128:$src, (i32 0x3))>;
6907 //===----------------------------------------------------------------------===//
6908 // SSE4.1 - Packed Bit Test
6909 //===----------------------------------------------------------------------===//
6911 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6912 // the intel intrinsic that corresponds to this.
6913 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6914 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6915 "vptest\t{$src2, $src1|$src1, $src2}",
6916 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6917 Sched<[WriteVecLogic]>, VEX;
6918 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6919 "vptest\t{$src2, $src1|$src1, $src2}",
6920 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6921 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6923 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6924 "vptest\t{$src2, $src1|$src1, $src2}",
6925 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6926 Sched<[WriteVecLogic]>, VEX, VEX_L;
6927 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6928 "vptest\t{$src2, $src1|$src1, $src2}",
6929 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6930 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6933 let Defs = [EFLAGS] in {
6934 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6935 "ptest\t{$src2, $src1|$src1, $src2}",
6936 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6937 Sched<[WriteVecLogic]>;
6938 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6939 "ptest\t{$src2, $src1|$src1, $src2}",
6940 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6941 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6944 // The bit test instructions below are AVX only
6945 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6946 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6947 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6949 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6950 Sched<[WriteVecLogic]>, VEX;
6951 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6952 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6953 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6954 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6957 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6958 let ExeDomain = SSEPackedSingle in {
6959 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6960 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6963 let ExeDomain = SSEPackedDouble in {
6964 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6965 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6970 //===----------------------------------------------------------------------===//
6971 // SSE4.1 - Misc Instructions
6972 //===----------------------------------------------------------------------===//
6974 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6975 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6976 "popcnt{w}\t{$src, $dst|$dst, $src}",
6977 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6978 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6980 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6981 "popcnt{w}\t{$src, $dst|$dst, $src}",
6982 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6983 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6984 Sched<[WriteFAddLd]>, OpSize16, XS;
6986 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6987 "popcnt{l}\t{$src, $dst|$dst, $src}",
6988 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6989 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6992 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6993 "popcnt{l}\t{$src, $dst|$dst, $src}",
6994 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6995 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6996 Sched<[WriteFAddLd]>, OpSize32, XS;
6998 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6999 "popcnt{q}\t{$src, $dst|$dst, $src}",
7000 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
7001 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
7002 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
7003 "popcnt{q}\t{$src, $dst|$dst, $src}",
7004 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
7005 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7006 Sched<[WriteFAddLd]>, XS;
7011 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
7012 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
7014 X86FoldableSchedWrite Sched> {
7015 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7017 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7018 [(set VR128:$dst, (IntId128 VR128:$src))]>,
7020 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7022 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7024 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7025 Sched<[Sched.Folded]>;
7028 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7029 // model, although the naming is misleading.
7030 let Predicates = [HasAVX] in
7031 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7032 int_x86_sse41_phminposuw,
7034 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7035 int_x86_sse41_phminposuw,
7038 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7039 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7040 Intrinsic IntId128, bit Is2Addr = 1,
7041 OpndItins itins = DEFAULT_ITINS> {
7042 let isCommutable = 1 in
7043 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7044 (ins VR128:$src1, VR128:$src2),
7046 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7047 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7048 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7049 itins.rr>, Sched<[itins.Sched]>;
7050 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7051 (ins VR128:$src1, i128mem:$src2),
7053 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7056 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7057 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7060 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7061 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7063 X86FoldableSchedWrite Sched> {
7064 let isCommutable = 1 in
7065 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7066 (ins VR256:$src1, VR256:$src2),
7067 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7068 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7070 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7071 (ins VR256:$src1, i256mem:$src2),
7072 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7074 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7075 Sched<[Sched.Folded, ReadAfterLd]>;
7079 /// SS48I_binop_rm - Simple SSE41 binary operator.
7080 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7081 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7082 X86MemOperand x86memop, bit Is2Addr = 1,
7083 OpndItins itins = SSE_INTALU_ITINS_P> {
7084 let isCommutable = 1 in
7085 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7086 (ins RC:$src1, RC:$src2),
7088 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7089 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7090 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7091 Sched<[itins.Sched]>;
7092 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7093 (ins RC:$src1, x86memop:$src2),
7095 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7096 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7098 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7099 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7102 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7104 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7105 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7106 PatFrag memop_frag, X86MemOperand x86memop,
7108 bit IsCommutable = 0, bit Is2Addr = 1> {
7109 let isCommutable = IsCommutable in
7110 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7111 (ins RC:$src1, RC:$src2),
7113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7115 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7116 Sched<[itins.Sched]>;
7117 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7118 (ins RC:$src1, x86memop:$src2),
7120 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7122 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7123 (bitconvert (memop_frag addr:$src2)))))]>,
7124 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7127 let Predicates = [HasAVX, NoVLX] in {
7128 let isCommutable = 0 in
7129 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7130 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7132 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7133 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7135 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7136 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7138 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7139 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7141 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7142 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7144 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7145 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7147 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7148 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7150 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7151 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7153 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7154 VR128, loadv2i64, i128mem,
7155 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7158 let Predicates = [HasAVX2, NoVLX] in {
7159 let isCommutable = 0 in
7160 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7161 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7163 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7164 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7166 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7167 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7169 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7170 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7172 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7173 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7175 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7176 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7178 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7179 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7181 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7182 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7184 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7185 VR256, loadv4i64, i256mem,
7186 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7189 let Constraints = "$src1 = $dst" in {
7190 let isCommutable = 0 in
7191 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7192 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7193 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7194 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7195 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7196 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7197 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7198 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7199 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7200 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7201 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7202 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7203 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7204 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7205 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7206 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7207 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7208 VR128, memopv2i64, i128mem,
7209 SSE_INTMUL_ITINS_P, 1>;
7212 let Predicates = [HasAVX, NoVLX] in {
7213 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7214 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7216 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7217 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7220 let Predicates = [HasAVX2] in {
7221 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7222 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7224 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7225 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7229 let Constraints = "$src1 = $dst" in {
7230 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7231 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7232 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7233 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7236 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7237 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7238 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7239 X86MemOperand x86memop, bit Is2Addr = 1,
7240 OpndItins itins = DEFAULT_ITINS> {
7241 let isCommutable = 1 in
7242 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7243 (ins RC:$src1, RC:$src2, u8imm:$src3),
7245 !strconcat(OpcodeStr,
7246 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7247 !strconcat(OpcodeStr,
7248 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7249 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7250 Sched<[itins.Sched]>;
7251 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7252 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
7254 !strconcat(OpcodeStr,
7255 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7256 !strconcat(OpcodeStr,
7257 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7260 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7261 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7264 let Predicates = [HasAVX] in {
7265 let isCommutable = 0 in {
7266 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7267 VR128, loadv2i64, i128mem, 0,
7268 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7271 let ExeDomain = SSEPackedSingle in {
7272 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7273 VR128, loadv4f32, f128mem, 0,
7274 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7275 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7276 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7277 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7280 let ExeDomain = SSEPackedDouble in {
7281 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7282 VR128, loadv2f64, f128mem, 0,
7283 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7284 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7285 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7286 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7289 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7290 VR128, loadv2i64, i128mem, 0,
7291 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7293 let ExeDomain = SSEPackedSingle in
7294 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7295 VR128, loadv4f32, f128mem, 0,
7296 SSE_DPPS_ITINS>, VEX_4V;
7297 let ExeDomain = SSEPackedDouble in
7298 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7299 VR128, loadv2f64, f128mem, 0,
7300 SSE_DPPS_ITINS>, VEX_4V;
7301 let ExeDomain = SSEPackedSingle in
7302 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7303 VR256, loadv8f32, i256mem, 0,
7304 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7307 let Predicates = [HasAVX2] in {
7308 let isCommutable = 0 in {
7309 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7310 VR256, loadv4i64, i256mem, 0,
7311 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7313 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7314 VR256, loadv4i64, i256mem, 0,
7315 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7318 let Constraints = "$src1 = $dst" in {
7319 let isCommutable = 0 in {
7320 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7321 VR128, memopv2i64, i128mem,
7322 1, SSE_MPSADBW_ITINS>;
7324 let ExeDomain = SSEPackedSingle in
7325 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7326 VR128, memopv4f32, f128mem,
7327 1, SSE_INTALU_ITINS_FBLEND_P>;
7328 let ExeDomain = SSEPackedDouble in
7329 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7330 VR128, memopv2f64, f128mem,
7331 1, SSE_INTALU_ITINS_FBLEND_P>;
7332 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7333 VR128, memopv2i64, i128mem,
7334 1, SSE_INTALU_ITINS_BLEND_P>;
7335 let ExeDomain = SSEPackedSingle in
7336 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7337 VR128, memopv4f32, f128mem, 1,
7339 let ExeDomain = SSEPackedDouble in
7340 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7341 VR128, memopv2f64, f128mem, 1,
7345 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7346 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7347 RegisterClass RC, X86MemOperand x86memop,
7348 PatFrag mem_frag, Intrinsic IntId,
7349 X86FoldableSchedWrite Sched> {
7350 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7351 (ins RC:$src1, RC:$src2, RC:$src3),
7352 !strconcat(OpcodeStr,
7353 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7354 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7355 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7358 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7359 (ins RC:$src1, x86memop:$src2, RC:$src3),
7360 !strconcat(OpcodeStr,
7361 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7363 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7365 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7366 Sched<[Sched.Folded, ReadAfterLd]>;
7369 let Predicates = [HasAVX] in {
7370 let ExeDomain = SSEPackedDouble in {
7371 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7372 loadv2f64, int_x86_sse41_blendvpd,
7374 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7375 loadv4f64, int_x86_avx_blendv_pd_256,
7376 WriteFVarBlend>, VEX_L;
7377 } // ExeDomain = SSEPackedDouble
7378 let ExeDomain = SSEPackedSingle in {
7379 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7380 loadv4f32, int_x86_sse41_blendvps,
7382 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7383 loadv8f32, int_x86_avx_blendv_ps_256,
7384 WriteFVarBlend>, VEX_L;
7385 } // ExeDomain = SSEPackedSingle
7386 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7387 loadv2i64, int_x86_sse41_pblendvb,
7391 let Predicates = [HasAVX2] in {
7392 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7393 loadv4i64, int_x86_avx2_pblendvb,
7394 WriteVarBlend>, VEX_L;
7397 let Predicates = [HasAVX] in {
7398 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7399 (v16i8 VR128:$src2))),
7400 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7401 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7402 (v4i32 VR128:$src2))),
7403 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7404 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7405 (v4f32 VR128:$src2))),
7406 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7407 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7408 (v2i64 VR128:$src2))),
7409 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7410 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7411 (v2f64 VR128:$src2))),
7412 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7413 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7414 (v8i32 VR256:$src2))),
7415 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7416 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7417 (v8f32 VR256:$src2))),
7418 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7419 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7420 (v4i64 VR256:$src2))),
7421 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7422 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7423 (v4f64 VR256:$src2))),
7424 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7426 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7428 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7429 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7431 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7433 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7435 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7436 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7438 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7439 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7441 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7444 let Predicates = [HasAVX2] in {
7445 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7446 (v32i8 VR256:$src2))),
7447 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7448 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7450 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7454 let Predicates = [UseAVX] in {
7455 let AddedComplexity = 15 in {
7456 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7457 // MOVS{S,D} to the lower bits.
7458 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7459 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7460 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7461 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7462 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7463 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7464 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7465 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7467 // Move low f32 and clear high bits.
7468 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7469 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7470 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7471 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7474 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7475 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7476 (SUBREG_TO_REG (i32 0),
7477 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7479 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7480 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7481 (SUBREG_TO_REG (i64 0),
7482 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7485 // Move low f64 and clear high bits.
7486 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7487 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7489 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7490 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7493 let Predicates = [UseSSE41] in {
7494 // With SSE41 we can use blends for these patterns.
7495 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7496 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7497 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7498 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7499 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7500 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7504 /// SS41I_ternary_int - SSE 4.1 ternary operator
7505 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7506 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7507 X86MemOperand x86memop, Intrinsic IntId,
7508 OpndItins itins = DEFAULT_ITINS> {
7509 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7510 (ins VR128:$src1, VR128:$src2),
7511 !strconcat(OpcodeStr,
7512 "\t{$src2, $dst|$dst, $src2}"),
7513 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7514 itins.rr>, Sched<[itins.Sched]>;
7516 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7517 (ins VR128:$src1, x86memop:$src2),
7518 !strconcat(OpcodeStr,
7519 "\t{$src2, $dst|$dst, $src2}"),
7522 (bitconvert (mem_frag addr:$src2)), XMM0))],
7523 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7527 let ExeDomain = SSEPackedDouble in
7528 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7529 int_x86_sse41_blendvpd,
7530 DEFAULT_ITINS_FBLENDSCHED>;
7531 let ExeDomain = SSEPackedSingle in
7532 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7533 int_x86_sse41_blendvps,
7534 DEFAULT_ITINS_FBLENDSCHED>;
7535 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7536 int_x86_sse41_pblendvb,
7537 DEFAULT_ITINS_VARBLENDSCHED>;
7539 // Aliases with the implicit xmm0 argument
7540 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7541 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7542 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7543 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7544 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7545 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7546 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7547 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7548 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7549 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7550 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7551 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7553 let Predicates = [UseSSE41] in {
7554 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7555 (v16i8 VR128:$src2))),
7556 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7557 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7558 (v4i32 VR128:$src2))),
7559 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7560 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7561 (v4f32 VR128:$src2))),
7562 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7563 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7564 (v2i64 VR128:$src2))),
7565 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7566 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7567 (v2f64 VR128:$src2))),
7568 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7570 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7572 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7573 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7575 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7576 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7578 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7582 let SchedRW = [WriteLoad] in {
7583 let Predicates = [HasAVX] in
7584 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7585 "vmovntdqa\t{$src, $dst|$dst, $src}",
7586 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7588 let Predicates = [HasAVX2] in
7589 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7590 "vmovntdqa\t{$src, $dst|$dst, $src}",
7591 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7593 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7594 "movntdqa\t{$src, $dst|$dst, $src}",
7595 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7598 //===----------------------------------------------------------------------===//
7599 // SSE4.2 - Compare Instructions
7600 //===----------------------------------------------------------------------===//
7602 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7603 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7604 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7605 X86MemOperand x86memop, bit Is2Addr = 1> {
7606 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7607 (ins RC:$src1, RC:$src2),
7609 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7611 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7612 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7613 (ins RC:$src1, x86memop:$src2),
7615 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7618 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7621 let Predicates = [HasAVX] in
7622 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7623 loadv2i64, i128mem, 0>, VEX_4V;
7625 let Predicates = [HasAVX2] in
7626 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7627 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7629 let Constraints = "$src1 = $dst" in
7630 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7631 memopv2i64, i128mem>;
7633 //===----------------------------------------------------------------------===//
7634 // SSE4.2 - String/text Processing Instructions
7635 //===----------------------------------------------------------------------===//
7637 // Packed Compare Implicit Length Strings, Return Mask
7638 multiclass pseudo_pcmpistrm<string asm> {
7639 def REG : PseudoI<(outs VR128:$dst),
7640 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7641 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7643 def MEM : PseudoI<(outs VR128:$dst),
7644 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7645 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7646 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7649 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7650 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7651 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7654 multiclass pcmpistrm_SS42AI<string asm> {
7655 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7656 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7657 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7658 []>, Sched<[WritePCmpIStrM]>;
7660 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7661 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7662 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7663 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7666 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7667 let Predicates = [HasAVX] in
7668 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7669 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7672 // Packed Compare Explicit Length Strings, Return Mask
7673 multiclass pseudo_pcmpestrm<string asm> {
7674 def REG : PseudoI<(outs VR128:$dst),
7675 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7676 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7677 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7678 def MEM : PseudoI<(outs VR128:$dst),
7679 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7680 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7681 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7684 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7685 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7686 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7689 multiclass SS42AI_pcmpestrm<string asm> {
7690 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7691 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7692 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7693 []>, Sched<[WritePCmpEStrM]>;
7695 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7696 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7697 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7698 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7701 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7702 let Predicates = [HasAVX] in
7703 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7704 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7707 // Packed Compare Implicit Length Strings, Return Index
7708 multiclass pseudo_pcmpistri<string asm> {
7709 def REG : PseudoI<(outs GR32:$dst),
7710 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7711 [(set GR32:$dst, EFLAGS,
7712 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7713 def MEM : PseudoI<(outs GR32:$dst),
7714 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7715 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7716 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7719 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7720 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7721 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7724 multiclass SS42AI_pcmpistri<string asm> {
7725 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7726 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7727 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7728 []>, Sched<[WritePCmpIStrI]>;
7730 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7731 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7732 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7733 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7736 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7737 let Predicates = [HasAVX] in
7738 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7739 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7742 // Packed Compare Explicit Length Strings, Return Index
7743 multiclass pseudo_pcmpestri<string asm> {
7744 def REG : PseudoI<(outs GR32:$dst),
7745 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7746 [(set GR32:$dst, EFLAGS,
7747 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7748 def MEM : PseudoI<(outs GR32:$dst),
7749 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7750 [(set GR32:$dst, EFLAGS,
7751 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7755 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7756 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7757 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7760 multiclass SS42AI_pcmpestri<string asm> {
7761 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7762 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7763 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7764 []>, Sched<[WritePCmpEStrI]>;
7766 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7767 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7768 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7769 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7772 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7773 let Predicates = [HasAVX] in
7774 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7775 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7778 //===----------------------------------------------------------------------===//
7779 // SSE4.2 - CRC Instructions
7780 //===----------------------------------------------------------------------===//
7782 // No CRC instructions have AVX equivalents
7784 // crc intrinsic instruction
7785 // This set of instructions are only rm, the only difference is the size
7787 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7788 RegisterClass RCIn, SDPatternOperator Int> :
7789 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7790 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7791 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7794 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7795 X86MemOperand x86memop, SDPatternOperator Int> :
7796 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7797 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7798 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7799 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7801 let Constraints = "$src1 = $dst" in {
7802 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7803 int_x86_sse42_crc32_32_8>;
7804 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7805 int_x86_sse42_crc32_32_8>;
7806 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7807 int_x86_sse42_crc32_32_16>, OpSize16;
7808 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7809 int_x86_sse42_crc32_32_16>, OpSize16;
7810 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7811 int_x86_sse42_crc32_32_32>, OpSize32;
7812 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7813 int_x86_sse42_crc32_32_32>, OpSize32;
7814 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7815 int_x86_sse42_crc32_64_64>, REX_W;
7816 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7817 int_x86_sse42_crc32_64_64>, REX_W;
7818 let hasSideEffects = 0 in {
7820 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7822 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7827 //===----------------------------------------------------------------------===//
7828 // SHA-NI Instructions
7829 //===----------------------------------------------------------------------===//
7831 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7833 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7834 (ins VR128:$src1, VR128:$src2),
7835 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7837 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7838 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7840 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7841 (ins VR128:$src1, i128mem:$src2),
7842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7844 (set VR128:$dst, (IntId VR128:$src1,
7845 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7846 (set VR128:$dst, (IntId VR128:$src1,
7847 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7850 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7851 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7852 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7853 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7855 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7856 (i8 imm:$src3)))]>, TA;
7857 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7858 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7859 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7861 (int_x86_sha1rnds4 VR128:$src1,
7862 (bc_v4i32 (memopv2i64 addr:$src2)),
7863 (i8 imm:$src3)))]>, TA;
7865 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7866 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7867 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7870 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7872 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7873 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7876 // Aliases with explicit %xmm0
7877 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7878 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7879 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7880 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7882 //===----------------------------------------------------------------------===//
7883 // AES-NI Instructions
7884 //===----------------------------------------------------------------------===//
7886 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7887 Intrinsic IntId128, bit Is2Addr = 1> {
7888 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7889 (ins VR128:$src1, VR128:$src2),
7891 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7892 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7893 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7894 Sched<[WriteAESDecEnc]>;
7895 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7896 (ins VR128:$src1, i128mem:$src2),
7898 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7899 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7901 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7902 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7905 // Perform One Round of an AES Encryption/Decryption Flow
7906 let Predicates = [HasAVX, HasAES] in {
7907 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7908 int_x86_aesni_aesenc, 0>, VEX_4V;
7909 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7910 int_x86_aesni_aesenclast, 0>, VEX_4V;
7911 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7912 int_x86_aesni_aesdec, 0>, VEX_4V;
7913 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7914 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7917 let Constraints = "$src1 = $dst" in {
7918 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7919 int_x86_aesni_aesenc>;
7920 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7921 int_x86_aesni_aesenclast>;
7922 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7923 int_x86_aesni_aesdec>;
7924 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7925 int_x86_aesni_aesdeclast>;
7928 // Perform the AES InvMixColumn Transformation
7929 let Predicates = [HasAVX, HasAES] in {
7930 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7932 "vaesimc\t{$src1, $dst|$dst, $src1}",
7934 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7936 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7937 (ins i128mem:$src1),
7938 "vaesimc\t{$src1, $dst|$dst, $src1}",
7939 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7940 Sched<[WriteAESIMCLd]>, VEX;
7942 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7944 "aesimc\t{$src1, $dst|$dst, $src1}",
7946 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7947 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7948 (ins i128mem:$src1),
7949 "aesimc\t{$src1, $dst|$dst, $src1}",
7950 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7951 Sched<[WriteAESIMCLd]>;
7953 // AES Round Key Generation Assist
7954 let Predicates = [HasAVX, HasAES] in {
7955 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7956 (ins VR128:$src1, u8imm:$src2),
7957 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7959 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7960 Sched<[WriteAESKeyGen]>, VEX;
7961 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7962 (ins i128mem:$src1, u8imm:$src2),
7963 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7965 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7966 Sched<[WriteAESKeyGenLd]>, VEX;
7968 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7969 (ins VR128:$src1, u8imm:$src2),
7970 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7972 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7973 Sched<[WriteAESKeyGen]>;
7974 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7975 (ins i128mem:$src1, u8imm:$src2),
7976 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7978 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7979 Sched<[WriteAESKeyGenLd]>;
7981 //===----------------------------------------------------------------------===//
7982 // PCLMUL Instructions
7983 //===----------------------------------------------------------------------===//
7985 // AVX carry-less Multiplication instructions
7986 let isCommutable = 1 in
7987 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7988 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7989 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7991 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7992 Sched<[WriteCLMul]>;
7994 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7995 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7996 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7997 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7998 (loadv2i64 addr:$src2), imm:$src3))]>,
7999 Sched<[WriteCLMulLd, ReadAfterLd]>;
8001 // Carry-less Multiplication instructions
8002 let Constraints = "$src1 = $dst" in {
8003 let isCommutable = 1 in
8004 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8005 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
8006 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8008 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
8009 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
8011 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8012 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
8013 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8014 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8015 (memopv2i64 addr:$src2), imm:$src3))],
8016 IIC_SSE_PCLMULQDQ_RM>,
8017 Sched<[WriteCLMulLd, ReadAfterLd]>;
8018 } // Constraints = "$src1 = $dst"
8021 multiclass pclmul_alias<string asm, int immop> {
8022 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8023 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8025 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8026 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8028 def : InstAlias<!strconcat("vpclmul", asm,
8029 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8030 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8033 def : InstAlias<!strconcat("vpclmul", asm,
8034 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8035 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8038 defm : pclmul_alias<"hqhq", 0x11>;
8039 defm : pclmul_alias<"hqlq", 0x01>;
8040 defm : pclmul_alias<"lqhq", 0x10>;
8041 defm : pclmul_alias<"lqlq", 0x00>;
8043 //===----------------------------------------------------------------------===//
8044 // SSE4A Instructions
8045 //===----------------------------------------------------------------------===//
8047 let Predicates = [HasSSE4A] in {
8049 let Constraints = "$src = $dst" in {
8050 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8051 (ins VR128:$src, u8imm:$len, u8imm:$idx),
8052 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8053 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8055 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8056 (ins VR128:$src, VR128:$mask),
8057 "extrq\t{$mask, $src|$src, $mask}",
8058 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8059 VR128:$mask))]>, PD;
8061 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8062 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
8063 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8064 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8065 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8066 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8067 (ins VR128:$src, VR128:$mask),
8068 "insertq\t{$mask, $src|$src, $mask}",
8069 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8070 VR128:$mask))]>, XD;
8073 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8074 "movntss\t{$src, $dst|$dst, $src}",
8075 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8077 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8078 "movntsd\t{$src, $dst|$dst, $src}",
8079 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8082 //===----------------------------------------------------------------------===//
8084 //===----------------------------------------------------------------------===//
8086 //===----------------------------------------------------------------------===//
8087 // VBROADCAST - Load from memory and broadcast to all elements of the
8088 // destination operand
8090 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8091 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8092 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8093 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8094 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8096 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8097 X86MemOperand x86memop, ValueType VT,
8098 PatFrag ld_frag, SchedWrite Sched> :
8099 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8100 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8101 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8102 Sched<[Sched]>, VEX {
8106 // AVX2 adds register forms
8107 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8108 Intrinsic Int, SchedWrite Sched> :
8109 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8110 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8111 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8113 let ExeDomain = SSEPackedSingle in {
8114 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8115 f32mem, v4f32, loadf32, WriteLoad>;
8116 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8117 f32mem, v8f32, loadf32,
8118 WriteFShuffleLd>, VEX_L;
8120 let ExeDomain = SSEPackedDouble in
8121 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8122 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8123 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8124 int_x86_avx_vbroadcastf128_pd_256,
8125 WriteFShuffleLd>, VEX_L;
8127 let ExeDomain = SSEPackedSingle in {
8128 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8129 int_x86_avx2_vbroadcast_ss_ps,
8131 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8132 int_x86_avx2_vbroadcast_ss_ps_256,
8133 WriteFShuffle256>, VEX_L;
8135 let ExeDomain = SSEPackedDouble in
8136 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8137 int_x86_avx2_vbroadcast_sd_pd_256,
8138 WriteFShuffle256>, VEX_L;
8140 let Predicates = [HasAVX2] in
8141 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8142 int_x86_avx2_vbroadcasti128, WriteLoad>,
8145 let Predicates = [HasAVX] in
8146 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8147 (VBROADCASTF128 addr:$src)>;
8150 //===----------------------------------------------------------------------===//
8151 // VINSERTF128 - Insert packed floating-point values
8153 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8154 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8155 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8156 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8157 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8159 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8160 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
8161 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8162 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8165 let Predicates = [HasAVX] in {
8166 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8168 (VINSERTF128rr VR256:$src1, VR128:$src2,
8169 (INSERT_get_vinsert128_imm VR256:$ins))>;
8170 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8172 (VINSERTF128rr VR256:$src1, VR128:$src2,
8173 (INSERT_get_vinsert128_imm VR256:$ins))>;
8175 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8177 (VINSERTF128rm VR256:$src1, addr:$src2,
8178 (INSERT_get_vinsert128_imm VR256:$ins))>;
8179 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8181 (VINSERTF128rm VR256:$src1, addr:$src2,
8182 (INSERT_get_vinsert128_imm VR256:$ins))>;
8185 let Predicates = [HasAVX1Only] in {
8186 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8188 (VINSERTF128rr VR256:$src1, VR128:$src2,
8189 (INSERT_get_vinsert128_imm VR256:$ins))>;
8190 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8192 (VINSERTF128rr VR256:$src1, VR128:$src2,
8193 (INSERT_get_vinsert128_imm VR256:$ins))>;
8194 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8196 (VINSERTF128rr VR256:$src1, VR128:$src2,
8197 (INSERT_get_vinsert128_imm VR256:$ins))>;
8198 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8200 (VINSERTF128rr VR256:$src1, VR128:$src2,
8201 (INSERT_get_vinsert128_imm VR256:$ins))>;
8203 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8205 (VINSERTF128rm VR256:$src1, addr:$src2,
8206 (INSERT_get_vinsert128_imm VR256:$ins))>;
8207 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8208 (bc_v4i32 (loadv2i64 addr:$src2)),
8210 (VINSERTF128rm VR256:$src1, addr:$src2,
8211 (INSERT_get_vinsert128_imm VR256:$ins))>;
8212 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8213 (bc_v16i8 (loadv2i64 addr:$src2)),
8215 (VINSERTF128rm VR256:$src1, addr:$src2,
8216 (INSERT_get_vinsert128_imm VR256:$ins))>;
8217 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8218 (bc_v8i16 (loadv2i64 addr:$src2)),
8220 (VINSERTF128rm VR256:$src1, addr:$src2,
8221 (INSERT_get_vinsert128_imm VR256:$ins))>;
8224 //===----------------------------------------------------------------------===//
8225 // VEXTRACTF128 - Extract packed floating-point values
8227 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8228 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8229 (ins VR256:$src1, u8imm:$src2),
8230 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8231 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8233 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8234 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
8235 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8236 []>, Sched<[WriteStore]>, VEX, VEX_L;
8240 let Predicates = [HasAVX] in {
8241 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8242 (v4f32 (VEXTRACTF128rr
8243 (v8f32 VR256:$src1),
8244 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8245 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8246 (v2f64 (VEXTRACTF128rr
8247 (v4f64 VR256:$src1),
8248 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8250 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8251 (iPTR imm))), addr:$dst),
8252 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8253 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8254 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8255 (iPTR imm))), addr:$dst),
8256 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8257 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8260 let Predicates = [HasAVX1Only] in {
8261 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8262 (v2i64 (VEXTRACTF128rr
8263 (v4i64 VR256:$src1),
8264 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8265 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8266 (v4i32 (VEXTRACTF128rr
8267 (v8i32 VR256:$src1),
8268 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8269 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8270 (v8i16 (VEXTRACTF128rr
8271 (v16i16 VR256:$src1),
8272 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8273 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8274 (v16i8 (VEXTRACTF128rr
8275 (v32i8 VR256:$src1),
8276 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8278 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8279 (iPTR imm))), addr:$dst),
8280 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8281 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8282 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8283 (iPTR imm))), addr:$dst),
8284 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8285 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8286 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8287 (iPTR imm))), addr:$dst),
8288 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8289 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8290 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8291 (iPTR imm))), addr:$dst),
8292 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8293 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8296 //===----------------------------------------------------------------------===//
8297 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8299 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8300 Intrinsic IntLd, Intrinsic IntLd256,
8301 Intrinsic IntSt, Intrinsic IntSt256> {
8302 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8303 (ins VR128:$src1, f128mem:$src2),
8304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8305 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8307 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8308 (ins VR256:$src1, f256mem:$src2),
8309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8310 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8312 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8313 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8315 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8316 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8317 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8318 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8319 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8322 let ExeDomain = SSEPackedSingle in
8323 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8324 int_x86_avx_maskload_ps,
8325 int_x86_avx_maskload_ps_256,
8326 int_x86_avx_maskstore_ps,
8327 int_x86_avx_maskstore_ps_256>;
8328 let ExeDomain = SSEPackedDouble in
8329 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8330 int_x86_avx_maskload_pd,
8331 int_x86_avx_maskload_pd_256,
8332 int_x86_avx_maskstore_pd,
8333 int_x86_avx_maskstore_pd_256>;
8335 //===----------------------------------------------------------------------===//
8336 // VPERMIL - Permute Single and Double Floating-Point Values
8338 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8339 RegisterClass RC, X86MemOperand x86memop_f,
8340 X86MemOperand x86memop_i, PatFrag i_frag,
8341 Intrinsic IntVar, ValueType vt> {
8342 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8343 (ins RC:$src1, RC:$src2),
8344 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8345 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8346 Sched<[WriteFShuffle]>;
8347 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8348 (ins RC:$src1, x86memop_i:$src2),
8349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8350 [(set RC:$dst, (IntVar RC:$src1,
8351 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8352 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8354 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8355 (ins RC:$src1, u8imm:$src2),
8356 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8357 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8358 Sched<[WriteFShuffle]>;
8359 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8360 (ins x86memop_f:$src1, u8imm:$src2),
8361 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8363 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8364 Sched<[WriteFShuffleLd]>;
8367 let ExeDomain = SSEPackedSingle in {
8368 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8369 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8370 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8371 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8373 let ExeDomain = SSEPackedDouble in {
8374 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8375 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8376 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8377 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8380 let Predicates = [HasAVX] in {
8381 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8382 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8383 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8384 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8385 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8386 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8387 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8388 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8390 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8391 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8392 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8393 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8394 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8396 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8397 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8398 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8400 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8401 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8402 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8403 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8404 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8405 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8406 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8407 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8409 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8410 (VPERMILPDri VR128:$src1, imm:$imm)>;
8411 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8412 (VPERMILPDmi addr:$src1, imm:$imm)>;
8415 //===----------------------------------------------------------------------===//
8416 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8418 let ExeDomain = SSEPackedSingle in {
8419 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8420 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8421 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8422 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8423 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8424 Sched<[WriteFShuffle]>;
8425 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8426 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8427 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8428 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8429 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8430 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8433 let Predicates = [HasAVX] in {
8434 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8435 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8436 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8437 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8438 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8441 let Predicates = [HasAVX1Only] in {
8442 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8443 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8444 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8445 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8446 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8447 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8448 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8449 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8451 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8452 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8453 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8454 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8455 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8456 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8457 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8458 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8459 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8460 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8461 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8462 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8465 //===----------------------------------------------------------------------===//
8466 // VZERO - Zero YMM registers
8468 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8469 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8470 // Zero All YMM registers
8471 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8472 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8474 // Zero Upper bits of YMM registers
8475 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8476 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8479 //===----------------------------------------------------------------------===//
8480 // Half precision conversion instructions
8481 //===----------------------------------------------------------------------===//
8482 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8483 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8484 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8485 [(set RC:$dst, (Int VR128:$src))]>,
8486 T8PD, VEX, Sched<[WriteCvtF2F]>;
8487 let hasSideEffects = 0, mayLoad = 1 in
8488 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8489 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8490 Sched<[WriteCvtF2FLd]>;
8493 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8494 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8495 (ins RC:$src1, i32u8imm:$src2),
8496 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8497 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8498 TAPD, VEX, Sched<[WriteCvtF2F]>;
8499 let hasSideEffects = 0, mayStore = 1,
8500 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8501 def mr : Ii8<0x1D, MRMDestMem, (outs),
8502 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8503 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8507 let Predicates = [HasF16C] in {
8508 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8509 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8510 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8511 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8513 // Pattern match vcvtph2ps of a scalar i64 load.
8514 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8515 (VCVTPH2PSrm addr:$src)>;
8516 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8517 (VCVTPH2PSrm addr:$src)>;
8520 // Patterns for matching conversions from float to half-float and vice versa.
8521 let Predicates = [HasF16C] in {
8522 def : Pat<(fp_to_f16 FR32:$src),
8523 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8524 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8526 def : Pat<(f16_to_fp GR16:$src),
8527 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8528 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8530 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8531 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8532 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8535 //===----------------------------------------------------------------------===//
8536 // AVX2 Instructions
8537 //===----------------------------------------------------------------------===//
8539 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8540 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8541 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8542 X86MemOperand x86memop> {
8543 let isCommutable = 1 in
8544 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8545 (ins RC:$src1, RC:$src2, u8imm:$src3),
8546 !strconcat(OpcodeStr,
8547 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8548 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8549 Sched<[WriteBlend]>, VEX_4V;
8550 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8551 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8552 !strconcat(OpcodeStr,
8553 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8556 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8557 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8560 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8561 VR128, loadv2i64, i128mem>;
8562 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8563 VR256, loadv4i64, i256mem>, VEX_L;
8565 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8567 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8568 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8570 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8572 //===----------------------------------------------------------------------===//
8573 // VPBROADCAST - Load from memory and broadcast to all elements of the
8574 // destination operand
8576 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8577 X86MemOperand x86memop, PatFrag ld_frag,
8578 Intrinsic Int128, Intrinsic Int256> {
8579 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8581 [(set VR128:$dst, (Int128 VR128:$src))]>,
8582 Sched<[WriteShuffle]>, VEX;
8583 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8586 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8587 Sched<[WriteLoad]>, VEX;
8588 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8589 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8590 [(set VR256:$dst, (Int256 VR128:$src))]>,
8591 Sched<[WriteShuffle256]>, VEX, VEX_L;
8592 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8593 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8595 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8596 Sched<[WriteLoad]>, VEX, VEX_L;
8599 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8600 int_x86_avx2_pbroadcastb_128,
8601 int_x86_avx2_pbroadcastb_256>;
8602 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8603 int_x86_avx2_pbroadcastw_128,
8604 int_x86_avx2_pbroadcastw_256>;
8605 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8606 int_x86_avx2_pbroadcastd_128,
8607 int_x86_avx2_pbroadcastd_256>;
8608 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8609 int_x86_avx2_pbroadcastq_128,
8610 int_x86_avx2_pbroadcastq_256>;
8612 let Predicates = [HasAVX2] in {
8613 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8614 (VPBROADCASTBrm addr:$src)>;
8615 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8616 (VPBROADCASTBYrm addr:$src)>;
8617 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8618 (VPBROADCASTWrm addr:$src)>;
8619 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8620 (VPBROADCASTWYrm addr:$src)>;
8621 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8622 (VPBROADCASTDrm addr:$src)>;
8623 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8624 (VPBROADCASTDYrm addr:$src)>;
8625 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8626 (VPBROADCASTQrm addr:$src)>;
8627 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8628 (VPBROADCASTQYrm addr:$src)>;
8630 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8631 (VPBROADCASTBrr VR128:$src)>;
8632 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8633 (VPBROADCASTBYrr VR128:$src)>;
8634 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8635 (VPBROADCASTWrr VR128:$src)>;
8636 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8637 (VPBROADCASTWYrr VR128:$src)>;
8638 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8639 (VPBROADCASTDrr VR128:$src)>;
8640 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8641 (VPBROADCASTDYrr VR128:$src)>;
8642 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8643 (VPBROADCASTQrr VR128:$src)>;
8644 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8645 (VPBROADCASTQYrr VR128:$src)>;
8646 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8647 (VBROADCASTSSrr VR128:$src)>;
8648 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8649 (VBROADCASTSSYrr VR128:$src)>;
8650 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8651 (VPBROADCASTQrr VR128:$src)>;
8652 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8653 (VBROADCASTSDYrr VR128:$src)>;
8655 // Provide aliases for broadcast from the same regitser class that
8656 // automatically does the extract.
8657 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8658 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8660 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8661 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8663 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8664 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8666 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8667 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8669 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8670 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8672 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8673 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8676 // Provide fallback in case the load node that is used in the patterns above
8677 // is used by additional users, which prevents the pattern selection.
8678 let AddedComplexity = 20 in {
8679 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8680 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8681 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8682 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8683 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8684 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8686 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8687 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8688 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8689 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8690 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8691 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8693 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8694 (VPBROADCASTBrr (COPY_TO_REGCLASS
8695 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8697 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8698 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8699 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8702 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8703 (VPBROADCASTWrr (COPY_TO_REGCLASS
8704 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8706 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8707 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8708 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8711 // The patterns for VPBROADCASTD are not needed because they would match
8712 // the exact same thing as VBROADCASTSS patterns.
8714 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8715 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8716 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8720 // AVX1 broadcast patterns
8721 let Predicates = [HasAVX1Only] in {
8722 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8723 (VBROADCASTSSYrm addr:$src)>;
8724 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8725 (VBROADCASTSDYrm addr:$src)>;
8726 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8727 (VBROADCASTSSrm addr:$src)>;
8730 let Predicates = [HasAVX] in {
8731 // Provide fallback in case the load node that is used in the patterns above
8732 // is used by additional users, which prevents the pattern selection.
8733 let AddedComplexity = 20 in {
8734 // 128bit broadcasts:
8735 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8736 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8737 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8738 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8739 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8740 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8741 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8742 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8743 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8744 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8746 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8747 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8748 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8749 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8750 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8751 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8752 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8753 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8754 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8755 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8758 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8759 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8762 //===----------------------------------------------------------------------===//
8763 // VPERM - Permute instructions
8766 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8767 ValueType OpVT, X86FoldableSchedWrite Sched> {
8768 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8769 (ins VR256:$src1, VR256:$src2),
8770 !strconcat(OpcodeStr,
8771 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8773 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8774 Sched<[Sched]>, VEX_4V, VEX_L;
8775 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8776 (ins VR256:$src1, i256mem:$src2),
8777 !strconcat(OpcodeStr,
8778 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8780 (OpVT (X86VPermv VR256:$src1,
8781 (bitconvert (mem_frag addr:$src2)))))]>,
8782 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8785 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8786 let ExeDomain = SSEPackedSingle in
8787 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8789 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8790 ValueType OpVT, X86FoldableSchedWrite Sched> {
8791 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8792 (ins VR256:$src1, u8imm:$src2),
8793 !strconcat(OpcodeStr,
8794 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8796 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8797 Sched<[Sched]>, VEX, VEX_L;
8798 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8799 (ins i256mem:$src1, u8imm:$src2),
8800 !strconcat(OpcodeStr,
8801 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8803 (OpVT (X86VPermi (mem_frag addr:$src1),
8804 (i8 imm:$src2))))]>,
8805 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8808 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8809 WriteShuffle256>, VEX_W;
8810 let ExeDomain = SSEPackedDouble in
8811 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8812 WriteFShuffle256>, VEX_W;
8814 //===----------------------------------------------------------------------===//
8815 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8817 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8818 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8819 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8820 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8821 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8823 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8824 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8825 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8826 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8828 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8830 let Predicates = [HasAVX2] in {
8831 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8832 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8833 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8834 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8835 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8836 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8838 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8840 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8841 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8842 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8843 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8844 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8846 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8850 //===----------------------------------------------------------------------===//
8851 // VINSERTI128 - Insert packed integer values
8853 let hasSideEffects = 0 in {
8854 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8855 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8856 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8857 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8859 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8860 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8861 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8862 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8865 let Predicates = [HasAVX2] in {
8866 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8868 (VINSERTI128rr VR256:$src1, VR128:$src2,
8869 (INSERT_get_vinsert128_imm VR256:$ins))>;
8870 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8872 (VINSERTI128rr VR256:$src1, VR128:$src2,
8873 (INSERT_get_vinsert128_imm VR256:$ins))>;
8874 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8876 (VINSERTI128rr VR256:$src1, VR128:$src2,
8877 (INSERT_get_vinsert128_imm VR256:$ins))>;
8878 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8880 (VINSERTI128rr VR256:$src1, VR128:$src2,
8881 (INSERT_get_vinsert128_imm VR256:$ins))>;
8883 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8885 (VINSERTI128rm VR256:$src1, addr:$src2,
8886 (INSERT_get_vinsert128_imm VR256:$ins))>;
8887 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8888 (bc_v4i32 (loadv2i64 addr:$src2)),
8890 (VINSERTI128rm VR256:$src1, addr:$src2,
8891 (INSERT_get_vinsert128_imm VR256:$ins))>;
8892 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8893 (bc_v16i8 (loadv2i64 addr:$src2)),
8895 (VINSERTI128rm VR256:$src1, addr:$src2,
8896 (INSERT_get_vinsert128_imm VR256:$ins))>;
8897 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8898 (bc_v8i16 (loadv2i64 addr:$src2)),
8900 (VINSERTI128rm VR256:$src1, addr:$src2,
8901 (INSERT_get_vinsert128_imm VR256:$ins))>;
8904 //===----------------------------------------------------------------------===//
8905 // VEXTRACTI128 - Extract packed integer values
8907 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8908 (ins VR256:$src1, u8imm:$src2),
8909 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8911 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8912 Sched<[WriteShuffle256]>, VEX, VEX_L;
8913 let hasSideEffects = 0, mayStore = 1 in
8914 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8915 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8916 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8917 Sched<[WriteStore]>, VEX, VEX_L;
8919 let Predicates = [HasAVX2] in {
8920 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8921 (v2i64 (VEXTRACTI128rr
8922 (v4i64 VR256:$src1),
8923 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8924 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8925 (v4i32 (VEXTRACTI128rr
8926 (v8i32 VR256:$src1),
8927 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8928 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8929 (v8i16 (VEXTRACTI128rr
8930 (v16i16 VR256:$src1),
8931 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8932 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8933 (v16i8 (VEXTRACTI128rr
8934 (v32i8 VR256:$src1),
8935 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8937 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8938 (iPTR imm))), addr:$dst),
8939 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8940 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8941 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8942 (iPTR imm))), addr:$dst),
8943 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8944 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8945 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8946 (iPTR imm))), addr:$dst),
8947 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8948 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8949 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8950 (iPTR imm))), addr:$dst),
8951 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8952 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8955 //===----------------------------------------------------------------------===//
8956 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8958 multiclass avx2_pmovmask<string OpcodeStr,
8959 Intrinsic IntLd128, Intrinsic IntLd256,
8960 Intrinsic IntSt128, Intrinsic IntSt256> {
8961 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8962 (ins VR128:$src1, i128mem:$src2),
8963 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8964 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8965 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8966 (ins VR256:$src1, i256mem:$src2),
8967 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8968 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8970 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8971 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8973 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8974 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8975 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8976 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8977 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8980 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8981 int_x86_avx2_maskload_d,
8982 int_x86_avx2_maskload_d_256,
8983 int_x86_avx2_maskstore_d,
8984 int_x86_avx2_maskstore_d_256>;
8985 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8986 int_x86_avx2_maskload_q,
8987 int_x86_avx2_maskload_q_256,
8988 int_x86_avx2_maskstore_q,
8989 int_x86_avx2_maskstore_q_256>, VEX_W;
8991 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8992 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8994 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8995 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8997 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8998 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
9000 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
9001 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
9003 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
9004 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
9006 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
9007 (bc_v8f32 (v8i32 immAllZerosV)))),
9008 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
9010 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
9011 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
9014 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
9015 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
9017 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
9018 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
9020 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
9021 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
9024 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9025 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9027 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
9028 (bc_v4f32 (v4i32 immAllZerosV)))),
9029 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9031 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
9032 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
9035 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9036 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9038 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
9039 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9041 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
9042 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
9045 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
9046 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9048 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
9049 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9051 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9052 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9054 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9055 (v4f64 immAllZerosV))),
9056 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9058 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
9059 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
9062 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9063 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9065 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9066 (bc_v4i64 (v8i32 immAllZerosV)))),
9067 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9069 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
9070 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
9073 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
9074 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
9076 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
9077 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
9079 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9080 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9082 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9083 (v2f64 immAllZerosV))),
9084 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9086 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
9087 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
9090 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9091 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9093 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9094 (bc_v2i64 (v4i32 immAllZerosV)))),
9095 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9097 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
9098 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
9101 //===----------------------------------------------------------------------===//
9102 // Variable Bit Shifts
9104 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9105 ValueType vt128, ValueType vt256> {
9106 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9107 (ins VR128:$src1, VR128:$src2),
9108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9110 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9111 VEX_4V, Sched<[WriteVarVecShift]>;
9112 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9113 (ins VR128:$src1, i128mem:$src2),
9114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9116 (vt128 (OpNode VR128:$src1,
9117 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9118 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9119 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9120 (ins VR256:$src1, VR256:$src2),
9121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9123 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9124 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9125 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9126 (ins VR256:$src1, i256mem:$src2),
9127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9129 (vt256 (OpNode VR256:$src1,
9130 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9131 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9134 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9135 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9136 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9137 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9138 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9140 //===----------------------------------------------------------------------===//
9141 // VGATHER - GATHER Operations
9142 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9143 X86MemOperand memop128, X86MemOperand memop256> {
9144 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9145 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9146 !strconcat(OpcodeStr,
9147 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9149 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9150 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9151 !strconcat(OpcodeStr,
9152 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9153 []>, VEX_4VOp3, VEX_L;
9156 let mayLoad = 1, Constraints
9157 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9159 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9160 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9161 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9162 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9164 let ExeDomain = SSEPackedDouble in {
9165 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9166 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9169 let ExeDomain = SSEPackedSingle in {
9170 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9171 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;