1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 // Similar to AVX512_maskable_3rc but in this case the input VT for the tied
280 // operand differs from the output VT. This requires a bitconvert on
281 // the preserved vector going into the vselect.
282 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
283 X86VectorVTInfo InVT,
284 dag Outs, dag NonTiedIns, string OpcodeStr,
285 string AttSrcAsm, string IntelSrcAsm,
287 AVX512_maskable_common<O, F, OutVT, Outs,
288 !con((ins InVT.RC:$src1), NonTiedIns),
289 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
290 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
291 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
292 (vselect InVT.KRCWM:$mask, RHS,
293 (bitconvert InVT.RC:$src1))>;
295 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
296 dag Outs, dag NonTiedIns, string OpcodeStr,
297 string AttSrcAsm, string IntelSrcAsm,
299 AVX512_maskable_common<O, F, _, Outs,
300 !con((ins _.RC:$src1), NonTiedIns),
301 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
302 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
303 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
304 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
306 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
309 string AttSrcAsm, string IntelSrcAsm,
311 AVX512_maskable_custom<O, F, Outs, Ins,
312 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
313 !con((ins _.KRCWM:$mask), Ins),
314 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
318 // Instruction with mask that puts result in mask register,
319 // like "compare" and "vptest"
320 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
322 dag Ins, dag MaskingIns,
324 string AttSrcAsm, string IntelSrcAsm,
326 list<dag> MaskingPattern,
328 InstrItinClass itin = NoItinerary> {
329 def NAME: AVX512<O, F, Outs, Ins,
330 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
331 "$dst "#Round#", "#IntelSrcAsm#"}",
334 def NAME#k: AVX512<O, F, Outs, MaskingIns,
335 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
336 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
337 MaskingPattern, itin>, EVEX_K;
340 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
342 dag Ins, dag MaskingIns,
344 string AttSrcAsm, string IntelSrcAsm,
345 dag RHS, dag MaskingRHS,
347 InstrItinClass itin = NoItinerary> :
348 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
349 AttSrcAsm, IntelSrcAsm,
350 [(set _.KRC:$dst, RHS)],
351 [(set _.KRC:$dst, MaskingRHS)],
354 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
355 dag Outs, dag Ins, string OpcodeStr,
356 string AttSrcAsm, string IntelSrcAsm,
357 dag RHS, string Round = "",
358 InstrItinClass itin = NoItinerary> :
359 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
360 !con((ins _.KRCWM:$mask), Ins),
361 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
362 (and _.KRCWM:$mask, RHS),
365 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
366 dag Outs, dag Ins, string OpcodeStr,
367 string AttSrcAsm, string IntelSrcAsm> :
368 AVX512_maskable_custom_cmp<O, F, Outs,
369 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
370 AttSrcAsm, IntelSrcAsm,
371 [],[],"", NoItinerary>;
373 // Bitcasts between 512-bit vector types. Return the original type since
374 // no instruction is needed for the conversion
375 let Predicates = [HasAVX512] in {
376 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
378 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
379 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
380 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
387 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
395 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
396 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
397 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
403 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
408 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
409 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
410 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
411 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
412 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
413 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
414 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
415 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
416 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
417 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
418 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
419 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
420 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
421 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
422 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
423 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
424 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
425 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
426 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
427 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
428 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
429 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
430 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
431 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
432 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
433 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
434 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
435 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
436 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
437 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
439 // Bitcasts between 256-bit vector types. Return the original type since
440 // no instruction is needed for the conversion
441 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
442 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
443 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
444 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
445 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
446 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
447 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
448 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
449 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
450 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
451 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
452 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
453 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
454 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
455 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
456 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
457 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
458 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
459 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
460 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
461 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
462 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
463 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
464 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
465 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
466 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
467 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
468 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
469 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
470 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
474 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
477 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
478 isPseudo = 1, Predicates = [HasAVX512] in {
479 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
480 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
483 let Predicates = [HasAVX512] in {
484 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
485 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
486 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
489 //===----------------------------------------------------------------------===//
490 // AVX-512 - VECTOR INSERT
492 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
493 PatFrag vinsert_insert> {
494 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
495 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
496 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
497 "vinsert" # From.EltTypeName # "x" # From.NumElts,
498 "$src3, $src2, $src1", "$src1, $src2, $src3",
499 (vinsert_insert:$src3 (To.VT To.RC:$src1),
500 (From.VT From.RC:$src2),
501 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
504 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
505 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
506 "vinsert" # From.EltTypeName # "x" # From.NumElts,
507 "$src3, $src2, $src1", "$src1, $src2, $src3",
508 (vinsert_insert:$src3 (To.VT To.RC:$src1),
509 (From.VT (bitconvert (From.LdFrag addr:$src2))),
510 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
511 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
515 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
516 X86VectorVTInfo To, PatFrag vinsert_insert,
517 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
518 let Predicates = p in {
519 def : Pat<(vinsert_insert:$ins
520 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
521 (To.VT (!cast<Instruction>(InstrStr#"rr")
522 To.RC:$src1, From.RC:$src2,
523 (INSERT_get_vinsert_imm To.RC:$ins)))>;
525 def : Pat<(vinsert_insert:$ins
527 (From.VT (bitconvert (From.LdFrag addr:$src2))),
529 (To.VT (!cast<Instruction>(InstrStr#"rm")
530 To.RC:$src1, addr:$src2,
531 (INSERT_get_vinsert_imm To.RC:$ins)))>;
535 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
536 ValueType EltVT64, int Opcode256> {
538 let Predicates = [HasVLX] in
539 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 4, EltVT32, VR128X>,
541 X86VectorVTInfo< 8, EltVT32, VR256X>,
542 vinsert128_insert>, EVEX_V256;
544 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
545 X86VectorVTInfo< 4, EltVT32, VR128X>,
546 X86VectorVTInfo<16, EltVT32, VR512>,
547 vinsert128_insert>, EVEX_V512;
549 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
550 X86VectorVTInfo< 4, EltVT64, VR256X>,
551 X86VectorVTInfo< 8, EltVT64, VR512>,
552 vinsert256_insert>, VEX_W, EVEX_V512;
554 let Predicates = [HasVLX, HasDQI] in
555 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
556 X86VectorVTInfo< 2, EltVT64, VR128X>,
557 X86VectorVTInfo< 4, EltVT64, VR256X>,
558 vinsert128_insert>, VEX_W, EVEX_V256;
560 let Predicates = [HasDQI] in {
561 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
562 X86VectorVTInfo< 2, EltVT64, VR128X>,
563 X86VectorVTInfo< 8, EltVT64, VR512>,
564 vinsert128_insert>, VEX_W, EVEX_V512;
566 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
567 X86VectorVTInfo< 8, EltVT32, VR256X>,
568 X86VectorVTInfo<16, EltVT32, VR512>,
569 vinsert256_insert>, EVEX_V512;
573 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
574 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
576 // Codegen pattern with the alternative types,
577 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
578 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
583 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
588 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
593 // Codegen pattern with the alternative types insert VEC128 into VEC256
594 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
595 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
596 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
597 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
598 // Codegen pattern with the alternative types insert VEC128 into VEC512
599 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
600 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
601 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
602 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
603 // Codegen pattern with the alternative types insert VEC256 into VEC512
604 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
605 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
606 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
607 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
609 // vinsertps - insert f32 to XMM
610 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
611 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
612 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
613 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
615 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
616 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
617 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
618 [(set VR128X:$dst, (X86insertps VR128X:$src1,
619 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
620 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
622 //===----------------------------------------------------------------------===//
623 // AVX-512 VECTOR EXTRACT
626 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
627 X86VectorVTInfo To> {
628 // A subvector extract from the first vector position is
629 // a subregister copy that needs no instruction.
630 def NAME # To.NumElts:
631 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
632 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
635 multiclass vextract_for_size<int Opcode,
636 X86VectorVTInfo From, X86VectorVTInfo To,
637 PatFrag vextract_extract> :
638 vextract_for_size_first_position_lowering<From, To> {
640 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
641 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
642 // vextract_extract), we interesting only in patterns without mask,
643 // intrinsics pattern match generated bellow.
644 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
645 (ins From.RC:$src1, i32u8imm:$idx),
646 "vextract" # To.EltTypeName # "x" # To.NumElts,
647 "$idx, $src1", "$src1, $idx",
648 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
650 AVX512AIi8Base, EVEX;
651 let mayStore = 1 in {
652 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
653 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
654 "vextract" # To.EltTypeName # "x" # To.NumElts #
655 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
658 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
659 (ins To.MemOp:$dst, To.KRCWM:$mask,
660 From.RC:$src1, i32u8imm:$src2),
661 "vextract" # To.EltTypeName # "x" # To.NumElts #
662 "\t{$src2, $src1, $dst {${mask}}|"
663 "$dst {${mask}}, $src1, $src2}",
668 // Intrinsic call with masking.
669 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
670 "x" # To.NumElts # "_" # From.Size)
671 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
672 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
673 From.ZSuffix # "rrk")
675 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
676 From.RC:$src1, imm:$idx)>;
678 // Intrinsic call with zero-masking.
679 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
680 "x" # To.NumElts # "_" # From.Size)
681 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
682 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
683 From.ZSuffix # "rrkz")
684 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
685 From.RC:$src1, imm:$idx)>;
687 // Intrinsic call without masking.
688 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
689 "x" # To.NumElts # "_" # From.Size)
690 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
691 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
693 From.RC:$src1, imm:$idx)>;
696 // Codegen pattern for the alternative types
697 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
698 X86VectorVTInfo To, PatFrag vextract_extract,
699 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
700 vextract_for_size_first_position_lowering<From, To> {
702 let Predicates = p in
703 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
704 (To.VT (!cast<Instruction>(InstrStr#"rr")
706 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
709 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
710 ValueType EltVT64, int Opcode256> {
711 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
712 X86VectorVTInfo<16, EltVT32, VR512>,
713 X86VectorVTInfo< 4, EltVT32, VR128X>,
714 vextract128_extract>,
715 EVEX_V512, EVEX_CD8<32, CD8VT4>;
716 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
717 X86VectorVTInfo< 8, EltVT64, VR512>,
718 X86VectorVTInfo< 4, EltVT64, VR256X>,
719 vextract256_extract>,
720 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
721 let Predicates = [HasVLX] in
722 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
723 X86VectorVTInfo< 8, EltVT32, VR256X>,
724 X86VectorVTInfo< 4, EltVT32, VR128X>,
725 vextract128_extract>,
726 EVEX_V256, EVEX_CD8<32, CD8VT4>;
727 let Predicates = [HasVLX, HasDQI] in
728 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
729 X86VectorVTInfo< 4, EltVT64, VR256X>,
730 X86VectorVTInfo< 2, EltVT64, VR128X>,
731 vextract128_extract>,
732 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
733 let Predicates = [HasDQI] in {
734 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
735 X86VectorVTInfo< 8, EltVT64, VR512>,
736 X86VectorVTInfo< 2, EltVT64, VR128X>,
737 vextract128_extract>,
738 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
739 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
740 X86VectorVTInfo<16, EltVT32, VR512>,
741 X86VectorVTInfo< 8, EltVT32, VR256X>,
742 vextract256_extract>,
743 EVEX_V512, EVEX_CD8<32, CD8VT8>;
747 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
748 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
750 // extract_subvector codegen patterns with the alternative types.
751 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
752 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
757 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
762 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
763 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
764 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
765 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
767 // Codegen pattern with the alternative types extract VEC128 from VEC512
768 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
769 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
770 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
771 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
772 // Codegen pattern with the alternative types extract VEC256 from VEC512
773 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
774 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
775 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
776 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
778 // A 128-bit subvector insert to the first 512-bit vector position
779 // is a subregister copy that needs no instruction.
780 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
781 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
782 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
784 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
785 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
786 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
788 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
789 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
790 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
792 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
793 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
794 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
797 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
798 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
799 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
800 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
801 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
802 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
803 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
804 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
805 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
806 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
807 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
808 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
810 // vextractps - extract 32 bits from XMM
811 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
812 (ins VR128X:$src1, u8imm:$src2),
813 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
817 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
818 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
819 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
820 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
821 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
823 //===---------------------------------------------------------------------===//
827 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
830 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
831 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
832 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
836 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
837 (DestInfo.VT (X86VBroadcast
838 (SrcInfo.ScalarLdFrag addr:$src)))>,
839 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
842 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
843 AVX512VLVectorVTInfo _> {
844 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
847 let Predicates = [HasVLX] in {
848 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
853 let ExeDomain = SSEPackedSingle in {
854 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
856 let Predicates = [HasVLX] in {
857 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
858 v4f32x_info, v4f32x_info>, EVEX_V128;
862 let ExeDomain = SSEPackedDouble in {
863 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
864 avx512vl_f64_info>, VEX_W;
867 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
868 // Later, we can canonize broadcast instructions before ISel phase and
869 // eliminate additional patterns on ISel.
870 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
871 // representations of source
872 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
873 X86VectorVTInfo _, RegisterClass SrcRC_v,
874 RegisterClass SrcRC_s> {
875 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
876 (!cast<Instruction>(InstName##"r")
877 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
879 let AddedComplexity = 30 in {
880 def : Pat<(_.VT (vselect _.KRCWM:$mask,
881 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
882 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
883 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
885 def : Pat<(_.VT(vselect _.KRCWM:$mask,
886 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
887 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
888 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
892 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
894 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
897 let Predicates = [HasVLX] in {
898 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
899 v8f32x_info, VR128X, FR32X>;
900 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
901 v4f32x_info, VR128X, FR32X>;
902 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
903 v4f64x_info, VR128X, FR64X>;
906 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
907 (VBROADCASTSSZm addr:$src)>;
908 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
909 (VBROADCASTSDZm addr:$src)>;
911 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
912 (VBROADCASTSSZm addr:$src)>;
913 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
914 (VBROADCASTSDZm addr:$src)>;
916 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
917 RegisterClass SrcRC> {
918 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
919 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
920 "$src", "$src", []>, T8PD, EVEX;
923 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
924 RegisterClass SrcRC, Predicate prd> {
925 let Predicates = [prd] in
926 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
927 let Predicates = [prd, HasVLX] in {
928 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
929 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
933 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
935 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
937 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
939 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
942 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
943 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
945 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
946 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
948 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
949 (VPBROADCASTDrZr GR32:$src)>;
950 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
951 (VPBROADCASTQrZr GR64:$src)>;
953 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
954 (VPBROADCASTDrZr GR32:$src)>;
955 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
956 (VPBROADCASTQrZr GR64:$src)>;
958 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
959 (v16i32 immAllZerosV), (i16 GR16:$mask))),
960 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
961 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
962 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
963 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
965 // Provide aliases for broadcast from the same register class that
966 // automatically does the extract.
967 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
968 X86VectorVTInfo SrcInfo> {
969 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
970 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
971 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
974 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
975 AVX512VLVectorVTInfo _, Predicate prd> {
976 let Predicates = [prd] in {
977 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
978 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
980 // Defined separately to avoid redefinition.
981 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
983 let Predicates = [prd, HasVLX] in {
984 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
985 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
987 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
992 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
993 avx512vl_i8_info, HasBWI>;
994 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
995 avx512vl_i16_info, HasBWI>;
996 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
997 avx512vl_i32_info, HasAVX512>;
998 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
999 avx512vl_i64_info, HasAVX512>, VEX_W;
1001 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
1002 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
1003 let mayLoad = 1 in {
1004 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
1005 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1007 (_Dst.VT (X86SubVBroadcast
1008 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
1009 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1011 !strconcat(OpcodeStr,
1012 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1014 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1016 !strconcat(OpcodeStr,
1017 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1022 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1023 v16i32_info, v4i32x_info>,
1024 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1025 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1026 v16f32_info, v4f32x_info>,
1027 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1028 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1029 v8i64_info, v4i64x_info>, VEX_W,
1030 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1031 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1032 v8f64_info, v4f64x_info>, VEX_W,
1033 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1035 let Predicates = [HasVLX] in {
1036 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1037 v8i32x_info, v4i32x_info>,
1038 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1039 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1040 v8f32x_info, v4f32x_info>,
1041 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1043 let Predicates = [HasVLX, HasDQI] in {
1044 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1045 v4i64x_info, v2i64x_info>, VEX_W,
1046 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1047 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1048 v4f64x_info, v2f64x_info>, VEX_W,
1049 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1051 let Predicates = [HasDQI] in {
1052 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1053 v8i64_info, v2i64x_info>, VEX_W,
1054 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1055 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1056 v16i32_info, v8i32x_info>,
1057 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1058 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1059 v8f64_info, v2f64x_info>, VEX_W,
1060 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1061 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1062 v16f32_info, v8f32x_info>,
1063 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1066 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1067 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1068 SDNode OpNode = X86SubVBroadcast> {
1070 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1071 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1072 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1075 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1076 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1078 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1079 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1082 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1083 AVX512VLVectorVTInfo _> {
1084 let Predicates = [HasDQI] in
1085 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1087 let Predicates = [HasDQI, HasVLX] in
1088 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1092 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1093 AVX512VLVectorVTInfo _> :
1094 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1096 let Predicates = [HasDQI, HasVLX] in
1097 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1098 X86SubV32x2Broadcast>, EVEX_V128;
1101 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1103 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1106 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1107 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1108 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1109 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1111 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1112 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1113 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1114 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1116 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1117 (VBROADCASTSSZr VR128X:$src)>;
1118 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1119 (VBROADCASTSDZr VR128X:$src)>;
1121 // Provide fallback in case the load node that is used in the patterns above
1122 // is used by additional users, which prevents the pattern selection.
1123 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1124 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1125 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1126 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1129 //===----------------------------------------------------------------------===//
1130 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1132 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1133 X86VectorVTInfo _, RegisterClass KRC> {
1134 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1135 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1136 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1139 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1140 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1141 let Predicates = [HasCDI] in
1142 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1143 let Predicates = [HasCDI, HasVLX] in {
1144 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1145 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1149 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1150 avx512vl_i32_info, VK16>;
1151 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1152 avx512vl_i64_info, VK8>, VEX_W;
1154 //===----------------------------------------------------------------------===//
1155 // -- VPERMI2 - 3 source operands form --
1156 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr,
1157 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1158 let Constraints = "$src1 = $dst" in {
1159 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1160 (ins _.RC:$src2, _.RC:$src3),
1161 OpcodeStr, "$src3, $src2", "$src2, $src3",
1162 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1166 defm rm: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1167 (ins _.RC:$src2, _.MemOp:$src3),
1168 OpcodeStr, "$src3, $src2", "$src2, $src3",
1169 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2,
1170 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1171 EVEX_4V, AVX5128IBase;
1174 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1175 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1176 let mayLoad = 1, Constraints = "$src1 = $dst" in
1177 defm rmb: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1178 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1179 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1180 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1181 (_.VT (X86VPermi2X IdxVT.RC:$src1,
1182 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1183 AVX5128IBase, EVEX_4V, EVEX_B;
1186 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1187 AVX512VLVectorVTInfo VTInfo,
1188 AVX512VLVectorVTInfo ShuffleMask> {
1189 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1190 ShuffleMask.info512>,
1191 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info512,
1192 ShuffleMask.info512>, EVEX_V512;
1193 let Predicates = [HasVLX] in {
1194 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1195 ShuffleMask.info128>,
1196 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info128,
1197 ShuffleMask.info128>, EVEX_V128;
1198 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1199 ShuffleMask.info256>,
1200 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info256,
1201 ShuffleMask.info256>, EVEX_V256;
1205 multiclass avx512_perm_i_sizes_w<bits<8> opc, string OpcodeStr,
1206 AVX512VLVectorVTInfo VTInfo,
1207 AVX512VLVectorVTInfo Idx> {
1208 let Predicates = [HasBWI] in
1209 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1210 Idx.info512>, EVEX_V512;
1211 let Predicates = [HasBWI, HasVLX] in {
1212 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1213 Idx.info128>, EVEX_V128;
1214 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1215 Idx.info256>, EVEX_V256;
1219 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d",
1220 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1221 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q",
1222 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1223 defm VPERMI2W : avx512_perm_i_sizes_w<0x75, "vpermi2w",
1224 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1225 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps",
1226 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1227 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd",
1228 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1231 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1232 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1233 let Constraints = "$src1 = $dst" in {
1234 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1235 (ins IdxVT.RC:$src2, _.RC:$src3),
1236 OpcodeStr, "$src3, $src2", "$src2, $src3",
1237 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3))>, EVEX_4V,
1241 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1242 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1243 OpcodeStr, "$src3, $src2", "$src2, $src3",
1244 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1245 (bitconvert (_.LdFrag addr:$src3))))>,
1246 EVEX_4V, AVX5128IBase;
1249 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1250 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1251 let mayLoad = 1, Constraints = "$src1 = $dst" in
1252 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1253 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1254 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1255 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1256 (_.VT (X86VPermt2 _.RC:$src1,
1257 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1258 AVX5128IBase, EVEX_4V, EVEX_B;
1261 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1262 AVX512VLVectorVTInfo VTInfo,
1263 AVX512VLVectorVTInfo ShuffleMask> {
1264 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1265 ShuffleMask.info512>,
1266 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1267 ShuffleMask.info512>, EVEX_V512;
1268 let Predicates = [HasVLX] in {
1269 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1270 ShuffleMask.info128>,
1271 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1272 ShuffleMask.info128>, EVEX_V128;
1273 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1274 ShuffleMask.info256>,
1275 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1276 ShuffleMask.info256>, EVEX_V256;
1280 multiclass avx512_perm_t_sizes_w<bits<8> opc, string OpcodeStr,
1281 AVX512VLVectorVTInfo VTInfo,
1282 AVX512VLVectorVTInfo Idx> {
1283 let Predicates = [HasBWI] in
1284 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1285 Idx.info512>, EVEX_V512;
1286 let Predicates = [HasBWI, HasVLX] in {
1287 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1288 Idx.info128>, EVEX_V128;
1289 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1290 Idx.info256>, EVEX_V256;
1294 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1295 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1296 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1297 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1298 defm VPERMT2W : avx512_perm_t_sizes_w<0x7D, "vpermt2w",
1299 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1300 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1301 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1302 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1303 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1305 //===----------------------------------------------------------------------===//
1306 // AVX-512 - BLEND using mask
1308 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1309 let ExeDomain = _.ExeDomain in {
1310 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1311 (ins _.RC:$src1, _.RC:$src2),
1312 !strconcat(OpcodeStr,
1313 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1315 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1316 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1317 !strconcat(OpcodeStr,
1318 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1319 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1320 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1321 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1322 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1323 !strconcat(OpcodeStr,
1324 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1325 []>, EVEX_4V, EVEX_KZ;
1326 let mayLoad = 1 in {
1327 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1328 (ins _.RC:$src1, _.MemOp:$src2),
1329 !strconcat(OpcodeStr,
1330 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1331 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1332 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1333 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1334 !strconcat(OpcodeStr,
1335 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1336 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1337 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1338 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1339 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1340 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1341 !strconcat(OpcodeStr,
1342 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1343 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1347 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1349 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1350 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1351 !strconcat(OpcodeStr,
1352 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1353 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1354 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1355 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1356 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1358 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1359 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1360 !strconcat(OpcodeStr,
1361 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1362 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1363 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1367 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1368 AVX512VLVectorVTInfo VTInfo> {
1369 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1370 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1372 let Predicates = [HasVLX] in {
1373 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1374 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1375 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1376 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1380 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1381 AVX512VLVectorVTInfo VTInfo> {
1382 let Predicates = [HasBWI] in
1383 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1385 let Predicates = [HasBWI, HasVLX] in {
1386 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1387 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1392 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1393 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1394 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1395 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1396 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1397 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1400 let Predicates = [HasAVX512] in {
1401 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1402 (v8f32 VR256X:$src2))),
1404 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1405 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1406 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1408 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1409 (v8i32 VR256X:$src2))),
1411 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1412 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1413 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1415 //===----------------------------------------------------------------------===//
1416 // Compare Instructions
1417 //===----------------------------------------------------------------------===//
1419 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1421 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1423 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1425 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1426 "vcmp${cc}"#_.Suffix,
1427 "$src2, $src1", "$src1, $src2",
1428 (OpNode (_.VT _.RC:$src1),
1432 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1434 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1435 "vcmp${cc}"#_.Suffix,
1436 "$src2, $src1", "$src1, $src2",
1437 (OpNode (_.VT _.RC:$src1),
1438 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1439 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1441 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1443 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1444 "vcmp${cc}"#_.Suffix,
1445 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1446 (OpNodeRnd (_.VT _.RC:$src1),
1449 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1450 // Accept explicit immediate argument form instead of comparison code.
1451 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1452 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1454 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1456 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1457 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1459 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1461 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1462 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1464 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1466 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1468 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1470 }// let isAsmParserOnly = 1, hasSideEffects = 0
1472 let isCodeGenOnly = 1 in {
1473 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1474 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1475 !strconcat("vcmp${cc}", _.Suffix,
1476 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1477 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1480 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1482 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1484 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1485 !strconcat("vcmp${cc}", _.Suffix,
1486 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1487 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1488 (_.ScalarLdFrag addr:$src2),
1490 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1494 let Predicates = [HasAVX512] in {
1495 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1497 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1498 AVX512XDIi8Base, VEX_W;
1501 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1502 X86VectorVTInfo _> {
1503 def rr : AVX512BI<opc, MRMSrcReg,
1504 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1505 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1506 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1507 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1509 def rm : AVX512BI<opc, MRMSrcMem,
1510 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1511 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1512 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1513 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1514 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1515 def rrk : AVX512BI<opc, MRMSrcReg,
1516 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1518 "$dst {${mask}}, $src1, $src2}"),
1519 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1520 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1521 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1523 def rmk : AVX512BI<opc, MRMSrcMem,
1524 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1526 "$dst {${mask}}, $src1, $src2}"),
1527 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1528 (OpNode (_.VT _.RC:$src1),
1530 (_.LdFrag addr:$src2))))))],
1531 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1534 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1535 X86VectorVTInfo _> :
1536 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1537 let mayLoad = 1 in {
1538 def rmb : AVX512BI<opc, MRMSrcMem,
1539 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1540 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1541 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1542 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1543 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1544 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1545 def rmbk : AVX512BI<opc, MRMSrcMem,
1546 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1547 _.ScalarMemOp:$src2),
1548 !strconcat(OpcodeStr,
1549 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1550 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1551 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1552 (OpNode (_.VT _.RC:$src1),
1554 (_.ScalarLdFrag addr:$src2)))))],
1555 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1559 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1560 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1561 let Predicates = [prd] in
1562 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1565 let Predicates = [prd, HasVLX] in {
1566 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1568 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1573 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1574 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1576 let Predicates = [prd] in
1577 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1580 let Predicates = [prd, HasVLX] in {
1581 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1583 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1588 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1589 avx512vl_i8_info, HasBWI>,
1592 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1593 avx512vl_i16_info, HasBWI>,
1594 EVEX_CD8<16, CD8VF>;
1596 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1597 avx512vl_i32_info, HasAVX512>,
1598 EVEX_CD8<32, CD8VF>;
1600 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1601 avx512vl_i64_info, HasAVX512>,
1602 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1604 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1605 avx512vl_i8_info, HasBWI>,
1608 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1609 avx512vl_i16_info, HasBWI>,
1610 EVEX_CD8<16, CD8VF>;
1612 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1613 avx512vl_i32_info, HasAVX512>,
1614 EVEX_CD8<32, CD8VF>;
1616 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1617 avx512vl_i64_info, HasAVX512>,
1618 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1620 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1621 (COPY_TO_REGCLASS (VPCMPGTDZrr
1622 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1623 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1625 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1626 (COPY_TO_REGCLASS (VPCMPEQDZrr
1627 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1628 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1630 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1631 X86VectorVTInfo _> {
1632 def rri : AVX512AIi8<opc, MRMSrcReg,
1633 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1634 !strconcat("vpcmp${cc}", Suffix,
1635 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1636 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1638 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1640 def rmi : AVX512AIi8<opc, MRMSrcMem,
1641 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1642 !strconcat("vpcmp${cc}", Suffix,
1643 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1644 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1645 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1647 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1648 def rrik : AVX512AIi8<opc, MRMSrcReg,
1649 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1651 !strconcat("vpcmp${cc}", Suffix,
1652 "\t{$src2, $src1, $dst {${mask}}|",
1653 "$dst {${mask}}, $src1, $src2}"),
1654 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1655 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1657 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1659 def rmik : AVX512AIi8<opc, MRMSrcMem,
1660 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1662 !strconcat("vpcmp${cc}", Suffix,
1663 "\t{$src2, $src1, $dst {${mask}}|",
1664 "$dst {${mask}}, $src1, $src2}"),
1665 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1666 (OpNode (_.VT _.RC:$src1),
1667 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1669 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1671 // Accept explicit immediate argument form instead of comparison code.
1672 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1673 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1674 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1675 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1676 "$dst, $src1, $src2, $cc}"),
1677 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1679 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1680 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1681 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1682 "$dst, $src1, $src2, $cc}"),
1683 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1684 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1685 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1687 !strconcat("vpcmp", Suffix,
1688 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1689 "$dst {${mask}}, $src1, $src2, $cc}"),
1690 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1692 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1693 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1695 !strconcat("vpcmp", Suffix,
1696 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1697 "$dst {${mask}}, $src1, $src2, $cc}"),
1698 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1702 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1703 X86VectorVTInfo _> :
1704 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1705 def rmib : AVX512AIi8<opc, MRMSrcMem,
1706 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1708 !strconcat("vpcmp${cc}", Suffix,
1709 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1710 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1711 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1712 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1714 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1715 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1716 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1717 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1718 !strconcat("vpcmp${cc}", Suffix,
1719 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1720 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1721 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1722 (OpNode (_.VT _.RC:$src1),
1723 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1725 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1727 // Accept explicit immediate argument form instead of comparison code.
1728 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1729 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1730 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1732 !strconcat("vpcmp", Suffix,
1733 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1734 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1735 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1736 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1737 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1738 _.ScalarMemOp:$src2, u8imm:$cc),
1739 !strconcat("vpcmp", Suffix,
1740 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1741 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1742 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1746 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1747 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1748 let Predicates = [prd] in
1749 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1751 let Predicates = [prd, HasVLX] in {
1752 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1753 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1757 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1758 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1759 let Predicates = [prd] in
1760 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1763 let Predicates = [prd, HasVLX] in {
1764 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1766 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1771 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1772 HasBWI>, EVEX_CD8<8, CD8VF>;
1773 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1774 HasBWI>, EVEX_CD8<8, CD8VF>;
1776 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1777 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1778 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1779 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1781 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1782 HasAVX512>, EVEX_CD8<32, CD8VF>;
1783 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1784 HasAVX512>, EVEX_CD8<32, CD8VF>;
1786 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1787 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1788 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1789 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1791 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1793 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1794 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1795 "vcmp${cc}"#_.Suffix,
1796 "$src2, $src1", "$src1, $src2",
1797 (X86cmpm (_.VT _.RC:$src1),
1801 let mayLoad = 1 in {
1802 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1803 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1804 "vcmp${cc}"#_.Suffix,
1805 "$src2, $src1", "$src1, $src2",
1806 (X86cmpm (_.VT _.RC:$src1),
1807 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1810 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1812 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1813 "vcmp${cc}"#_.Suffix,
1814 "${src2}"##_.BroadcastStr##", $src1",
1815 "$src1, ${src2}"##_.BroadcastStr,
1816 (X86cmpm (_.VT _.RC:$src1),
1817 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1820 // Accept explicit immediate argument form instead of comparison code.
1821 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1822 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1824 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1826 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1828 let mayLoad = 1 in {
1829 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1831 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1833 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1835 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1837 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1839 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1840 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1845 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1846 // comparison code form (VCMP[EQ/LT/LE/...]
1847 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1848 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1849 "vcmp${cc}"#_.Suffix,
1850 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1851 (X86cmpmRnd (_.VT _.RC:$src1),
1854 (i32 FROUND_NO_EXC))>, EVEX_B;
1856 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1857 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1859 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1861 "$cc,{sae}, $src2, $src1",
1862 "$src1, $src2,{sae}, $cc">, EVEX_B;
1866 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1867 let Predicates = [HasAVX512] in {
1868 defm Z : avx512_vcmp_common<_.info512>,
1869 avx512_vcmp_sae<_.info512>, EVEX_V512;
1872 let Predicates = [HasAVX512,HasVLX] in {
1873 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1874 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1878 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1879 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1880 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1881 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1883 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1884 (COPY_TO_REGCLASS (VCMPPSZrri
1885 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1886 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1888 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1889 (COPY_TO_REGCLASS (VPCMPDZrri
1890 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1891 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1893 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1894 (COPY_TO_REGCLASS (VPCMPUDZrri
1895 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1896 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1899 // ----------------------------------------------------------------
1901 //handle fpclass instruction mask = op(reg_scalar,imm)
1902 // op(mem_scalar,imm)
1903 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1904 X86VectorVTInfo _, Predicate prd> {
1905 let Predicates = [prd] in {
1906 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1907 (ins _.RC:$src1, i32u8imm:$src2),
1908 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1909 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1910 (i32 imm:$src2)))], NoItinerary>;
1911 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1912 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1913 OpcodeStr##_.Suffix#
1914 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1915 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1916 (OpNode (_.VT _.RC:$src1),
1917 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1918 let mayLoad = 1, AddedComplexity = 20 in {
1919 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1920 (ins _.MemOp:$src1, i32u8imm:$src2),
1921 OpcodeStr##_.Suffix##
1922 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1924 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1925 (i32 imm:$src2)))], NoItinerary>;
1926 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1927 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1928 OpcodeStr##_.Suffix##
1929 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1930 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1931 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1932 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1937 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1938 // fpclass(reg_vec, mem_vec, imm)
1939 // fpclass(reg_vec, broadcast(eltVt), imm)
1940 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1941 X86VectorVTInfo _, string mem, string broadcast>{
1942 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1943 (ins _.RC:$src1, i32u8imm:$src2),
1944 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1945 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1946 (i32 imm:$src2)))], NoItinerary>;
1947 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1948 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1949 OpcodeStr##_.Suffix#
1950 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1951 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1952 (OpNode (_.VT _.RC:$src1),
1953 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1954 let mayLoad = 1 in {
1955 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1956 (ins _.MemOp:$src1, i32u8imm:$src2),
1957 OpcodeStr##_.Suffix##mem#
1958 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1959 [(set _.KRC:$dst,(OpNode
1960 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1961 (i32 imm:$src2)))], NoItinerary>;
1962 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1963 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1964 OpcodeStr##_.Suffix##mem#
1965 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1966 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1967 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1968 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1969 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1970 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1971 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1972 _.BroadcastStr##", $dst | $dst, ${src1}"
1973 ##_.BroadcastStr##", $src2}",
1974 [(set _.KRC:$dst,(OpNode
1975 (_.VT (X86VBroadcast
1976 (_.ScalarLdFrag addr:$src1))),
1977 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1978 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1979 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1980 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1981 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1982 _.BroadcastStr##", $src2}",
1983 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1984 (_.VT (X86VBroadcast
1985 (_.ScalarLdFrag addr:$src1))),
1986 (i32 imm:$src2))))], NoItinerary>,
1991 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1992 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1994 let Predicates = [prd] in {
1995 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1996 broadcast>, EVEX_V512;
1998 let Predicates = [prd, HasVLX] in {
1999 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
2000 broadcast>, EVEX_V128;
2001 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
2002 broadcast>, EVEX_V256;
2006 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
2007 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
2008 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
2009 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
2010 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
2011 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
2012 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2013 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
2014 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2015 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
2018 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
2019 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
2021 //-----------------------------------------------------------------
2022 // Mask register copy, including
2023 // - copy between mask registers
2024 // - load/store mask registers
2025 // - copy from GPR to mask register and vice versa
2027 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
2028 string OpcodeStr, RegisterClass KRC,
2029 ValueType vvt, X86MemOperand x86memop> {
2030 let hasSideEffects = 0 in {
2031 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2032 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2034 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2035 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2036 [(set KRC:$dst, (vvt (load addr:$src)))]>;
2038 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2039 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2040 [(store KRC:$src, addr:$dst)]>;
2044 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
2046 RegisterClass KRC, RegisterClass GRC> {
2047 let hasSideEffects = 0 in {
2048 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
2049 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2050 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
2051 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2055 let Predicates = [HasDQI] in
2056 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2057 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
2060 let Predicates = [HasAVX512] in
2061 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2062 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2065 let Predicates = [HasBWI] in {
2066 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2068 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2072 let Predicates = [HasBWI] in {
2073 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2075 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2079 // GR from/to mask register
2080 let Predicates = [HasDQI] in {
2081 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2082 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2083 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2084 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2086 let Predicates = [HasAVX512] in {
2087 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2088 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2089 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2090 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2092 let Predicates = [HasBWI] in {
2093 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2094 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2096 let Predicates = [HasBWI] in {
2097 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2098 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2102 let Predicates = [HasDQI] in {
2103 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2104 (KMOVBmk addr:$dst, VK8:$src)>;
2105 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2106 (KMOVBkm addr:$src)>;
2108 def : Pat<(store VK4:$src, addr:$dst),
2109 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2110 def : Pat<(store VK2:$src, addr:$dst),
2111 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2113 let Predicates = [HasAVX512, NoDQI] in {
2114 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2115 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2116 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2117 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2119 let Predicates = [HasAVX512] in {
2120 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2121 (KMOVWmk addr:$dst, VK16:$src)>;
2122 def : Pat<(i1 (load addr:$src)),
2123 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2124 (MOV8rm addr:$src), sub_8bit)),
2126 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2127 (KMOVWkm addr:$src)>;
2129 let Predicates = [HasBWI] in {
2130 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2131 (KMOVDmk addr:$dst, VK32:$src)>;
2132 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2133 (KMOVDkm addr:$src)>;
2135 let Predicates = [HasBWI] in {
2136 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2137 (KMOVQmk addr:$dst, VK64:$src)>;
2138 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2139 (KMOVQkm addr:$src)>;
2142 let Predicates = [HasAVX512] in {
2143 def : Pat<(i1 (trunc (i64 GR64:$src))),
2144 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2147 def : Pat<(i1 (trunc (i32 GR32:$src))),
2148 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2150 def : Pat<(i1 (trunc (i8 GR8:$src))),
2152 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2154 def : Pat<(i1 (trunc (i16 GR16:$src))),
2156 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2159 def : Pat<(i32 (zext VK1:$src)),
2160 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2161 def : Pat<(i32 (anyext VK1:$src)),
2162 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2164 def : Pat<(i8 (zext VK1:$src)),
2167 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2168 def : Pat<(i8 (anyext VK1:$src)),
2170 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2172 def : Pat<(i64 (zext VK1:$src)),
2173 (AND64ri8 (SUBREG_TO_REG (i64 0),
2174 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2175 def : Pat<(i16 (zext VK1:$src)),
2177 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2179 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2180 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2181 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2182 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2184 let Predicates = [HasBWI] in {
2185 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2186 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2187 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2188 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2192 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2193 let Predicates = [HasAVX512, NoDQI] in {
2194 // GR from/to 8-bit mask without native support
2195 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2197 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2198 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2200 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2204 let Predicates = [HasAVX512] in {
2205 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2206 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2207 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2208 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2210 let Predicates = [HasBWI] in {
2211 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2212 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2213 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2214 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2217 // Mask unary operation
2219 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2220 RegisterClass KRC, SDPatternOperator OpNode,
2222 let Predicates = [prd] in
2223 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2224 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2225 [(set KRC:$dst, (OpNode KRC:$src))]>;
2228 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2229 SDPatternOperator OpNode> {
2230 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2232 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2233 HasAVX512>, VEX, PS;
2234 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2235 HasBWI>, VEX, PD, VEX_W;
2236 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2237 HasBWI>, VEX, PS, VEX_W;
2240 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2242 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2243 let Predicates = [HasAVX512] in
2244 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2246 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2247 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2249 defm : avx512_mask_unop_int<"knot", "KNOT">;
2251 let Predicates = [HasDQI] in
2252 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2253 let Predicates = [HasAVX512] in
2254 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2255 let Predicates = [HasBWI] in
2256 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2257 let Predicates = [HasBWI] in
2258 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2260 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2261 let Predicates = [HasAVX512, NoDQI] in {
2262 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2263 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2264 def : Pat<(not VK8:$src),
2266 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2268 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2269 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2270 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2271 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2273 // Mask binary operation
2274 // - KAND, KANDN, KOR, KXNOR, KXOR
2275 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2276 RegisterClass KRC, SDPatternOperator OpNode,
2277 Predicate prd, bit IsCommutable> {
2278 let Predicates = [prd], isCommutable = IsCommutable in
2279 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2280 !strconcat(OpcodeStr,
2281 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2282 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2285 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2286 SDPatternOperator OpNode, bit IsCommutable,
2287 Predicate prdW = HasAVX512> {
2288 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2289 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2290 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2291 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2292 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2293 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2294 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2295 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2298 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2299 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2301 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2302 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2303 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2304 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2305 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2306 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2308 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2309 let Predicates = [HasAVX512] in
2310 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2311 (i16 GR16:$src1), (i16 GR16:$src2)),
2312 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2313 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2314 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2317 defm : avx512_mask_binop_int<"kand", "KAND">;
2318 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2319 defm : avx512_mask_binop_int<"kor", "KOR">;
2320 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2321 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2323 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2324 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2325 // for the DQI set, this type is legal and KxxxB instruction is used
2326 let Predicates = [NoDQI] in
2327 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2329 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2330 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2332 // All types smaller than 8 bits require conversion anyway
2333 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2334 (COPY_TO_REGCLASS (Inst
2335 (COPY_TO_REGCLASS VK1:$src1, VK16),
2336 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2337 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2338 (COPY_TO_REGCLASS (Inst
2339 (COPY_TO_REGCLASS VK2:$src1, VK16),
2340 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2341 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2342 (COPY_TO_REGCLASS (Inst
2343 (COPY_TO_REGCLASS VK4:$src1, VK16),
2344 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2347 defm : avx512_binop_pat<and, KANDWrr>;
2348 defm : avx512_binop_pat<andn, KANDNWrr>;
2349 defm : avx512_binop_pat<or, KORWrr>;
2350 defm : avx512_binop_pat<xnor, KXNORWrr>;
2351 defm : avx512_binop_pat<xor, KXORWrr>;
2353 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2354 (KXNORWrr VK16:$src1, VK16:$src2)>;
2355 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2356 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2357 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2358 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2359 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2360 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2362 let Predicates = [NoDQI] in
2363 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2364 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2365 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2367 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2368 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2369 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2371 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2372 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2373 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2375 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2376 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2377 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2380 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2381 RegisterClass KRCSrc, Predicate prd> {
2382 let Predicates = [prd] in {
2383 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2384 (ins KRC:$src1, KRC:$src2),
2385 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2388 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2389 (!cast<Instruction>(NAME##rr)
2390 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2391 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2395 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2396 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2397 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2400 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2401 SDNode OpNode, Predicate prd> {
2402 let Predicates = [prd], Defs = [EFLAGS] in
2403 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2404 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2405 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2408 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2409 Predicate prdW = HasAVX512> {
2410 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2412 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2414 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2416 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2420 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2421 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2424 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2426 let Predicates = [HasAVX512] in
2427 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2428 !strconcat(OpcodeStr,
2429 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2430 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2433 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2435 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2437 let Predicates = [HasDQI] in
2438 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2440 let Predicates = [HasBWI] in {
2441 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2443 let Predicates = [HasDQI] in
2444 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2449 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2450 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2452 // Mask setting all 0s or 1s
2453 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2454 let Predicates = [HasAVX512] in
2455 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2456 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2457 [(set KRC:$dst, (VT Val))]>;
2460 multiclass avx512_mask_setop_w<PatFrag Val> {
2461 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2462 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2463 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2464 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2467 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2468 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2470 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2471 let Predicates = [HasAVX512] in {
2472 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2473 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2474 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2475 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2476 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2477 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2478 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2480 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2481 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2483 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2484 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2486 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2487 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2489 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 0))),
2490 (v16i1 (COPY_TO_REGCLASS VK32:$src, VK16))>;
2492 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2493 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2495 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2496 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2498 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2499 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2500 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2501 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2503 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2504 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2506 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2507 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2508 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2509 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2511 def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2512 (v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
2513 def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2514 (v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
2515 def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2516 (v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
2517 def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2518 (v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
2520 def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2521 (v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
2522 def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2523 (v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
2524 def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2525 (v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
2526 def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2527 (v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
2528 def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
2529 (v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
2532 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2533 (v8i1 (COPY_TO_REGCLASS
2534 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2535 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2537 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2538 (v8i1 (COPY_TO_REGCLASS
2539 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2540 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2542 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2543 (v4i1 (COPY_TO_REGCLASS
2544 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2545 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2547 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2548 (v4i1 (COPY_TO_REGCLASS
2549 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2550 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2552 //===----------------------------------------------------------------------===//
2553 // AVX-512 - Aligned and unaligned load and store
2557 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2558 PatFrag ld_frag, PatFrag mload,
2559 bit IsReMaterializable = 1> {
2560 let hasSideEffects = 0 in {
2561 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2562 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2564 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2565 (ins _.KRCWM:$mask, _.RC:$src),
2566 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2567 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2570 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2571 SchedRW = [WriteLoad] in
2572 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2573 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2574 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2577 let Constraints = "$src0 = $dst" in {
2578 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2579 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2580 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2581 "${dst} {${mask}}, $src1}"),
2582 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2584 (_.VT _.RC:$src0))))], _.ExeDomain>,
2586 let mayLoad = 1, SchedRW = [WriteLoad] in
2587 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2588 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2589 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2590 "${dst} {${mask}}, $src1}"),
2591 [(set _.RC:$dst, (_.VT
2592 (vselect _.KRCWM:$mask,
2593 (_.VT (bitconvert (ld_frag addr:$src1))),
2594 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2596 let mayLoad = 1, SchedRW = [WriteLoad] in
2597 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2598 (ins _.KRCWM:$mask, _.MemOp:$src),
2599 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2600 "${dst} {${mask}} {z}, $src}",
2601 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2602 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2603 _.ExeDomain>, EVEX, EVEX_KZ;
2605 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2606 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2608 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2609 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2611 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2612 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2613 _.KRCWM:$mask, addr:$ptr)>;
2616 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2617 AVX512VLVectorVTInfo _,
2619 bit IsReMaterializable = 1> {
2620 let Predicates = [prd] in
2621 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2622 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2624 let Predicates = [prd, HasVLX] in {
2625 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2626 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2627 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2628 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2632 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2633 AVX512VLVectorVTInfo _,
2635 bit IsReMaterializable = 1> {
2636 let Predicates = [prd] in
2637 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2638 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2640 let Predicates = [prd, HasVLX] in {
2641 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2642 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2643 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2644 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2648 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2649 PatFrag st_frag, PatFrag mstore> {
2651 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2652 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2653 [], _.ExeDomain>, EVEX;
2654 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2655 (ins _.KRCWM:$mask, _.RC:$src),
2656 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2657 "${dst} {${mask}}, $src}",
2658 [], _.ExeDomain>, EVEX, EVEX_K;
2659 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2660 (ins _.KRCWM:$mask, _.RC:$src),
2661 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2662 "${dst} {${mask}} {z}, $src}",
2663 [], _.ExeDomain>, EVEX, EVEX_KZ;
2665 let mayStore = 1 in {
2666 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2667 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2668 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2669 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2670 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2671 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2672 [], _.ExeDomain>, EVEX, EVEX_K;
2675 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2676 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2677 _.KRCWM:$mask, _.RC:$src)>;
2681 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2682 AVX512VLVectorVTInfo _, Predicate prd> {
2683 let Predicates = [prd] in
2684 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2685 masked_store_unaligned>, EVEX_V512;
2687 let Predicates = [prd, HasVLX] in {
2688 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2689 masked_store_unaligned>, EVEX_V256;
2690 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2691 masked_store_unaligned>, EVEX_V128;
2695 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2696 AVX512VLVectorVTInfo _, Predicate prd> {
2697 let Predicates = [prd] in
2698 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2699 masked_store_aligned512>, EVEX_V512;
2701 let Predicates = [prd, HasVLX] in {
2702 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2703 masked_store_aligned256>, EVEX_V256;
2704 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2705 masked_store_aligned128>, EVEX_V128;
2709 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2711 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2712 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2714 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2716 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2717 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2719 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2720 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2721 PS, EVEX_CD8<32, CD8VF>;
2723 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2724 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2725 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2727 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2728 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2729 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2731 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2732 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2733 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2735 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2736 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2737 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2739 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2740 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2741 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2743 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2744 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2745 (VMOVAPDZrm addr:$ptr)>;
2747 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2748 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2749 (VMOVAPSZrm addr:$ptr)>;
2751 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2753 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2755 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2757 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2760 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2762 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2764 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2766 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2769 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2771 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2772 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2774 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2776 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2777 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2779 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2780 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2781 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2783 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2784 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2785 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2787 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2788 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2789 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2791 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2792 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2793 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2795 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2796 (v16i32 immAllZerosV), GR16:$mask)),
2797 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2799 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2800 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2801 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2803 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2805 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2807 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2809 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2812 let AddedComplexity = 20 in {
2813 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2814 (bc_v8i64 (v16i32 immAllZerosV)))),
2815 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2817 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2818 (v8i64 VR512:$src))),
2819 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2822 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2823 (v16i32 immAllZerosV))),
2824 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2826 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2827 (v16i32 VR512:$src))),
2828 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2831 // Move Int Doubleword to Packed Double Int
2833 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2834 "vmovd\t{$src, $dst|$dst, $src}",
2836 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2838 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2839 "vmovd\t{$src, $dst|$dst, $src}",
2841 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2842 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2843 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2844 "vmovq\t{$src, $dst|$dst, $src}",
2846 (v2i64 (scalar_to_vector GR64:$src)))],
2847 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2848 let isCodeGenOnly = 1 in {
2849 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2850 "vmovq\t{$src, $dst|$dst, $src}",
2851 [(set FR64:$dst, (bitconvert GR64:$src))],
2852 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2853 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2854 "vmovq\t{$src, $dst|$dst, $src}",
2855 [(set GR64:$dst, (bitconvert FR64:$src))],
2856 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2858 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2859 "vmovq\t{$src, $dst|$dst, $src}",
2860 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2861 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2862 EVEX_CD8<64, CD8VT1>;
2864 // Move Int Doubleword to Single Scalar
2866 let isCodeGenOnly = 1 in {
2867 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2868 "vmovd\t{$src, $dst|$dst, $src}",
2869 [(set FR32X:$dst, (bitconvert GR32:$src))],
2870 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2872 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2873 "vmovd\t{$src, $dst|$dst, $src}",
2874 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2875 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2878 // Move doubleword from xmm register to r/m32
2880 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2881 "vmovd\t{$src, $dst|$dst, $src}",
2882 [(set GR32:$dst, (extractelt (v4i32 VR128X:$src),
2883 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2885 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2886 (ins i32mem:$dst, VR128X:$src),
2887 "vmovd\t{$src, $dst|$dst, $src}",
2888 [(store (i32 (extractelt (v4i32 VR128X:$src),
2889 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2890 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2892 // Move quadword from xmm1 register to r/m64
2894 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2895 "vmovq\t{$src, $dst|$dst, $src}",
2896 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2898 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2899 Requires<[HasAVX512, In64BitMode]>;
2901 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2902 (ins i64mem:$dst, VR128X:$src),
2903 "vmovq\t{$src, $dst|$dst, $src}",
2904 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2905 addr:$dst)], IIC_SSE_MOVDQ>,
2906 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2907 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2909 def VMOV64toPQIZrr_REV : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
2911 "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
2912 EVEX, VEX_W, VEX_LIG;
2914 // Move Scalar Single to Double Int
2916 let isCodeGenOnly = 1 in {
2917 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2919 "vmovd\t{$src, $dst|$dst, $src}",
2920 [(set GR32:$dst, (bitconvert FR32X:$src))],
2921 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2922 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2923 (ins i32mem:$dst, FR32X:$src),
2924 "vmovd\t{$src, $dst|$dst, $src}",
2925 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2926 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2929 // Move Quadword Int to Packed Quadword Int
2931 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2933 "vmovq\t{$src, $dst|$dst, $src}",
2935 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2936 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2938 //===----------------------------------------------------------------------===//
2939 // AVX-512 MOVSS, MOVSD
2940 //===----------------------------------------------------------------------===//
2942 multiclass avx512_move_scalar <string asm, SDNode OpNode,
2943 X86VectorVTInfo _> {
2944 defm rr_Int : AVX512_maskable_scalar<0x10, MRMSrcReg, _, (outs _.RC:$dst),
2945 (ins _.RC:$src1, _.RC:$src2),
2946 asm, "$src2, $src1","$src1, $src2",
2947 (_.VT (OpNode (_.VT _.RC:$src1),
2948 (_.VT _.RC:$src2))),
2949 IIC_SSE_MOV_S_RR>, EVEX_4V;
2950 let Constraints = "$src1 = $dst" , mayLoad = 1 in
2951 defm rm_Int : AVX512_maskable_3src_scalar<0x10, MRMSrcMem, _,
2953 (ins _.ScalarMemOp:$src),
2955 (_.VT (OpNode (_.VT _.RC:$src1),
2956 (_.VT (scalar_to_vector
2957 (_.ScalarLdFrag addr:$src)))))>, EVEX;
2958 let isCodeGenOnly = 1 in {
2959 def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
2960 (ins _.RC:$src1, _.FRC:$src2),
2961 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2962 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1,
2963 (scalar_to_vector _.FRC:$src2))))],
2964 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V;
2966 def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
2967 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2968 [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
2969 _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX;
2971 let mayStore = 1 in {
2972 def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src),
2973 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2974 [(store _.FRC:$src, addr:$dst)], _.ExeDomain, IIC_SSE_MOV_S_MR>,
2976 def mrk: AVX512PI<0x11, MRMDestMem, (outs),
2977 (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src),
2978 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2979 [], _.ExeDomain, IIC_SSE_MOV_S_MR>, EVEX, EVEX_K;
2983 defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>,
2984 VEX_LIG, XS, EVEX_CD8<32, CD8VT1>;
2986 defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
2987 VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2989 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2990 (COPY_TO_REGCLASS (VMOVSSZrr_Intk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2991 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>;
2993 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2994 (COPY_TO_REGCLASS (VMOVSDZrr_Intk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2995 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), FR64X)>;
2997 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2998 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2999 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3001 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
3002 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3003 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
3004 XS, EVEX_4V, VEX_LIG;
3006 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
3007 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3008 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
3009 XD, EVEX_4V, VEX_LIG, VEX_W;
3011 let Predicates = [HasAVX512] in {
3012 let AddedComplexity = 15 in {
3013 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3014 // MOVS{S,D} to the lower bits.
3015 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3016 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
3017 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3018 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3019 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3020 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3021 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3022 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
3024 // Move low f32 and clear high bits.
3025 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3026 (SUBREG_TO_REG (i32 0),
3027 (VMOVSSZrr (v4f32 (V_SET0)),
3028 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3029 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3030 (SUBREG_TO_REG (i32 0),
3031 (VMOVSSZrr (v4i32 (V_SET0)),
3032 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3035 let AddedComplexity = 20 in {
3036 // MOVSSrm zeros the high parts of the register; represent this
3037 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3038 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3039 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3040 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3041 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3042 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3043 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3045 // MOVSDrm zeros the high parts of the register; represent this
3046 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3047 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3048 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3049 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3050 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3051 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3052 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3053 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3054 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3055 def : Pat<(v2f64 (X86vzload addr:$src)),
3056 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3058 // Represent the same patterns above but in the form they appear for
3060 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3061 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3062 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3063 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3064 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3065 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3066 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3067 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3068 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3070 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3071 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3072 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3073 FR32X:$src)), sub_xmm)>;
3074 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3075 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3076 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3077 FR64X:$src)), sub_xmm)>;
3078 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3079 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3080 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3082 // Move low f64 and clear high bits.
3083 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3084 (SUBREG_TO_REG (i32 0),
3085 (VMOVSDZrr (v2f64 (V_SET0)),
3086 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3088 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3089 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3090 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3092 // Extract and store.
3093 def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
3095 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3096 def : Pat<(store (f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
3098 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3100 // Shuffle with VMOVSS
3101 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3102 (VMOVSSZrr (v4i32 VR128X:$src1),
3103 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3104 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3105 (VMOVSSZrr (v4f32 VR128X:$src1),
3106 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3109 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3110 (SUBREG_TO_REG (i32 0),
3111 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3112 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3114 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3115 (SUBREG_TO_REG (i32 0),
3116 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3117 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3120 // Shuffle with VMOVSD
3121 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3122 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3123 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3124 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3125 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3126 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3127 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3128 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3131 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3132 (SUBREG_TO_REG (i32 0),
3133 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3134 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3136 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3137 (SUBREG_TO_REG (i32 0),
3138 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3139 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3142 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3143 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3144 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3145 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3146 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3147 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3148 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3149 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3152 let AddedComplexity = 15 in
3153 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3155 "vmovq\t{$src, $dst|$dst, $src}",
3156 [(set VR128X:$dst, (v2i64 (X86vzmovl
3157 (v2i64 VR128X:$src))))],
3158 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3160 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3161 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3163 "vmovq\t{$src, $dst|$dst, $src}",
3164 [(set VR128X:$dst, (v2i64 (X86vzmovl
3165 (loadv2i64 addr:$src))))],
3166 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3167 EVEX_CD8<8, CD8VT8>;
3169 let Predicates = [HasAVX512] in {
3170 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3171 let AddedComplexity = 20 in {
3172 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3173 (VMOVDI2PDIZrm addr:$src)>;
3174 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3175 (VMOV64toPQIZrr GR64:$src)>;
3176 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3177 (VMOVDI2PDIZrr GR32:$src)>;
3179 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3180 (VMOVDI2PDIZrm addr:$src)>;
3181 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3182 (VMOVDI2PDIZrm addr:$src)>;
3183 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3184 (VMOVZPQILo2PQIZrm addr:$src)>;
3185 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3186 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3187 def : Pat<(v2i64 (X86vzload addr:$src)),
3188 (VMOVZPQILo2PQIZrm addr:$src)>;
3191 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3192 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3193 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3194 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3195 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3196 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3197 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3200 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3201 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3203 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3204 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3206 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3207 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3209 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3210 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3212 //===----------------------------------------------------------------------===//
3213 // AVX-512 - Non-temporals
3214 //===----------------------------------------------------------------------===//
3215 let SchedRW = [WriteLoad] in {
3216 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3217 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3218 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3219 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3220 EVEX_CD8<64, CD8VF>;
3222 let Predicates = [HasAVX512, HasVLX] in {
3223 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3225 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3226 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3227 EVEX_CD8<64, CD8VF>;
3229 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3231 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3232 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3233 EVEX_CD8<64, CD8VF>;
3237 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3238 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3239 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3240 let SchedRW = [WriteStore], mayStore = 1,
3241 AddedComplexity = 400 in
3242 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3243 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3244 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3247 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3248 string elty, string elsz, string vsz512,
3249 string vsz256, string vsz128, Domain d,
3250 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3251 let Predicates = [prd] in
3252 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3253 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3254 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3257 let Predicates = [prd, HasVLX] in {
3258 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3259 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3260 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3263 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3264 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3265 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3270 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3271 "i", "64", "8", "4", "2", SSEPackedInt,
3272 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3274 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3275 "f", "64", "8", "4", "2", SSEPackedDouble,
3276 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3278 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3279 "f", "32", "16", "8", "4", SSEPackedSingle,
3280 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3282 //===----------------------------------------------------------------------===//
3283 // AVX-512 - Integer arithmetic
3285 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3286 X86VectorVTInfo _, OpndItins itins,
3287 bit IsCommutable = 0> {
3288 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3289 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3290 "$src2, $src1", "$src1, $src2",
3291 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3292 itins.rr, IsCommutable>,
3293 AVX512BIBase, EVEX_4V;
3296 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3297 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3298 "$src2, $src1", "$src1, $src2",
3299 (_.VT (OpNode _.RC:$src1,
3300 (bitconvert (_.LdFrag addr:$src2)))),
3302 AVX512BIBase, EVEX_4V;
3305 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3306 X86VectorVTInfo _, OpndItins itins,
3307 bit IsCommutable = 0> :
3308 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3310 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3311 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3312 "${src2}"##_.BroadcastStr##", $src1",
3313 "$src1, ${src2}"##_.BroadcastStr,
3314 (_.VT (OpNode _.RC:$src1,
3316 (_.ScalarLdFrag addr:$src2)))),
3318 AVX512BIBase, EVEX_4V, EVEX_B;
3321 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3322 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3323 Predicate prd, bit IsCommutable = 0> {
3324 let Predicates = [prd] in
3325 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3326 IsCommutable>, EVEX_V512;
3328 let Predicates = [prd, HasVLX] in {
3329 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3330 IsCommutable>, EVEX_V256;
3331 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3332 IsCommutable>, EVEX_V128;
3336 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3337 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3338 Predicate prd, bit IsCommutable = 0> {
3339 let Predicates = [prd] in
3340 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3341 IsCommutable>, EVEX_V512;
3343 let Predicates = [prd, HasVLX] in {
3344 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3345 IsCommutable>, EVEX_V256;
3346 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3347 IsCommutable>, EVEX_V128;
3351 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3352 OpndItins itins, Predicate prd,
3353 bit IsCommutable = 0> {
3354 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3355 itins, prd, IsCommutable>,
3356 VEX_W, EVEX_CD8<64, CD8VF>;
3359 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3360 OpndItins itins, Predicate prd,
3361 bit IsCommutable = 0> {
3362 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3363 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3366 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3367 OpndItins itins, Predicate prd,
3368 bit IsCommutable = 0> {
3369 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3370 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3373 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3374 OpndItins itins, Predicate prd,
3375 bit IsCommutable = 0> {
3376 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3377 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3380 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3381 SDNode OpNode, OpndItins itins, Predicate prd,
3382 bit IsCommutable = 0> {
3383 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3386 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3390 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3391 SDNode OpNode, OpndItins itins, Predicate prd,
3392 bit IsCommutable = 0> {
3393 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3396 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3400 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3401 bits<8> opc_d, bits<8> opc_q,
3402 string OpcodeStr, SDNode OpNode,
3403 OpndItins itins, bit IsCommutable = 0> {
3404 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3405 itins, HasAVX512, IsCommutable>,
3406 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3407 itins, HasBWI, IsCommutable>;
3410 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3411 SDNode OpNode,X86VectorVTInfo _Src,
3412 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3413 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3414 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3415 "$src2, $src1","$src1, $src2",
3417 (_Src.VT _Src.RC:$src1),
3418 (_Src.VT _Src.RC:$src2))),
3419 itins.rr, IsCommutable>,
3420 AVX512BIBase, EVEX_4V;
3421 let mayLoad = 1 in {
3422 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3423 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3424 "$src2, $src1", "$src1, $src2",
3425 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3426 (bitconvert (_Src.LdFrag addr:$src2)))),
3428 AVX512BIBase, EVEX_4V;
3430 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3431 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3433 "${src2}"##_Dst.BroadcastStr##", $src1",
3434 "$src1, ${src2}"##_Dst.BroadcastStr,
3435 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3436 (_Dst.VT (X86VBroadcast
3437 (_Dst.ScalarLdFrag addr:$src2)))))),
3439 AVX512BIBase, EVEX_4V, EVEX_B;
3443 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3444 SSE_INTALU_ITINS_P, 1>;
3445 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3446 SSE_INTALU_ITINS_P, 0>;
3447 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3448 SSE_INTALU_ITINS_P, HasBWI, 1>;
3449 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3450 SSE_INTALU_ITINS_P, HasBWI, 0>;
3451 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3452 SSE_INTALU_ITINS_P, HasBWI, 1>;
3453 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3454 SSE_INTALU_ITINS_P, HasBWI, 0>;
3455 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3456 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3457 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3458 SSE_INTALU_ITINS_P, HasBWI, 1>;
3459 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3460 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3461 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3463 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3465 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3467 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3468 SSE_INTALU_ITINS_P, HasBWI, 1>;
3470 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3471 SDNode OpNode, bit IsCommutable = 0> {
3473 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3474 v16i32_info, v8i64_info, IsCommutable>,
3475 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3476 let Predicates = [HasVLX] in {
3477 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3478 v8i32x_info, v4i64x_info, IsCommutable>,
3479 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3480 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3481 v4i32x_info, v2i64x_info, IsCommutable>,
3482 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3486 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3488 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3491 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3492 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3493 let mayLoad = 1 in {
3494 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3495 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3497 "${src2}"##_Src.BroadcastStr##", $src1",
3498 "$src1, ${src2}"##_Src.BroadcastStr,
3499 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3500 (_Src.VT (X86VBroadcast
3501 (_Src.ScalarLdFrag addr:$src2))))))>,
3502 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3506 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3507 SDNode OpNode,X86VectorVTInfo _Src,
3508 X86VectorVTInfo _Dst> {
3509 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3510 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3511 "$src2, $src1","$src1, $src2",
3513 (_Src.VT _Src.RC:$src1),
3514 (_Src.VT _Src.RC:$src2)))>,
3515 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3516 let mayLoad = 1 in {
3517 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3518 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3519 "$src2, $src1", "$src1, $src2",
3520 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3521 (bitconvert (_Src.LdFrag addr:$src2))))>,
3522 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3526 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3528 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3530 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3531 v32i16_info>, EVEX_V512;
3532 let Predicates = [HasVLX] in {
3533 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3535 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3536 v16i16x_info>, EVEX_V256;
3537 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3539 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3540 v8i16x_info>, EVEX_V128;
3543 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3545 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3546 v64i8_info>, EVEX_V512;
3547 let Predicates = [HasVLX] in {
3548 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3549 v32i8x_info>, EVEX_V256;
3550 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3551 v16i8x_info>, EVEX_V128;
3555 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3556 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3557 AVX512VLVectorVTInfo _Dst> {
3558 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3559 _Dst.info512>, EVEX_V512;
3560 let Predicates = [HasVLX] in {
3561 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3562 _Dst.info256>, EVEX_V256;
3563 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3564 _Dst.info128>, EVEX_V128;
3568 let Predicates = [HasBWI] in {
3569 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3570 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3571 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3572 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3574 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3575 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3576 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3577 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3580 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3581 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3582 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3583 SSE_INTALU_ITINS_P, HasBWI, 1>;
3584 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3585 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3587 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3588 SSE_INTALU_ITINS_P, HasBWI, 1>;
3589 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3590 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3591 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3592 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3594 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3595 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3596 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3597 SSE_INTALU_ITINS_P, HasBWI, 1>;
3598 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3599 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3601 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3602 SSE_INTALU_ITINS_P, HasBWI, 1>;
3603 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3604 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3605 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3606 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3607 //===----------------------------------------------------------------------===//
3608 // AVX-512 Logical Instructions
3609 //===----------------------------------------------------------------------===//
3611 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3612 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3613 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3614 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3615 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3616 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3617 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3618 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3620 //===----------------------------------------------------------------------===//
3621 // AVX-512 FP arithmetic
3622 //===----------------------------------------------------------------------===//
3623 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3624 SDNode OpNode, SDNode VecNode, OpndItins itins,
3627 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3628 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3629 "$src2, $src1", "$src1, $src2",
3630 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3631 (i32 FROUND_CURRENT)),
3632 itins.rr, IsCommutable>;
3634 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3635 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3636 "$src2, $src1", "$src1, $src2",
3637 (VecNode (_.VT _.RC:$src1),
3638 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3639 (i32 FROUND_CURRENT)),
3640 itins.rm, IsCommutable>;
3641 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3642 Predicates = [HasAVX512] in {
3643 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3644 (ins _.FRC:$src1, _.FRC:$src2),
3645 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3646 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3648 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3649 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3650 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3651 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3652 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3656 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3657 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3659 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3660 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3661 "$rc, $src2, $src1", "$src1, $src2, $rc",
3662 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3663 (i32 imm:$rc)), itins.rr, IsCommutable>,
3666 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3667 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3669 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3670 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3671 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3672 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3673 (i32 FROUND_NO_EXC))>, EVEX_B;
3676 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3678 SizeItins itins, bit IsCommutable> {
3679 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3680 itins.s, IsCommutable>,
3681 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3682 itins.s, IsCommutable>,
3683 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3684 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3685 itins.d, IsCommutable>,
3686 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3687 itins.d, IsCommutable>,
3688 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3691 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3693 SizeItins itins, bit IsCommutable> {
3694 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3695 itins.s, IsCommutable>,
3696 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3697 itins.s, IsCommutable>,
3698 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3699 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3700 itins.d, IsCommutable>,
3701 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3702 itins.d, IsCommutable>,
3703 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3705 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3706 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3707 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3708 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3709 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3710 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3712 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3713 X86VectorVTInfo _, bit IsCommutable> {
3714 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3715 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3716 "$src2, $src1", "$src1, $src2",
3717 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3718 let mayLoad = 1 in {
3719 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3720 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3721 "$src2, $src1", "$src1, $src2",
3722 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3723 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3724 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3725 "${src2}"##_.BroadcastStr##", $src1",
3726 "$src1, ${src2}"##_.BroadcastStr,
3727 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3728 (_.ScalarLdFrag addr:$src2))))>,
3733 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3734 X86VectorVTInfo _> {
3735 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3736 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3737 "$rc, $src2, $src1", "$src1, $src2, $rc",
3738 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3739 EVEX_4V, EVEX_B, EVEX_RC;
3743 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3744 X86VectorVTInfo _> {
3745 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3746 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3747 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3748 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3752 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3753 bit IsCommutable = 0> {
3754 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3755 IsCommutable>, EVEX_V512, PS,
3756 EVEX_CD8<32, CD8VF>;
3757 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3758 IsCommutable>, EVEX_V512, PD, VEX_W,
3759 EVEX_CD8<64, CD8VF>;
3761 // Define only if AVX512VL feature is present.
3762 let Predicates = [HasVLX] in {
3763 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3764 IsCommutable>, EVEX_V128, PS,
3765 EVEX_CD8<32, CD8VF>;
3766 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3767 IsCommutable>, EVEX_V256, PS,
3768 EVEX_CD8<32, CD8VF>;
3769 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3770 IsCommutable>, EVEX_V128, PD, VEX_W,
3771 EVEX_CD8<64, CD8VF>;
3772 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3773 IsCommutable>, EVEX_V256, PD, VEX_W,
3774 EVEX_CD8<64, CD8VF>;
3778 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3779 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3780 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3781 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3782 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3785 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3786 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3787 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3788 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3789 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3792 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3793 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3794 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3795 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3796 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3797 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3798 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3799 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3800 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3801 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3802 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3803 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3804 let Predicates = [HasDQI] in {
3805 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3806 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3807 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3808 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3811 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3812 X86VectorVTInfo _> {
3813 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3814 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3815 "$src2, $src1", "$src1, $src2",
3816 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3817 let mayLoad = 1 in {
3818 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3819 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3820 "$src2, $src1", "$src1, $src2",
3821 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3822 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3823 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3824 "${src2}"##_.BroadcastStr##", $src1",
3825 "$src1, ${src2}"##_.BroadcastStr,
3826 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3827 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3832 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3833 X86VectorVTInfo _> {
3834 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3835 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3836 "$src2, $src1", "$src1, $src2",
3837 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3838 let mayLoad = 1 in {
3839 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3840 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3841 "$src2, $src1", "$src1, $src2",
3842 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3846 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3847 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3848 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3849 EVEX_V512, EVEX_CD8<32, CD8VF>;
3850 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3851 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3852 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3853 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3854 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3855 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3856 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3857 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3858 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3860 // Define only if AVX512VL feature is present.
3861 let Predicates = [HasVLX] in {
3862 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3863 EVEX_V128, EVEX_CD8<32, CD8VF>;
3864 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3865 EVEX_V256, EVEX_CD8<32, CD8VF>;
3866 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3867 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3868 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3869 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3872 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3874 //===----------------------------------------------------------------------===//
3875 // AVX-512 VPTESTM instructions
3876 //===----------------------------------------------------------------------===//
3878 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3879 X86VectorVTInfo _> {
3880 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3881 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3882 "$src2, $src1", "$src1, $src2",
3883 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3886 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3887 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3888 "$src2, $src1", "$src1, $src2",
3889 (OpNode (_.VT _.RC:$src1),
3890 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3892 EVEX_CD8<_.EltSize, CD8VF>;
3895 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3896 X86VectorVTInfo _> {
3898 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3899 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3900 "${src2}"##_.BroadcastStr##", $src1",
3901 "$src1, ${src2}"##_.BroadcastStr,
3902 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3903 (_.ScalarLdFrag addr:$src2))))>,
3904 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3906 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3907 AVX512VLVectorVTInfo _> {
3908 let Predicates = [HasAVX512] in
3909 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3910 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3912 let Predicates = [HasAVX512, HasVLX] in {
3913 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3914 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3915 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3916 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3920 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3921 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3923 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3924 avx512vl_i64_info>, VEX_W;
3927 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3929 let Predicates = [HasBWI] in {
3930 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3932 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3935 let Predicates = [HasVLX, HasBWI] in {
3937 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3939 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3941 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3943 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3948 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3950 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3951 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3953 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3954 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3956 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3957 (v16i32 VR512:$src2), (i16 -1))),
3958 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3960 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3961 (v8i64 VR512:$src2), (i8 -1))),
3962 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3964 //===----------------------------------------------------------------------===//
3965 // AVX-512 Shift instructions
3966 //===----------------------------------------------------------------------===//
3967 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3968 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3969 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3970 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3971 "$src2, $src1", "$src1, $src2",
3972 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3973 SSE_INTSHIFT_ITINS_P.rr>;
3975 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3976 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3977 "$src2, $src1", "$src1, $src2",
3978 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3980 SSE_INTSHIFT_ITINS_P.rm>;
3983 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3984 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3986 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3987 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3988 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3989 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3990 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3993 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3994 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3995 // src2 is always 128-bit
3996 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3997 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3998 "$src2, $src1", "$src1, $src2",
3999 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
4000 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
4001 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4002 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
4003 "$src2, $src1", "$src1, $src2",
4004 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4005 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4009 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4010 ValueType SrcVT, PatFrag bc_frag,
4011 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4012 let Predicates = [prd] in
4013 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4014 VTInfo.info512>, EVEX_V512,
4015 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4016 let Predicates = [prd, HasVLX] in {
4017 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4018 VTInfo.info256>, EVEX_V256,
4019 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4020 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4021 VTInfo.info128>, EVEX_V128,
4022 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4026 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4027 string OpcodeStr, SDNode OpNode> {
4028 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4029 avx512vl_i32_info, HasAVX512>;
4030 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4031 avx512vl_i64_info, HasAVX512>, VEX_W;
4032 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4033 avx512vl_i16_info, HasBWI>;
4036 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4037 string OpcodeStr, SDNode OpNode,
4038 AVX512VLVectorVTInfo VTInfo> {
4039 let Predicates = [HasAVX512] in
4040 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4042 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4043 VTInfo.info512>, EVEX_V512;
4044 let Predicates = [HasAVX512, HasVLX] in {
4045 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4047 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4048 VTInfo.info256>, EVEX_V256;
4049 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4051 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4052 VTInfo.info128>, EVEX_V128;
4056 multiclass avx512_shift_rmi_w<bits<8> opcw,
4057 Format ImmFormR, Format ImmFormM,
4058 string OpcodeStr, SDNode OpNode> {
4059 let Predicates = [HasBWI] in
4060 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4061 v32i16_info>, EVEX_V512;
4062 let Predicates = [HasVLX, HasBWI] in {
4063 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4064 v16i16x_info>, EVEX_V256;
4065 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4066 v8i16x_info>, EVEX_V128;
4070 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4071 Format ImmFormR, Format ImmFormM,
4072 string OpcodeStr, SDNode OpNode> {
4073 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4074 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4075 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4076 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4079 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4080 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4082 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4083 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4085 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4086 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4088 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4089 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4091 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4092 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4093 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4095 //===-------------------------------------------------------------------===//
4096 // Variable Bit Shifts
4097 //===-------------------------------------------------------------------===//
4098 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4099 X86VectorVTInfo _> {
4100 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4101 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4102 "$src2, $src1", "$src1, $src2",
4103 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4104 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4106 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4107 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4108 "$src2, $src1", "$src1, $src2",
4109 (_.VT (OpNode _.RC:$src1,
4110 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4111 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4112 EVEX_CD8<_.EltSize, CD8VF>;
4115 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4116 X86VectorVTInfo _> {
4118 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4119 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4120 "${src2}"##_.BroadcastStr##", $src1",
4121 "$src1, ${src2}"##_.BroadcastStr,
4122 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4123 (_.ScalarLdFrag addr:$src2))))),
4124 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4125 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4127 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4128 AVX512VLVectorVTInfo _> {
4129 let Predicates = [HasAVX512] in
4130 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4131 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4133 let Predicates = [HasAVX512, HasVLX] in {
4134 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4135 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4136 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4137 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4141 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4143 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4145 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4146 avx512vl_i64_info>, VEX_W;
4149 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4151 let Predicates = [HasBWI] in
4152 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4154 let Predicates = [HasVLX, HasBWI] in {
4156 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4158 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4163 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4164 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4165 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4166 avx512_var_shift_w<0x11, "vpsravw", sra>;
4167 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4168 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4169 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4170 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4172 //===-------------------------------------------------------------------===//
4173 // 1-src variable permutation VPERMW/D/Q
4174 //===-------------------------------------------------------------------===//
4175 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4176 AVX512VLVectorVTInfo _> {
4177 let Predicates = [HasAVX512] in
4178 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4179 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4181 let Predicates = [HasAVX512, HasVLX] in
4182 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4183 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4186 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4187 string OpcodeStr, SDNode OpNode,
4188 AVX512VLVectorVTInfo VTInfo> {
4189 let Predicates = [HasAVX512] in
4190 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4192 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4193 VTInfo.info512>, EVEX_V512;
4194 let Predicates = [HasAVX512, HasVLX] in
4195 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4197 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4198 VTInfo.info256>, EVEX_V256;
4202 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4204 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4206 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4207 avx512vl_i64_info>, VEX_W;
4208 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4210 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4211 avx512vl_f64_info>, VEX_W;
4213 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4214 X86VPermi, avx512vl_i64_info>,
4215 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4216 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4217 X86VPermi, avx512vl_f64_info>,
4218 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4219 //===----------------------------------------------------------------------===//
4220 // AVX-512 - VPERMIL
4221 //===----------------------------------------------------------------------===//
4223 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4224 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4225 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4226 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4227 "$src2, $src1", "$src1, $src2",
4228 (_.VT (OpNode _.RC:$src1,
4229 (Ctrl.VT Ctrl.RC:$src2)))>,
4231 let mayLoad = 1 in {
4232 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4233 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4234 "$src2, $src1", "$src1, $src2",
4237 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4238 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4239 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4240 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4241 "${src2}"##_.BroadcastStr##", $src1",
4242 "$src1, ${src2}"##_.BroadcastStr,
4245 (Ctrl.VT (X86VBroadcast
4246 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4247 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4251 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4252 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4253 let Predicates = [HasAVX512] in {
4254 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4255 Ctrl.info512>, EVEX_V512;
4257 let Predicates = [HasAVX512, HasVLX] in {
4258 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4259 Ctrl.info128>, EVEX_V128;
4260 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4261 Ctrl.info256>, EVEX_V256;
4265 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4266 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4268 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4269 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4271 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4273 let isCodeGenOnly = 1 in {
4274 // lowering implementation with the alternative types
4275 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4276 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4277 OpcodeStr, X86VPermilpi, Ctrl>,
4278 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4282 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4284 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4285 avx512vl_i64_info>, VEX_W;
4286 //===----------------------------------------------------------------------===//
4287 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4288 //===----------------------------------------------------------------------===//
4290 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4291 X86PShufd, avx512vl_i32_info>,
4292 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4293 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4294 X86PShufhw>, EVEX, AVX512XSIi8Base;
4295 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4296 X86PShuflw>, EVEX, AVX512XDIi8Base;
4298 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4299 let Predicates = [HasBWI] in
4300 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4302 let Predicates = [HasVLX, HasBWI] in {
4303 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4304 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4308 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4310 //===----------------------------------------------------------------------===//
4311 // Move Low to High and High to Low packed FP Instructions
4312 //===----------------------------------------------------------------------===//
4313 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4314 (ins VR128X:$src1, VR128X:$src2),
4315 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4316 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4317 IIC_SSE_MOV_LH>, EVEX_4V;
4318 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4319 (ins VR128X:$src1, VR128X:$src2),
4320 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4321 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4322 IIC_SSE_MOV_LH>, EVEX_4V;
4324 let Predicates = [HasAVX512] in {
4326 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4327 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4328 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4329 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4332 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4333 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4336 //===----------------------------------------------------------------------===//
4337 // VMOVHPS/PD VMOVLPS Instructions
4338 // All patterns was taken from SSS implementation.
4339 //===----------------------------------------------------------------------===//
4340 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4341 X86VectorVTInfo _> {
4343 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4344 (ins _.RC:$src1, f64mem:$src2),
4345 !strconcat(OpcodeStr,
4346 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4350 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4351 IIC_SSE_MOV_LH>, EVEX_4V;
4354 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4355 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4356 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4357 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4358 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4359 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4360 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4361 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4363 let Predicates = [HasAVX512] in {
4365 def : Pat<(X86Movlhps VR128X:$src1,
4366 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4367 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4368 def : Pat<(X86Movlhps VR128X:$src1,
4369 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4370 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4372 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4373 (scalar_to_vector (loadf64 addr:$src2)))),
4374 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4375 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4376 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4377 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4379 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4380 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4381 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4382 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4384 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4385 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4386 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4387 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4388 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4389 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4390 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4393 let mayStore = 1 in {
4394 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4395 (ins f64mem:$dst, VR128X:$src),
4396 "vmovhps\t{$src, $dst|$dst, $src}",
4397 [(store (f64 (vector_extract
4398 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4399 (bc_v2f64 (v4f32 VR128X:$src))),
4400 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4401 EVEX, EVEX_CD8<32, CD8VT2>;
4402 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4403 (ins f64mem:$dst, VR128X:$src),
4404 "vmovhpd\t{$src, $dst|$dst, $src}",
4405 [(store (f64 (vector_extract
4406 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4407 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4408 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4409 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4410 (ins f64mem:$dst, VR128X:$src),
4411 "vmovlps\t{$src, $dst|$dst, $src}",
4412 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4413 (iPTR 0))), addr:$dst)],
4415 EVEX, EVEX_CD8<32, CD8VT2>;
4416 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4417 (ins f64mem:$dst, VR128X:$src),
4418 "vmovlpd\t{$src, $dst|$dst, $src}",
4419 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4420 (iPTR 0))), addr:$dst)],
4422 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4424 let Predicates = [HasAVX512] in {
4426 def : Pat<(store (f64 (vector_extract
4427 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4428 (iPTR 0))), addr:$dst),
4429 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4431 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4433 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4434 def : Pat<(store (v4i32 (X86Movlps
4435 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4436 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4438 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4440 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4441 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4443 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4445 //===----------------------------------------------------------------------===//
4446 // FMA - Fused Multiply Operations
4449 let Constraints = "$src1 = $dst" in {
4450 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4451 X86VectorVTInfo _> {
4452 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4453 (ins _.RC:$src2, _.RC:$src3),
4454 OpcodeStr, "$src3, $src2", "$src2, $src3",
4455 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4458 let mayLoad = 1 in {
4459 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4460 (ins _.RC:$src2, _.MemOp:$src3),
4461 OpcodeStr, "$src3, $src2", "$src2, $src3",
4462 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4465 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4466 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4467 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4468 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4470 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4471 AVX512FMA3Base, EVEX_B;
4475 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4476 X86VectorVTInfo _> {
4477 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4478 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4479 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4480 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4481 AVX512FMA3Base, EVEX_B, EVEX_RC;
4483 } // Constraints = "$src1 = $dst"
4485 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4486 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4487 let Predicates = [HasAVX512] in {
4488 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4489 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4490 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4492 let Predicates = [HasVLX, HasAVX512] in {
4493 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4494 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4495 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4496 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4500 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4501 SDNode OpNodeRnd > {
4502 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4504 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4505 avx512vl_f64_info>, VEX_W;
4508 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4509 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4510 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4511 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4512 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4513 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4516 let Constraints = "$src1 = $dst" in {
4517 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4518 X86VectorVTInfo _> {
4519 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4520 (ins _.RC:$src2, _.RC:$src3),
4521 OpcodeStr, "$src3, $src2", "$src2, $src3",
4522 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4525 let mayLoad = 1 in {
4526 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4527 (ins _.RC:$src2, _.MemOp:$src3),
4528 OpcodeStr, "$src3, $src2", "$src2, $src3",
4529 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4532 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4533 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4534 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4535 "$src2, ${src3}"##_.BroadcastStr,
4536 (_.VT (OpNode _.RC:$src2,
4537 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4538 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4542 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4543 X86VectorVTInfo _> {
4544 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4545 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4546 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4547 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4548 AVX512FMA3Base, EVEX_B, EVEX_RC;
4550 } // Constraints = "$src1 = $dst"
4552 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4553 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4554 let Predicates = [HasAVX512] in {
4555 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4556 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4557 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4559 let Predicates = [HasVLX, HasAVX512] in {
4560 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4561 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4562 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4563 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4567 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4568 SDNode OpNodeRnd > {
4569 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4571 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4572 avx512vl_f64_info>, VEX_W;
4575 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4576 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4577 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4578 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4579 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4580 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4582 let Constraints = "$src1 = $dst" in {
4583 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4584 X86VectorVTInfo _> {
4585 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4586 (ins _.RC:$src3, _.RC:$src2),
4587 OpcodeStr, "$src2, $src3", "$src3, $src2",
4588 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4591 let mayLoad = 1 in {
4592 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4593 (ins _.RC:$src3, _.MemOp:$src2),
4594 OpcodeStr, "$src2, $src3", "$src3, $src2",
4595 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4598 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4599 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4600 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4601 "$src3, ${src2}"##_.BroadcastStr,
4602 (_.VT (OpNode _.RC:$src1,
4603 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4604 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4608 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4609 X86VectorVTInfo _> {
4610 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4611 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4612 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4613 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4614 AVX512FMA3Base, EVEX_B, EVEX_RC;
4616 } // Constraints = "$src1 = $dst"
4618 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4619 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4620 let Predicates = [HasAVX512] in {
4621 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4622 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4623 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4625 let Predicates = [HasVLX, HasAVX512] in {
4626 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4627 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4628 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4629 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4633 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4634 SDNode OpNodeRnd > {
4635 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4637 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4638 avx512vl_f64_info>, VEX_W;
4641 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4642 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4643 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4644 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4645 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4646 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4649 let Constraints = "$src1 = $dst" in {
4650 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4651 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4652 dag RHS_r, dag RHS_m > {
4653 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4654 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4655 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4658 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4659 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4660 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4662 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4663 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4664 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4665 AVX512FMA3Base, EVEX_B, EVEX_RC;
4667 let isCodeGenOnly = 1 in {
4668 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4669 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4670 !strconcat(OpcodeStr,
4671 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4674 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4675 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4676 !strconcat(OpcodeStr,
4677 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4679 }// isCodeGenOnly = 1
4681 }// Constraints = "$src1 = $dst"
4683 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4684 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4687 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4688 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4689 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4690 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4691 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4693 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4695 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4696 (_.ScalarLdFrag addr:$src3))))>;
4698 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4699 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4700 (_.VT (OpNode _.RC:$src2,
4701 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4703 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4705 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4707 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4708 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4710 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4711 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4712 (_.VT (OpNode _.RC:$src1,
4713 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4715 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4717 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4719 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4720 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4723 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4724 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4725 let Predicates = [HasAVX512] in {
4726 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4727 OpNodeRnd, f32x_info, "SS">,
4728 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4729 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4730 OpNodeRnd, f64x_info, "SD">,
4731 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4735 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4736 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4737 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4738 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4740 //===----------------------------------------------------------------------===//
4741 // AVX-512 Scalar convert from sign integer to float/double
4742 //===----------------------------------------------------------------------===//
4744 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4745 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4746 PatFrag ld_frag, string asm> {
4747 let hasSideEffects = 0 in {
4748 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4749 (ins DstVT.FRC:$src1, SrcRC:$src),
4750 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4753 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4754 (ins DstVT.FRC:$src1, x86memop:$src),
4755 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4757 } // hasSideEffects = 0
4758 let isCodeGenOnly = 1 in {
4759 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4760 (ins DstVT.RC:$src1, SrcRC:$src2),
4761 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4762 [(set DstVT.RC:$dst,
4763 (OpNode (DstVT.VT DstVT.RC:$src1),
4765 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4767 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4768 (ins DstVT.RC:$src1, x86memop:$src2),
4769 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4770 [(set DstVT.RC:$dst,
4771 (OpNode (DstVT.VT DstVT.RC:$src1),
4772 (ld_frag addr:$src2),
4773 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4774 }//isCodeGenOnly = 1
4777 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4778 X86VectorVTInfo DstVT, string asm> {
4779 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4780 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4782 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4783 [(set DstVT.RC:$dst,
4784 (OpNode (DstVT.VT DstVT.RC:$src1),
4786 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4789 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4790 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4791 PatFrag ld_frag, string asm> {
4792 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4793 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4797 let Predicates = [HasAVX512] in {
4798 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4799 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4800 XS, EVEX_CD8<32, CD8VT1>;
4801 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4802 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4803 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4804 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4805 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4806 XD, EVEX_CD8<32, CD8VT1>;
4807 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4808 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4809 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4811 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4812 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4813 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4814 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4815 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4816 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4817 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4818 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4820 def : Pat<(f32 (sint_to_fp GR32:$src)),
4821 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4822 def : Pat<(f32 (sint_to_fp GR64:$src)),
4823 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4824 def : Pat<(f64 (sint_to_fp GR32:$src)),
4825 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4826 def : Pat<(f64 (sint_to_fp GR64:$src)),
4827 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4829 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4830 v4f32x_info, i32mem, loadi32,
4831 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4832 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4833 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4834 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4835 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4836 i32mem, loadi32, "cvtusi2sd{l}">,
4837 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4838 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4839 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4840 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4842 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4843 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4844 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4845 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4846 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4847 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4848 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4849 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4851 def : Pat<(f32 (uint_to_fp GR32:$src)),
4852 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4853 def : Pat<(f32 (uint_to_fp GR64:$src)),
4854 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4855 def : Pat<(f64 (uint_to_fp GR32:$src)),
4856 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4857 def : Pat<(f64 (uint_to_fp GR64:$src)),
4858 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4861 //===----------------------------------------------------------------------===//
4862 // AVX-512 Scalar convert from float/double to integer
4863 //===----------------------------------------------------------------------===//
4864 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4865 RegisterClass DstRC, Intrinsic Int,
4866 Operand memop, ComplexPattern mem_cpat, string asm> {
4867 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4868 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4869 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4870 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4871 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4872 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4873 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4875 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4876 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4877 } // hasSideEffects = 0, Predicates = [HasAVX512]
4880 // Convert float/double to signed/unsigned int 32/64
4881 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4882 ssmem, sse_load_f32, "cvtss2si">,
4883 XS, EVEX_CD8<32, CD8VT1>;
4884 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4885 int_x86_sse_cvtss2si64,
4886 ssmem, sse_load_f32, "cvtss2si">,
4887 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4888 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4889 int_x86_avx512_cvtss2usi,
4890 ssmem, sse_load_f32, "cvtss2usi">,
4891 XS, EVEX_CD8<32, CD8VT1>;
4892 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4893 int_x86_avx512_cvtss2usi64, ssmem,
4894 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4895 EVEX_CD8<32, CD8VT1>;
4896 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4897 sdmem, sse_load_f64, "cvtsd2si">,
4898 XD, EVEX_CD8<64, CD8VT1>;
4899 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4900 int_x86_sse2_cvtsd2si64,
4901 sdmem, sse_load_f64, "cvtsd2si">,
4902 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4903 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4904 int_x86_avx512_cvtsd2usi,
4905 sdmem, sse_load_f64, "cvtsd2usi">,
4906 XD, EVEX_CD8<64, CD8VT1>;
4907 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4908 int_x86_avx512_cvtsd2usi64, sdmem,
4909 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4910 EVEX_CD8<64, CD8VT1>;
4912 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4913 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4914 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4915 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4916 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4917 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4918 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4919 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4920 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4921 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4922 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4923 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4924 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4926 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4927 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4928 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4929 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4931 // Convert float/double to signed/unsigned int 32/64 with truncation
4932 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4933 X86VectorVTInfo _DstRC, SDNode OpNode,
4935 let Predicates = [HasAVX512] in {
4936 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4937 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4938 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4939 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4940 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4942 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4943 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4944 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4947 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4948 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4949 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4950 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4951 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4952 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4953 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4954 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4955 (i32 FROUND_NO_EXC)))]>,
4956 EVEX,VEX_LIG , EVEX_B;
4958 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4959 (ins _SrcRC.MemOp:$src),
4960 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4963 } // isCodeGenOnly = 1, hasSideEffects = 0
4968 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4969 fp_to_sint,X86cvttss2IntRnd>,
4970 XS, EVEX_CD8<32, CD8VT1>;
4971 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4972 fp_to_sint,X86cvttss2IntRnd>,
4973 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4974 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4975 fp_to_sint,X86cvttsd2IntRnd>,
4976 XD, EVEX_CD8<64, CD8VT1>;
4977 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4978 fp_to_sint,X86cvttsd2IntRnd>,
4979 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4981 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4982 fp_to_uint,X86cvttss2UIntRnd>,
4983 XS, EVEX_CD8<32, CD8VT1>;
4984 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4985 fp_to_uint,X86cvttss2UIntRnd>,
4986 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4987 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4988 fp_to_uint,X86cvttsd2UIntRnd>,
4989 XD, EVEX_CD8<64, CD8VT1>;
4990 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4991 fp_to_uint,X86cvttsd2UIntRnd>,
4992 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4993 let Predicates = [HasAVX512] in {
4994 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4995 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4996 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4997 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4998 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4999 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5000 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
5001 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5004 //===----------------------------------------------------------------------===//
5005 // AVX-512 Convert form float to double and back
5006 //===----------------------------------------------------------------------===//
5007 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5008 X86VectorVTInfo _Src, SDNode OpNode> {
5009 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5010 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5011 "$src2, $src1", "$src1, $src2",
5012 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5013 (_Src.VT _Src.RC:$src2)))>,
5014 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
5015 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5016 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
5017 "$src2, $src1", "$src1, $src2",
5018 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5019 (_Src.VT (scalar_to_vector
5020 (_Src.ScalarLdFrag addr:$src2)))))>,
5021 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
5024 // Scalar Coversion with SAE - suppress all exceptions
5025 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5026 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5027 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5028 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5029 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5030 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5031 (_Src.VT _Src.RC:$src2),
5032 (i32 FROUND_NO_EXC)))>,
5033 EVEX_4V, VEX_LIG, EVEX_B;
5036 // Scalar Conversion with rounding control (RC)
5037 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5038 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5039 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5040 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
5041 "$rc, $src2, $src1", "$src1, $src2, $rc",
5042 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5043 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
5044 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
5047 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
5048 SDNode OpNodeRnd, X86VectorVTInfo _src,
5049 X86VectorVTInfo _dst> {
5050 let Predicates = [HasAVX512] in {
5051 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5052 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
5053 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5058 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5059 SDNode OpNodeRnd, X86VectorVTInfo _src,
5060 X86VectorVTInfo _dst> {
5061 let Predicates = [HasAVX512] in {
5062 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5063 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5064 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5067 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5068 X86froundRnd, f64x_info, f32x_info>;
5069 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5070 X86fpextRnd,f32x_info, f64x_info >;
5072 def : Pat<(f64 (fextend FR32X:$src)),
5073 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5074 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5075 Requires<[HasAVX512]>;
5076 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5077 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5078 Requires<[HasAVX512]>;
5080 def : Pat<(f64 (extloadf32 addr:$src)),
5081 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5082 Requires<[HasAVX512, OptForSize]>;
5084 def : Pat<(f64 (extloadf32 addr:$src)),
5085 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5086 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5087 Requires<[HasAVX512, OptForSpeed]>;
5089 def : Pat<(f32 (fround FR64X:$src)),
5090 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5091 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5092 Requires<[HasAVX512]>;
5093 //===----------------------------------------------------------------------===//
5094 // AVX-512 Vector convert from signed/unsigned integer to float/double
5095 // and from float/double to signed/unsigned integer
5096 //===----------------------------------------------------------------------===//
5098 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5099 X86VectorVTInfo _Src, SDNode OpNode,
5100 string Broadcast = _.BroadcastStr,
5101 string Alias = ""> {
5103 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5104 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5105 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5107 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5108 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5109 (_.VT (OpNode (_Src.VT
5110 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5112 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5113 (ins _Src.MemOp:$src), OpcodeStr,
5114 "${src}"##Broadcast, "${src}"##Broadcast,
5115 (_.VT (OpNode (_Src.VT
5116 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5119 // Coversion with SAE - suppress all exceptions
5120 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5121 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5122 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5123 (ins _Src.RC:$src), OpcodeStr,
5124 "{sae}, $src", "$src, {sae}",
5125 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5126 (i32 FROUND_NO_EXC)))>,
5130 // Conversion with rounding control (RC)
5131 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5132 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5133 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5134 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5135 "$rc, $src", "$src, $rc",
5136 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5137 EVEX, EVEX_B, EVEX_RC;
5140 // Extend Float to Double
5141 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5142 let Predicates = [HasAVX512] in {
5143 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5144 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5145 X86vfpextRnd>, EVEX_V512;
5147 let Predicates = [HasVLX] in {
5148 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5149 X86vfpext, "{1to2}">, EVEX_V128;
5150 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5155 // Truncate Double to Float
5156 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5157 let Predicates = [HasAVX512] in {
5158 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5159 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5160 X86vfproundRnd>, EVEX_V512;
5162 let Predicates = [HasVLX] in {
5163 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5164 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5165 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5166 "{1to4}", "{y}">, EVEX_V256;
5170 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5171 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5172 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5173 PS, EVEX_CD8<32, CD8VH>;
5175 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5176 (VCVTPS2PDZrm addr:$src)>;
5178 let Predicates = [HasVLX] in {
5179 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5180 (VCVTPS2PDZ256rm addr:$src)>;
5183 // Convert Signed/Unsigned Doubleword to Double
5184 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5186 // No rounding in this op
5187 let Predicates = [HasAVX512] in
5188 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5191 let Predicates = [HasVLX] in {
5192 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5193 OpNode128, "{1to2}">, EVEX_V128;
5194 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5199 // Convert Signed/Unsigned Doubleword to Float
5200 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5202 let Predicates = [HasAVX512] in
5203 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5204 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5205 OpNodeRnd>, EVEX_V512;
5207 let Predicates = [HasVLX] in {
5208 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5210 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5215 // Convert Float to Signed/Unsigned Doubleword with truncation
5216 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5217 SDNode OpNode, SDNode OpNodeRnd> {
5218 let Predicates = [HasAVX512] in {
5219 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5220 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5221 OpNodeRnd>, EVEX_V512;
5223 let Predicates = [HasVLX] in {
5224 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5226 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5231 // Convert Float to Signed/Unsigned Doubleword
5232 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5233 SDNode OpNode, SDNode OpNodeRnd> {
5234 let Predicates = [HasAVX512] in {
5235 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5236 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5237 OpNodeRnd>, EVEX_V512;
5239 let Predicates = [HasVLX] in {
5240 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5242 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5247 // Convert Double to Signed/Unsigned Doubleword with truncation
5248 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5249 SDNode OpNode, SDNode OpNodeRnd> {
5250 let Predicates = [HasAVX512] in {
5251 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5252 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5253 OpNodeRnd>, EVEX_V512;
5255 let Predicates = [HasVLX] in {
5256 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5257 // memory forms of these instructions in Asm Parcer. They have the same
5258 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5259 // due to the same reason.
5260 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5261 "{1to2}", "{x}">, EVEX_V128;
5262 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5263 "{1to4}", "{y}">, EVEX_V256;
5267 // Convert Double to Signed/Unsigned Doubleword
5268 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5269 SDNode OpNode, SDNode OpNodeRnd> {
5270 let Predicates = [HasAVX512] in {
5271 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5272 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5273 OpNodeRnd>, EVEX_V512;
5275 let Predicates = [HasVLX] in {
5276 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5277 // memory forms of these instructions in Asm Parcer. They have the same
5278 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5279 // due to the same reason.
5280 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5281 "{1to2}", "{x}">, EVEX_V128;
5282 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5283 "{1to4}", "{y}">, EVEX_V256;
5287 // Convert Double to Signed/Unsigned Quardword
5288 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5289 SDNode OpNode, SDNode OpNodeRnd> {
5290 let Predicates = [HasDQI] in {
5291 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5292 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5293 OpNodeRnd>, EVEX_V512;
5295 let Predicates = [HasDQI, HasVLX] in {
5296 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5298 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5303 // Convert Double to Signed/Unsigned Quardword with truncation
5304 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5305 SDNode OpNode, SDNode OpNodeRnd> {
5306 let Predicates = [HasDQI] in {
5307 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5308 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5309 OpNodeRnd>, EVEX_V512;
5311 let Predicates = [HasDQI, HasVLX] in {
5312 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5314 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5319 // Convert Signed/Unsigned Quardword to Double
5320 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5321 SDNode OpNode, SDNode OpNodeRnd> {
5322 let Predicates = [HasDQI] in {
5323 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5324 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5325 OpNodeRnd>, EVEX_V512;
5327 let Predicates = [HasDQI, HasVLX] in {
5328 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5330 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5335 // Convert Float to Signed/Unsigned Quardword
5336 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5337 SDNode OpNode, SDNode OpNodeRnd> {
5338 let Predicates = [HasDQI] in {
5339 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5340 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5341 OpNodeRnd>, EVEX_V512;
5343 let Predicates = [HasDQI, HasVLX] in {
5344 // Explicitly specified broadcast string, since we take only 2 elements
5345 // from v4f32x_info source
5346 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5347 "{1to2}">, EVEX_V128;
5348 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5353 // Convert Float to Signed/Unsigned Quardword with truncation
5354 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5355 SDNode OpNode, SDNode OpNodeRnd> {
5356 let Predicates = [HasDQI] in {
5357 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5358 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5359 OpNodeRnd>, EVEX_V512;
5361 let Predicates = [HasDQI, HasVLX] in {
5362 // Explicitly specified broadcast string, since we take only 2 elements
5363 // from v4f32x_info source
5364 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5365 "{1to2}">, EVEX_V128;
5366 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5371 // Convert Signed/Unsigned Quardword to Float
5372 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5373 SDNode OpNode, SDNode OpNodeRnd> {
5374 let Predicates = [HasDQI] in {
5375 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5376 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5377 OpNodeRnd>, EVEX_V512;
5379 let Predicates = [HasDQI, HasVLX] in {
5380 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5381 // memory forms of these instructions in Asm Parcer. They have the same
5382 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5383 // due to the same reason.
5384 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5385 "{1to2}", "{x}">, EVEX_V128;
5386 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5387 "{1to4}", "{y}">, EVEX_V256;
5391 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5392 EVEX_CD8<32, CD8VH>;
5394 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5396 PS, EVEX_CD8<32, CD8VF>;
5398 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5400 XS, EVEX_CD8<32, CD8VF>;
5402 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5404 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5406 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5407 X86VFpToUintRnd>, PS,
5408 EVEX_CD8<32, CD8VF>;
5410 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5411 X86VFpToUintRnd>, PS, VEX_W,
5412 EVEX_CD8<64, CD8VF>;
5414 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5415 XS, EVEX_CD8<32, CD8VH>;
5417 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5418 X86VUintToFpRnd>, XD,
5419 EVEX_CD8<32, CD8VF>;
5421 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5422 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5424 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5425 X86cvtpd2IntRnd>, XD, VEX_W,
5426 EVEX_CD8<64, CD8VF>;
5428 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5430 PS, EVEX_CD8<32, CD8VF>;
5431 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5432 X86cvtpd2UIntRnd>, VEX_W,
5433 PS, EVEX_CD8<64, CD8VF>;
5435 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5436 X86cvtpd2IntRnd>, VEX_W,
5437 PD, EVEX_CD8<64, CD8VF>;
5439 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5440 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5442 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5443 X86cvtpd2UIntRnd>, VEX_W,
5444 PD, EVEX_CD8<64, CD8VF>;
5446 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5447 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5449 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5450 X86VFpToSlongRnd>, VEX_W,
5451 PD, EVEX_CD8<64, CD8VF>;
5453 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5454 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5456 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5457 X86VFpToUlongRnd>, VEX_W,
5458 PD, EVEX_CD8<64, CD8VF>;
5460 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5461 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5463 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5464 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5466 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5467 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5469 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5470 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5472 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5473 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5475 let Predicates = [HasAVX512, NoVLX] in {
5476 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5477 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5478 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5480 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5481 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5482 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5484 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5485 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5486 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5488 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5489 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5490 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5492 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5493 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5494 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5497 let Predicates = [HasAVX512] in {
5498 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5499 (VCVTPD2PSZrm addr:$src)>;
5500 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5501 (VCVTPS2PDZrm addr:$src)>;
5504 //===----------------------------------------------------------------------===//
5505 // Half precision conversion instructions
5506 //===----------------------------------------------------------------------===//
5507 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5508 X86MemOperand x86memop, PatFrag ld_frag> {
5509 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5510 "vcvtph2ps", "$src", "$src",
5511 (X86cvtph2ps (_src.VT _src.RC:$src),
5512 (i32 FROUND_CURRENT))>, T8PD;
5513 let hasSideEffects = 0, mayLoad = 1 in {
5514 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5515 "vcvtph2ps", "$src", "$src",
5516 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5517 (i32 FROUND_CURRENT))>, T8PD;
5521 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5522 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5523 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5524 (X86cvtph2ps (_src.VT _src.RC:$src),
5525 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5529 let Predicates = [HasAVX512] in {
5530 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5531 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5532 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5533 let Predicates = [HasVLX] in {
5534 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5535 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5536 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5537 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5541 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5542 X86MemOperand x86memop> {
5543 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5544 (ins _src.RC:$src1, i32u8imm:$src2),
5545 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5546 (X86cvtps2ph (_src.VT _src.RC:$src1),
5548 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5549 let hasSideEffects = 0, mayStore = 1 in {
5550 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5551 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5552 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5553 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5554 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5556 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5557 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5558 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5562 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5563 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5564 (ins _src.RC:$src1, i32u8imm:$src2),
5565 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5566 (X86cvtps2ph (_src.VT _src.RC:$src1),
5568 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5570 let Predicates = [HasAVX512] in {
5571 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5572 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5573 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5574 let Predicates = [HasVLX] in {
5575 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5576 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5577 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5578 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5582 // Unordered/Ordered scalar fp compare with Sea and set EFLAGS
5583 multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _, SDNode OpNode,
5585 def rb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
5586 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
5587 [(set EFLAGS, (OpNode (_.VT _.RC:$src1), _.RC:$src2,
5588 (i32 FROUND_NO_EXC)))],
5589 IIC_SSE_COMIS_RR>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
5593 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5594 defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, X86ucomiSae, "vucomiss">,
5595 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5596 defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, X86ucomiSae, "vucomisd">,
5597 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5598 defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, X86comiSae, "vcomiss">,
5599 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5600 defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, X86comiSae, "vcomisd">,
5601 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5604 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5605 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5606 "ucomiss">, PS, EVEX, VEX_LIG,
5607 EVEX_CD8<32, CD8VT1>;
5608 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5609 "ucomisd">, PD, EVEX,
5610 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5611 let Pattern = []<dag> in {
5612 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5613 "comiss">, PS, EVEX, VEX_LIG,
5614 EVEX_CD8<32, CD8VT1>;
5615 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5616 "comisd">, PD, EVEX,
5617 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5619 let isCodeGenOnly = 1 in {
5620 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5621 load, "ucomiss">, PS, EVEX, VEX_LIG,
5622 EVEX_CD8<32, CD8VT1>;
5623 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5624 load, "ucomisd">, PD, EVEX,
5625 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5627 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5628 load, "comiss">, PS, EVEX, VEX_LIG,
5629 EVEX_CD8<32, CD8VT1>;
5630 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5631 load, "comisd">, PD, EVEX,
5632 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5636 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5637 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5638 X86VectorVTInfo _> {
5639 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5640 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5641 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5642 "$src2, $src1", "$src1, $src2",
5643 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5644 let mayLoad = 1 in {
5645 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5646 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5647 "$src2, $src1", "$src1, $src2",
5648 (OpNode (_.VT _.RC:$src1),
5649 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5654 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5655 EVEX_CD8<32, CD8VT1>, T8PD;
5656 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5657 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5658 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5659 EVEX_CD8<32, CD8VT1>, T8PD;
5660 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5661 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5663 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5664 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5665 X86VectorVTInfo _> {
5666 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5667 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5668 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5669 let mayLoad = 1 in {
5670 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5671 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5673 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5674 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5675 (ins _.ScalarMemOp:$src), OpcodeStr,
5676 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5678 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5683 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5684 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5685 EVEX_V512, EVEX_CD8<32, CD8VF>;
5686 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5687 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5689 // Define only if AVX512VL feature is present.
5690 let Predicates = [HasVLX] in {
5691 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5692 OpNode, v4f32x_info>,
5693 EVEX_V128, EVEX_CD8<32, CD8VF>;
5694 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5695 OpNode, v8f32x_info>,
5696 EVEX_V256, EVEX_CD8<32, CD8VF>;
5697 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5698 OpNode, v2f64x_info>,
5699 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5700 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5701 OpNode, v4f64x_info>,
5702 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5706 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5707 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5709 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5710 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5711 (VRSQRT14PSZr VR512:$src)>;
5712 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5713 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5714 (VRSQRT14PDZr VR512:$src)>;
5716 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5717 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5718 (VRCP14PSZr VR512:$src)>;
5719 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5720 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5721 (VRCP14PDZr VR512:$src)>;
5723 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5724 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5727 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5728 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5729 "$src2, $src1", "$src1, $src2",
5730 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5731 (i32 FROUND_CURRENT))>;
5733 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5734 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5735 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5736 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5737 (i32 FROUND_NO_EXC))>, EVEX_B;
5739 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5740 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5741 "$src2, $src1", "$src1, $src2",
5742 (OpNode (_.VT _.RC:$src1),
5743 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5744 (i32 FROUND_CURRENT))>;
5747 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5748 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5749 EVEX_CD8<32, CD8VT1>;
5750 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5751 EVEX_CD8<64, CD8VT1>, VEX_W;
5754 let hasSideEffects = 0, Predicates = [HasERI] in {
5755 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5756 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5759 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5760 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5762 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5765 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5766 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5767 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5769 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5770 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5772 (bitconvert (_.LdFrag addr:$src))),
5773 (i32 FROUND_CURRENT))>;
5775 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5776 (ins _.MemOp:$src), OpcodeStr,
5777 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5779 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5780 (i32 FROUND_CURRENT))>, EVEX_B;
5782 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5784 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5785 (ins _.RC:$src), OpcodeStr,
5786 "{sae}, $src", "$src, {sae}",
5787 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5790 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5791 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5792 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5793 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5794 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5795 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5796 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5799 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5801 // Define only if AVX512VL feature is present.
5802 let Predicates = [HasVLX] in {
5803 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5804 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5805 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5806 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5807 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5808 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5809 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5810 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5813 let Predicates = [HasERI], hasSideEffects = 0 in {
5815 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5816 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5817 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5819 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5820 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5822 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5823 SDNode OpNodeRnd, X86VectorVTInfo _>{
5824 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5825 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5826 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5827 EVEX, EVEX_B, EVEX_RC;
5830 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5831 SDNode OpNode, X86VectorVTInfo _>{
5832 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5833 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5834 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5835 let mayLoad = 1 in {
5836 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5837 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5839 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5841 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5842 (ins _.ScalarMemOp:$src), OpcodeStr,
5843 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5845 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5850 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5852 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5854 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5855 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5857 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5858 // Define only if AVX512VL feature is present.
5859 let Predicates = [HasVLX] in {
5860 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5861 OpNode, v4f32x_info>,
5862 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5863 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5864 OpNode, v8f32x_info>,
5865 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5866 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5867 OpNode, v2f64x_info>,
5868 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5869 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5870 OpNode, v4f64x_info>,
5871 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5875 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5877 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5878 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5879 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5880 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5883 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5884 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5886 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5887 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5888 "$src2, $src1", "$src1, $src2",
5889 (OpNodeRnd (_.VT _.RC:$src1),
5891 (i32 FROUND_CURRENT))>;
5893 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5894 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5895 "$src2, $src1", "$src1, $src2",
5896 (OpNodeRnd (_.VT _.RC:$src1),
5897 (_.VT (scalar_to_vector
5898 (_.ScalarLdFrag addr:$src2))),
5899 (i32 FROUND_CURRENT))>;
5901 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5902 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5903 "$rc, $src2, $src1", "$src1, $src2, $rc",
5904 (OpNodeRnd (_.VT _.RC:$src1),
5909 let isCodeGenOnly = 1 in {
5910 def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
5911 (ins _.FRC:$src1, _.FRC:$src2),
5912 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5915 def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
5916 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5917 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5920 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5921 (!cast<Instruction>(NAME#SUFF#Zr)
5922 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5924 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5925 (!cast<Instruction>(NAME#SUFF#Zm)
5926 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5929 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5930 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5931 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5932 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5933 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5936 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5937 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5939 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5941 let Predicates = [HasAVX512] in {
5942 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5943 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5944 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5945 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5946 Requires<[OptForSize]>;
5947 def : Pat<(f32 (X86frcp FR32X:$src)),
5948 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5949 def : Pat<(f32 (X86frcp (load addr:$src))),
5950 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5951 Requires<[OptForSize]>;
5955 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5957 let ExeDomain = _.ExeDomain in {
5958 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5959 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5960 "$src3, $src2, $src1", "$src1, $src2, $src3",
5961 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5962 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5964 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5965 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5966 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5967 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5968 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5971 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5972 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5973 "$src3, $src2, $src1", "$src1, $src2, $src3",
5974 (_.VT (X86RndScales (_.VT _.RC:$src1),
5975 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5976 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5978 let Predicates = [HasAVX512] in {
5979 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5980 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5981 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5982 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5983 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5984 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5985 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5986 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5987 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5988 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5989 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5990 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5991 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5992 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5993 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5995 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5996 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5997 addr:$src, (i32 0x1))), _.FRC)>;
5998 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5999 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6000 addr:$src, (i32 0x2))), _.FRC)>;
6001 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6002 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6003 addr:$src, (i32 0x3))), _.FRC)>;
6004 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6005 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6006 addr:$src, (i32 0x4))), _.FRC)>;
6007 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6008 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6009 addr:$src, (i32 0xc))), _.FRC)>;
6013 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
6014 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6016 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
6017 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
6019 //-------------------------------------------------
6020 // Integer truncate and extend operations
6021 //-------------------------------------------------
6023 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6024 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
6025 X86MemOperand x86memop> {
6027 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
6028 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6029 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6032 // for intrinsic patter match
6033 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6034 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6036 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6039 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6040 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6041 DestInfo.ImmAllZerosV)),
6042 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6045 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6046 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6047 DestInfo.RC:$src0)),
6048 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6049 DestInfo.KRCWM:$mask ,
6052 let mayStore = 1 in {
6053 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
6054 (ins x86memop:$dst, SrcInfo.RC:$src),
6055 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6058 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
6059 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6060 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6065 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6066 X86VectorVTInfo DestInfo,
6067 PatFrag truncFrag, PatFrag mtruncFrag > {
6069 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6070 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6071 addr:$dst, SrcInfo.RC:$src)>;
6073 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6074 (SrcInfo.VT SrcInfo.RC:$src)),
6075 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6076 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6079 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6080 X86VectorVTInfo DestInfo, string sat > {
6082 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6083 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6084 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6085 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6086 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6087 (SrcInfo.VT SrcInfo.RC:$src))>;
6089 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6090 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6091 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6092 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6093 (SrcInfo.VT SrcInfo.RC:$src))>;
6096 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6097 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6098 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6099 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6100 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6101 Predicate prd = HasAVX512>{
6103 let Predicates = [HasVLX, prd] in {
6104 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6105 DestInfoZ128, x86memopZ128>,
6106 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6107 truncFrag, mtruncFrag>, EVEX_V128;
6109 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6110 DestInfoZ256, x86memopZ256>,
6111 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6112 truncFrag, mtruncFrag>, EVEX_V256;
6114 let Predicates = [prd] in
6115 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6116 DestInfoZ, x86memopZ>,
6117 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6118 truncFrag, mtruncFrag>, EVEX_V512;
6121 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6122 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6123 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6124 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6125 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6127 let Predicates = [HasVLX, prd] in {
6128 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6129 DestInfoZ128, x86memopZ128>,
6130 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6133 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6134 DestInfoZ256, x86memopZ256>,
6135 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6138 let Predicates = [prd] in
6139 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6140 DestInfoZ, x86memopZ>,
6141 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6145 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6146 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6147 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6148 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6150 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6151 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6152 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6153 sat>, EVEX_CD8<8, CD8VO>;
6156 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6157 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6158 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6159 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6161 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6162 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6163 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6164 sat>, EVEX_CD8<16, CD8VQ>;
6167 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6168 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6169 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6170 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6172 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6173 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6174 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6175 sat>, EVEX_CD8<32, CD8VH>;
6178 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6179 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6180 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6181 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6183 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6184 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6185 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6186 sat>, EVEX_CD8<8, CD8VQ>;
6189 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6190 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6191 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6192 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6194 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6195 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6196 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6197 sat>, EVEX_CD8<16, CD8VH>;
6200 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6201 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6202 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6203 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6205 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6206 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6207 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6208 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6211 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6212 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6213 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6215 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6216 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6217 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6219 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6220 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6221 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6223 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6224 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6225 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6227 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6228 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6229 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6231 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6232 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6233 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6235 let Predicates = [HasAVX512, NoVLX] in {
6236 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6237 (v8i16 (EXTRACT_SUBREG
6238 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6239 VR256X:$src, sub_ymm)))), sub_xmm))>;
6240 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6241 (v4i32 (EXTRACT_SUBREG
6242 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6243 VR256X:$src, sub_ymm)))), sub_xmm))>;
6246 let Predicates = [HasBWI, NoVLX] in {
6247 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6248 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6249 VR256X:$src, sub_ymm))), sub_xmm))>;
6252 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6253 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6254 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6256 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6257 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6258 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6261 let mayLoad = 1 in {
6262 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6263 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6264 (DestInfo.VT (LdFrag addr:$src))>,
6269 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6270 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6271 let Predicates = [HasVLX, HasBWI] in {
6272 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6273 v16i8x_info, i64mem, LdFrag, OpNode>,
6274 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6276 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6277 v16i8x_info, i128mem, LdFrag, OpNode>,
6278 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6280 let Predicates = [HasBWI] in {
6281 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6282 v32i8x_info, i256mem, LdFrag, OpNode>,
6283 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6287 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6288 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6289 let Predicates = [HasVLX, HasAVX512] in {
6290 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6291 v16i8x_info, i32mem, LdFrag, OpNode>,
6292 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6294 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6295 v16i8x_info, i64mem, LdFrag, OpNode>,
6296 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6298 let Predicates = [HasAVX512] in {
6299 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6300 v16i8x_info, i128mem, LdFrag, OpNode>,
6301 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6305 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6306 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6307 let Predicates = [HasVLX, HasAVX512] in {
6308 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6309 v16i8x_info, i16mem, LdFrag, OpNode>,
6310 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6312 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6313 v16i8x_info, i32mem, LdFrag, OpNode>,
6314 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6316 let Predicates = [HasAVX512] in {
6317 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6318 v16i8x_info, i64mem, LdFrag, OpNode>,
6319 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6323 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6324 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6325 let Predicates = [HasVLX, HasAVX512] in {
6326 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6327 v8i16x_info, i64mem, LdFrag, OpNode>,
6328 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6330 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6331 v8i16x_info, i128mem, LdFrag, OpNode>,
6332 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6334 let Predicates = [HasAVX512] in {
6335 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6336 v16i16x_info, i256mem, LdFrag, OpNode>,
6337 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6341 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6342 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6343 let Predicates = [HasVLX, HasAVX512] in {
6344 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6345 v8i16x_info, i32mem, LdFrag, OpNode>,
6346 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6348 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6349 v8i16x_info, i64mem, LdFrag, OpNode>,
6350 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6352 let Predicates = [HasAVX512] in {
6353 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6354 v8i16x_info, i128mem, LdFrag, OpNode>,
6355 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6359 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6360 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6362 let Predicates = [HasVLX, HasAVX512] in {
6363 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6364 v4i32x_info, i64mem, LdFrag, OpNode>,
6365 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6367 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6368 v4i32x_info, i128mem, LdFrag, OpNode>,
6369 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6371 let Predicates = [HasAVX512] in {
6372 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6373 v8i32x_info, i256mem, LdFrag, OpNode>,
6374 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6378 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6379 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6380 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6381 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6382 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6383 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6386 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6387 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6388 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6389 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6390 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6391 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6393 //===----------------------------------------------------------------------===//
6394 // GATHER - SCATTER Operations
6396 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6397 X86MemOperand memop, PatFrag GatherNode> {
6398 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6399 ExeDomain = _.ExeDomain in
6400 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6401 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6402 !strconcat(OpcodeStr#_.Suffix,
6403 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6404 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6405 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6406 vectoraddr:$src2))]>, EVEX, EVEX_K,
6407 EVEX_CD8<_.EltSize, CD8VT1>;
6410 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6411 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6412 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6413 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6414 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6415 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6416 let Predicates = [HasVLX] in {
6417 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6418 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6419 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6420 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6421 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6422 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6423 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6424 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6428 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6429 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6430 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6431 mgatherv16i32>, EVEX_V512;
6432 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6433 mgatherv8i64>, EVEX_V512;
6434 let Predicates = [HasVLX] in {
6435 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6436 vy32xmem, mgatherv8i32>, EVEX_V256;
6437 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6438 vy64xmem, mgatherv4i64>, EVEX_V256;
6439 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6440 vx32xmem, mgatherv4i32>, EVEX_V128;
6441 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6442 vx64xmem, mgatherv2i64>, EVEX_V128;
6447 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6448 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6450 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6451 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6453 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6454 X86MemOperand memop, PatFrag ScatterNode> {
6456 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6458 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6459 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6460 !strconcat(OpcodeStr#_.Suffix,
6461 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6462 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6463 _.KRCWM:$mask, vectoraddr:$dst))]>,
6464 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6467 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6468 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6469 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6470 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6471 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6472 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6473 let Predicates = [HasVLX] in {
6474 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6475 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6476 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6477 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6478 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6479 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6480 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6481 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6485 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6486 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6487 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6488 mscatterv16i32>, EVEX_V512;
6489 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6490 mscatterv8i64>, EVEX_V512;
6491 let Predicates = [HasVLX] in {
6492 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6493 vy32xmem, mscatterv8i32>, EVEX_V256;
6494 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6495 vy64xmem, mscatterv4i64>, EVEX_V256;
6496 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6497 vx32xmem, mscatterv4i32>, EVEX_V128;
6498 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6499 vx64xmem, mscatterv2i64>, EVEX_V128;
6503 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6504 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6506 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6507 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6510 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6511 RegisterClass KRC, X86MemOperand memop> {
6512 let Predicates = [HasPFI], hasSideEffects = 1 in
6513 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6514 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6518 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6519 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6521 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6522 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6524 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6525 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6527 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6528 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6530 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6531 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6533 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6534 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6536 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6537 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6539 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6540 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6542 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6543 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6545 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6546 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6548 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6549 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6551 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6552 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6554 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6555 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6557 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6558 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6560 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6561 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6563 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6564 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6566 // Helper fragments to match sext vXi1 to vXiY.
6567 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6568 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6570 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6571 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6572 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6574 def : Pat<(store VK1:$src, addr:$dst),
6576 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6577 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6579 def : Pat<(store VK8:$src, addr:$dst),
6581 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6582 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6584 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6585 (truncstore node:$val, node:$ptr), [{
6586 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6589 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6590 (MOV8mr addr:$dst, GR8:$src)>;
6592 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6593 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6594 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6595 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6598 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6599 string OpcodeStr, Predicate prd> {
6600 let Predicates = [prd] in
6601 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6603 let Predicates = [prd, HasVLX] in {
6604 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6605 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6609 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6610 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6612 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6614 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6616 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6620 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6622 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6623 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6624 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6625 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6628 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6629 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6630 let Predicates = [prd] in
6631 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6634 let Predicates = [prd, HasVLX] in {
6635 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6637 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6642 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6643 avx512vl_i8_info, HasBWI>;
6644 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6645 avx512vl_i16_info, HasBWI>, VEX_W;
6646 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6647 avx512vl_i32_info, HasDQI>;
6648 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6649 avx512vl_i64_info, HasDQI>, VEX_W;
6651 //===----------------------------------------------------------------------===//
6652 // AVX-512 - COMPRESS and EXPAND
6655 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6657 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6658 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6659 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6661 let mayStore = 1 in {
6662 def mr : AVX5128I<opc, MRMDestMem, (outs),
6663 (ins _.MemOp:$dst, _.RC:$src),
6664 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6665 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6667 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6668 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6669 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6670 [(store (_.VT (vselect _.KRCWM:$mask,
6671 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6673 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6677 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6678 AVX512VLVectorVTInfo VTInfo> {
6679 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6681 let Predicates = [HasVLX] in {
6682 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6683 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6687 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6689 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6691 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6693 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6697 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6699 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6700 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6701 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6704 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6705 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6706 (_.VT (X86expand (_.VT (bitconvert
6707 (_.LdFrag addr:$src1)))))>,
6708 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6711 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6712 AVX512VLVectorVTInfo VTInfo> {
6713 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6715 let Predicates = [HasVLX] in {
6716 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6717 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6721 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6723 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6725 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6727 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6730 //handle instruction reg_vec1 = op(reg_vec,imm)
6732 // op(broadcast(eltVt),imm)
6733 //all instruction created with FROUND_CURRENT
6734 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6736 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6737 (ins _.RC:$src1, i32u8imm:$src2),
6738 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6739 (OpNode (_.VT _.RC:$src1),
6741 (i32 FROUND_CURRENT))>;
6742 let mayLoad = 1 in {
6743 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6744 (ins _.MemOp:$src1, i32u8imm:$src2),
6745 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6746 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6748 (i32 FROUND_CURRENT))>;
6749 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6750 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6751 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6752 "${src1}"##_.BroadcastStr##", $src2",
6753 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6755 (i32 FROUND_CURRENT))>, EVEX_B;
6759 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6760 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6761 SDNode OpNode, X86VectorVTInfo _>{
6762 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6763 (ins _.RC:$src1, i32u8imm:$src2),
6764 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6765 "$src1, {sae}, $src2",
6766 (OpNode (_.VT _.RC:$src1),
6768 (i32 FROUND_NO_EXC))>, EVEX_B;
6771 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6772 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6773 let Predicates = [prd] in {
6774 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6775 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6778 let Predicates = [prd, HasVLX] in {
6779 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6781 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6786 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6787 // op(reg_vec2,mem_vec,imm)
6788 // op(reg_vec2,broadcast(eltVt),imm)
6789 //all instruction created with FROUND_CURRENT
6790 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6792 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6793 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6794 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6795 (OpNode (_.VT _.RC:$src1),
6798 (i32 FROUND_CURRENT))>;
6799 let mayLoad = 1 in {
6800 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6801 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6802 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6803 (OpNode (_.VT _.RC:$src1),
6804 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6806 (i32 FROUND_CURRENT))>;
6807 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6808 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6809 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6810 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6811 (OpNode (_.VT _.RC:$src1),
6812 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6814 (i32 FROUND_CURRENT))>, EVEX_B;
6818 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6819 // op(reg_vec2,mem_vec,imm)
6820 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6821 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6823 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6824 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6825 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6826 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6827 (SrcInfo.VT SrcInfo.RC:$src2),
6830 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6831 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6832 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6833 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6834 (SrcInfo.VT (bitconvert
6835 (SrcInfo.LdFrag addr:$src2))),
6839 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6840 // op(reg_vec2,mem_vec,imm)
6841 // op(reg_vec2,broadcast(eltVt),imm)
6842 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6844 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6847 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6848 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6849 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6850 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6851 (OpNode (_.VT _.RC:$src1),
6852 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6853 (i8 imm:$src3))>, EVEX_B;
6856 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6857 // op(reg_vec2,mem_scalar,imm)
6858 //all instruction created with FROUND_CURRENT
6859 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6860 X86VectorVTInfo _> {
6862 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6863 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6864 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6865 (OpNode (_.VT _.RC:$src1),
6868 (i32 FROUND_CURRENT))>;
6869 let mayLoad = 1 in {
6870 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6871 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6872 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6873 (OpNode (_.VT _.RC:$src1),
6874 (_.VT (scalar_to_vector
6875 (_.ScalarLdFrag addr:$src2))),
6877 (i32 FROUND_CURRENT))>;
6879 let isAsmParserOnly = 1 in {
6880 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6881 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6882 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6888 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6889 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6890 SDNode OpNode, X86VectorVTInfo _>{
6891 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6892 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6893 OpcodeStr, "$src3,{sae}, $src2, $src1",
6894 "$src1, $src2,{sae}, $src3",
6895 (OpNode (_.VT _.RC:$src1),
6898 (i32 FROUND_NO_EXC))>, EVEX_B;
6900 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6901 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6902 SDNode OpNode, X86VectorVTInfo _> {
6903 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6904 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6905 OpcodeStr, "$src3,{sae}, $src2, $src1",
6906 "$src1, $src2,{sae}, $src3",
6907 (OpNode (_.VT _.RC:$src1),
6910 (i32 FROUND_NO_EXC))>, EVEX_B;
6913 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6914 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6915 let Predicates = [prd] in {
6916 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6917 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6921 let Predicates = [prd, HasVLX] in {
6922 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6924 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6929 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6930 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6931 let Predicates = [HasBWI] in {
6932 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6933 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6935 let Predicates = [HasBWI, HasVLX] in {
6936 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6937 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6938 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6939 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6943 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6944 bits<8> opc, SDNode OpNode>{
6945 let Predicates = [HasAVX512] in {
6946 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6948 let Predicates = [HasAVX512, HasVLX] in {
6949 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6950 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6954 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6955 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6956 let Predicates = [prd] in {
6957 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6958 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6962 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6963 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6964 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6965 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6966 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6967 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6970 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6971 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6972 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6973 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6974 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6975 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6977 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6978 0x55, X86VFixupimm, HasAVX512>,
6979 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6980 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6981 0x55, X86VFixupimm, HasAVX512>,
6982 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6984 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6985 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6986 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6987 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6988 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6989 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6992 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6993 0x50, X86VRange, HasDQI>,
6994 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6995 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6996 0x50, X86VRange, HasDQI>,
6997 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6999 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
7000 0x51, X86VRange, HasDQI>,
7001 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7002 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
7003 0x51, X86VRange, HasDQI>,
7004 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7006 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
7007 0x57, X86Reduces, HasDQI>,
7008 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7009 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
7010 0x57, X86Reduces, HasDQI>,
7011 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7013 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
7014 0x27, X86GetMants, HasAVX512>,
7015 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7016 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
7017 0x27, X86GetMants, HasAVX512>,
7018 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7020 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
7021 bits<8> opc, SDNode OpNode = X86Shuf128>{
7022 let Predicates = [HasAVX512] in {
7023 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
7026 let Predicates = [HasAVX512, HasVLX] in {
7027 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7030 let Predicates = [HasAVX512] in {
7031 def : Pat<(v16f32 (ffloor VR512:$src)),
7032 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
7033 def : Pat<(v16f32 (fnearbyint VR512:$src)),
7034 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
7035 def : Pat<(v16f32 (fceil VR512:$src)),
7036 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
7037 def : Pat<(v16f32 (frint VR512:$src)),
7038 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
7039 def : Pat<(v16f32 (ftrunc VR512:$src)),
7040 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
7042 def : Pat<(v8f64 (ffloor VR512:$src)),
7043 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
7044 def : Pat<(v8f64 (fnearbyint VR512:$src)),
7045 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
7046 def : Pat<(v8f64 (fceil VR512:$src)),
7047 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
7048 def : Pat<(v8f64 (frint VR512:$src)),
7049 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
7050 def : Pat<(v8f64 (ftrunc VR512:$src)),
7051 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
7054 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
7055 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7056 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
7057 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7058 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
7059 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7060 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
7061 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7063 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7064 AVX512VLVectorVTInfo VTInfo_FP>{
7065 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
7066 AVX512AIi8Base, EVEX_4V;
7067 let isCodeGenOnly = 1 in {
7068 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
7069 AVX512AIi8Base, EVEX_4V;
7073 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
7074 EVEX_CD8<32, CD8VF>;
7075 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
7076 EVEX_CD8<64, CD8VF>, VEX_W;
7078 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7079 let Predicates = p in
7080 def NAME#_.VTName#rri:
7081 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7082 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7083 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7086 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7087 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7088 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7089 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7091 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7092 avx512vl_i8_info, avx512vl_i8_info>,
7093 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7094 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7095 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7096 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7097 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7100 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7101 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7103 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7104 X86VectorVTInfo _> {
7105 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7106 (ins _.RC:$src1), OpcodeStr,
7108 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7111 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7112 (ins _.MemOp:$src1), OpcodeStr,
7114 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7115 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7118 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7119 X86VectorVTInfo _> :
7120 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7122 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7123 (ins _.ScalarMemOp:$src1), OpcodeStr,
7124 "${src1}"##_.BroadcastStr,
7125 "${src1}"##_.BroadcastStr,
7126 (_.VT (OpNode (X86VBroadcast
7127 (_.ScalarLdFrag addr:$src1))))>,
7128 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7131 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7132 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7133 let Predicates = [prd] in
7134 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7136 let Predicates = [prd, HasVLX] in {
7137 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7139 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7144 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7145 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7146 let Predicates = [prd] in
7147 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7150 let Predicates = [prd, HasVLX] in {
7151 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7153 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7158 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7159 SDNode OpNode, Predicate prd> {
7160 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7162 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7166 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7167 SDNode OpNode, Predicate prd> {
7168 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7169 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7172 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7173 bits<8> opc_d, bits<8> opc_q,
7174 string OpcodeStr, SDNode OpNode> {
7175 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7177 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7181 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7184 (bc_v16i32 (v16i1sextv16i32)),
7185 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7186 (VPABSDZrr VR512:$src)>;
7188 (bc_v8i64 (v8i1sextv8i64)),
7189 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7190 (VPABSQZrr VR512:$src)>;
7192 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7194 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7195 let isCodeGenOnly = 1 in
7196 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
7197 ctlz_zero_undef, prd>;
7200 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7201 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7203 //===---------------------------------------------------------------------===//
7204 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7205 //===---------------------------------------------------------------------===//
7206 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7207 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7209 let isCodeGenOnly = 1 in
7210 defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7214 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7215 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7217 //===----------------------------------------------------------------------===//
7218 // AVX-512 - MOVDDUP
7219 //===----------------------------------------------------------------------===//
7221 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7222 X86VectorVTInfo _> {
7223 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7224 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7225 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7227 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7228 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7229 (_.VT (OpNode (_.VT (scalar_to_vector
7230 (_.ScalarLdFrag addr:$src)))))>,
7231 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7234 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7235 AVX512VLVectorVTInfo VTInfo> {
7237 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7239 let Predicates = [HasAVX512, HasVLX] in {
7240 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7242 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7247 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7248 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7249 avx512vl_f64_info>, XD, VEX_W;
7250 let isCodeGenOnly = 1 in
7251 defm NAME#_I: avx512_movddup_common<opc, OpcodeStr, OpNode,
7255 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7257 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7258 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7259 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7260 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7262 //===----------------------------------------------------------------------===//
7263 // AVX-512 - Unpack Instructions
7264 //===----------------------------------------------------------------------===//
7265 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7266 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7268 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7269 SSE_INTALU_ITINS_P, HasBWI>;
7270 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7271 SSE_INTALU_ITINS_P, HasBWI>;
7272 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7273 SSE_INTALU_ITINS_P, HasBWI>;
7274 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7275 SSE_INTALU_ITINS_P, HasBWI>;
7277 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7278 SSE_INTALU_ITINS_P, HasAVX512>;
7279 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7280 SSE_INTALU_ITINS_P, HasAVX512>;
7281 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7282 SSE_INTALU_ITINS_P, HasAVX512>;
7283 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7284 SSE_INTALU_ITINS_P, HasAVX512>;
7286 //===----------------------------------------------------------------------===//
7287 // AVX-512 - Extract & Insert Integer Instructions
7288 //===----------------------------------------------------------------------===//
7290 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7291 X86VectorVTInfo _> {
7293 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7294 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7295 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7296 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7299 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7302 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7303 let Predicates = [HasBWI] in {
7304 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7305 (ins _.RC:$src1, u8imm:$src2),
7306 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7307 [(set GR32orGR64:$dst,
7308 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7311 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7315 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7316 let Predicates = [HasBWI] in {
7317 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7318 (ins _.RC:$src1, u8imm:$src2),
7319 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7320 [(set GR32orGR64:$dst,
7321 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7324 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7325 (ins _.RC:$src1, u8imm:$src2),
7326 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7329 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7333 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7334 RegisterClass GRC> {
7335 let Predicates = [HasDQI] in {
7336 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7337 (ins _.RC:$src1, u8imm:$src2),
7338 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7340 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7344 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7345 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7346 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7347 [(store (extractelt (_.VT _.RC:$src1),
7348 imm:$src2),addr:$dst)]>,
7349 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7353 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7354 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7355 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7356 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7358 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7359 X86VectorVTInfo _, PatFrag LdFrag> {
7360 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7361 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7362 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7364 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7365 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7368 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7369 X86VectorVTInfo _, PatFrag LdFrag> {
7370 let Predicates = [HasBWI] in {
7371 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7372 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7373 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7375 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7377 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7381 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7382 X86VectorVTInfo _, RegisterClass GRC> {
7383 let Predicates = [HasDQI] in {
7384 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7385 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7386 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7388 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7391 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7392 _.ScalarLdFrag>, TAPD;
7396 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7398 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7400 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7401 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7402 //===----------------------------------------------------------------------===//
7403 // VSHUFPS - VSHUFPD Operations
7404 //===----------------------------------------------------------------------===//
7405 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7406 AVX512VLVectorVTInfo VTInfo_FP>{
7407 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7408 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7409 AVX512AIi8Base, EVEX_4V;
7410 let isCodeGenOnly = 1 in {
7411 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7412 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7413 AVX512AIi8Base, EVEX_4V;
7417 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7418 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7419 //===----------------------------------------------------------------------===//
7420 // AVX-512 - Byte shift Left/Right
7421 //===----------------------------------------------------------------------===//
7423 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7424 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7425 def rr : AVX512<opc, MRMr,
7426 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7427 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7428 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7430 def rm : AVX512<opc, MRMm,
7431 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7432 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7433 [(set _.RC:$dst,(_.VT (OpNode
7434 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7437 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7438 Format MRMm, string OpcodeStr, Predicate prd>{
7439 let Predicates = [prd] in
7440 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7441 OpcodeStr, v8i64_info>, EVEX_V512;
7442 let Predicates = [prd, HasVLX] in {
7443 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7444 OpcodeStr, v4i64x_info>, EVEX_V256;
7445 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7446 OpcodeStr, v2i64x_info>, EVEX_V128;
7449 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7450 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7451 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7452 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7455 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7456 string OpcodeStr, X86VectorVTInfo _dst,
7457 X86VectorVTInfo _src>{
7458 def rr : AVX512BI<opc, MRMSrcReg,
7459 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7460 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7461 [(set _dst.RC:$dst,(_dst.VT
7462 (OpNode (_src.VT _src.RC:$src1),
7463 (_src.VT _src.RC:$src2))))]>;
7465 def rm : AVX512BI<opc, MRMSrcMem,
7466 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7467 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7468 [(set _dst.RC:$dst,(_dst.VT
7469 (OpNode (_src.VT _src.RC:$src1),
7470 (_src.VT (bitconvert
7471 (_src.LdFrag addr:$src2))))))]>;
7474 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7475 string OpcodeStr, Predicate prd> {
7476 let Predicates = [prd] in
7477 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7478 v64i8_info>, EVEX_V512;
7479 let Predicates = [prd, HasVLX] in {
7480 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7481 v32i8x_info>, EVEX_V256;
7482 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7483 v16i8x_info>, EVEX_V128;
7487 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7490 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7492 let Constraints = "$src1 = $dst" in {
7493 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7494 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7495 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7496 (OpNode (_.VT _.RC:$src1),
7499 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7500 let mayLoad = 1 in {
7501 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7502 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7503 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7504 (OpNode (_.VT _.RC:$src1),
7506 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7508 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7509 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7510 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7511 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7512 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7513 (OpNode (_.VT _.RC:$src1),
7515 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7516 (i8 imm:$src4))>, EVEX_B,
7517 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7519 }// Constraints = "$src1 = $dst"
7522 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7523 let Predicates = [HasAVX512] in
7524 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7525 let Predicates = [HasAVX512, HasVLX] in {
7526 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7527 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7531 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7532 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;