1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmInstrumentation.h"
12 #include "X86Operand.h"
13 #include "llvm/ADT/StringExtras.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/IR/Function.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/MC/MCTargetOptions.h"
25 #include "llvm/Support/CommandLine.h"
30 static cl::opt<bool> ClAsanInstrumentAssembly(
31 "asan-instrument-assembly",
32 cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
35 bool IsStackReg(unsigned Reg) {
36 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
39 std::string FuncName(unsigned AccessSize, bool IsWrite) {
40 return std::string("__asan_report_") + (IsWrite ? "store" : "load") +
44 class X86AddressSanitizer : public X86AsmInstrumentation {
46 X86AddressSanitizer(const MCSubtargetInfo &STI)
47 : X86AsmInstrumentation(STI), RepPrefix(false) {}
48 virtual ~X86AddressSanitizer() {}
50 // X86AsmInstrumentation implementation:
51 virtual void InstrumentAndEmitInstruction(
52 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
53 const MCInstrInfo &MII, MCStreamer &Out) override {
54 InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
56 EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
58 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
60 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
62 EmitInstruction(Out, Inst);
65 // Should be implemented differently in x86_32 and x86_64 subclasses.
66 virtual void InstrumentMemOperandSmallImpl(
67 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
69 virtual void InstrumentMemOperandLargeImpl(
70 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
72 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
75 void InstrumentMemOperand(MCParsedAsmOperand &Op, unsigned AccessSize,
76 bool IsWrite, MCContext &Ctx, MCStreamer &Out);
77 void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
78 unsigned AccessSize, MCContext &Ctx, MCStreamer &Out);
79 void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands,
80 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
81 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
82 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
84 void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
87 // True when previous instruction was actually REP prefix.
91 void X86AddressSanitizer::InstrumentMemOperand(
92 MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
94 assert(Op.isMem() && "Op should be a memory operand.");
95 assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
96 "AccessSize should be a power of two, less or equal than 16.");
98 X86Operand &MemOp = static_cast<X86Operand &>(Op);
99 // FIXME: get rid of this limitation.
100 if (IsStackReg(MemOp.getMemBaseReg()) || IsStackReg(MemOp.getMemIndexReg()))
103 // FIXME: take into account load/store alignment.
105 InstrumentMemOperandSmallImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
107 InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
110 void X86AddressSanitizer::InstrumentMOVSBase(
111 unsigned DstReg, unsigned SrcReg, unsigned CntReg, unsigned AccessSize,
112 MCContext &Ctx, MCStreamer &Out) {
113 // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
114 // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
116 // FIXME: extract prolog and epilogue from InstrumentMemOperand()
117 // and optimize this sequence of InstrumentMemOperand() calls.
121 const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
122 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
123 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
124 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, Ctx, Out);
127 // Test -1(%SrcReg, %CntReg, AccessSize)
129 const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
130 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
131 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(), SMLoc()));
132 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, Ctx, Out);
137 const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
138 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
139 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
140 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, Ctx, Out);
143 // Test -1(%DstReg, %CntReg, AccessSize)
145 const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
146 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
147 0, Disp, DstReg, CntReg, AccessSize, SMLoc(), SMLoc()));
148 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, Ctx, Out);
152 void X86AddressSanitizer::InstrumentMOVS(
153 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
154 const MCInstrInfo &MII, MCStreamer &Out) {
155 // Access size in bytes.
156 unsigned AccessSize = 0;
158 switch (Inst.getOpcode()) {
175 InstrumentMOVSImpl(AccessSize, Ctx, Out);
178 void X86AddressSanitizer::InstrumentMOV(
179 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
180 const MCInstrInfo &MII, MCStreamer &Out) {
181 // Access size in bytes.
182 unsigned AccessSize = 0;
184 switch (Inst.getOpcode()) {
215 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
216 for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
217 assert(Operands[Ix]);
218 MCParsedAsmOperand &Op = *Operands[Ix];
220 InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
224 class X86AddressSanitizer32 : public X86AddressSanitizer {
226 static const long kShadowOffset = 0x20000000;
228 X86AddressSanitizer32(const MCSubtargetInfo &STI)
229 : X86AddressSanitizer(STI) {}
230 virtual ~X86AddressSanitizer32() {}
232 virtual void InstrumentMemOperandSmallImpl(
233 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
234 MCStreamer &Out) override;
235 virtual void InstrumentMemOperandLargeImpl(
236 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
237 MCStreamer &Out) override;
238 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
239 MCStreamer &Out) override;
242 void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
243 bool IsWrite, unsigned AddressReg) {
244 EmitInstruction(Out, MCInstBuilder(X86::CLD));
245 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
247 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP)
248 .addReg(X86::ESP).addImm(-16));
249 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
251 const std::string &Fn = FuncName(AccessSize, IsWrite);
252 MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
253 const MCSymbolRefExpr *FnExpr =
254 MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
255 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
259 void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
260 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
262 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
263 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
264 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX));
265 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
269 Inst.setOpcode(X86::LEA32r);
270 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
271 Op.addMemOperands(Inst, 5);
272 EmitInstruction(Out, Inst);
276 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
277 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
278 .addReg(X86::ECX).addImm(3));
282 Inst.setOpcode(X86::MOV8rm);
283 Inst.addOperand(MCOperand::CreateReg(X86::CL));
284 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
285 std::unique_ptr<X86Operand> Op(
286 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
287 Op->addMemOperands(Inst, 5);
288 EmitInstruction(Out, Inst);
292 MCInstBuilder(X86::TEST8rr).addReg(X86::CL).addReg(X86::CL));
293 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
294 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
295 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
298 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
299 EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::EDX)
300 .addReg(X86::EDX).addImm(7));
302 switch (AccessSize) {
307 Inst.setOpcode(X86::LEA32r);
308 Inst.addOperand(MCOperand::CreateReg(X86::EDX));
310 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
311 std::unique_ptr<X86Operand> Op(
312 X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
313 Op->addMemOperands(Inst, 5);
314 EmitInstruction(Out, Inst);
318 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX)
319 .addReg(X86::EDX).addImm(3));
322 assert(false && "Incorrect access size");
327 Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::ECX).addReg(X86::CL));
329 Out, MCInstBuilder(X86::CMP32rr).addReg(X86::EDX).addReg(X86::ECX));
330 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
332 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
333 EmitLabel(Out, DoneSym);
335 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
336 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EDX));
337 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
338 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
341 void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
342 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
344 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
345 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
346 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
350 Inst.setOpcode(X86::LEA32r);
351 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
352 Op.addMemOperands(Inst, 5);
353 EmitInstruction(Out, Inst);
356 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
357 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
358 .addReg(X86::ECX).addImm(3));
361 switch (AccessSize) {
363 Inst.setOpcode(X86::CMP8mi);
366 Inst.setOpcode(X86::CMP16mi);
369 assert(false && "Incorrect access size");
372 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
373 std::unique_ptr<X86Operand> Op(
374 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
375 Op->addMemOperands(Inst, 5);
376 Inst.addOperand(MCOperand::CreateImm(0));
377 EmitInstruction(Out, Inst);
379 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
380 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
381 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
383 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
384 EmitLabel(Out, DoneSym);
386 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
387 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
388 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
391 void X86AddressSanitizer32::InstrumentMOVSImpl(
392 unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) {
393 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
395 // No need to test when ECX is equals to zero.
396 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
397 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
399 Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
400 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
402 // Instrument first and last elements in src and dst range.
403 InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
404 X86::ECX /* CntReg */, AccessSize, Ctx, Out);
406 EmitLabel(Out, DoneSym);
407 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
410 class X86AddressSanitizer64 : public X86AddressSanitizer {
412 static const long kShadowOffset = 0x7fff8000;
414 X86AddressSanitizer64(const MCSubtargetInfo &STI)
415 : X86AddressSanitizer(STI) {}
416 virtual ~X86AddressSanitizer64() {}
418 virtual void InstrumentMemOperandSmallImpl(
419 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
420 MCStreamer &Out) override;
421 virtual void InstrumentMemOperandLargeImpl(
422 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
423 MCStreamer &Out) override;
424 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
425 MCStreamer &Out) override;
428 void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
430 Inst.setOpcode(X86::LEA64r);
431 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
433 const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
434 std::unique_ptr<X86Operand> Op(
435 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
436 Op->addMemOperands(Inst, 5);
437 EmitInstruction(Out, Inst);
440 void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
442 EmitInstruction(Out, MCInstBuilder(X86::CLD));
443 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
445 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP)
446 .addReg(X86::RSP).addImm(-16));
448 const std::string &Fn = FuncName(AccessSize, IsWrite);
449 MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
450 const MCSymbolRefExpr *FnExpr =
451 MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
452 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
456 void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
457 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
459 EmitAdjustRSP(Ctx, Out, -128);
460 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
461 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX));
462 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
463 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
466 Inst.setOpcode(X86::LEA64r);
467 Inst.addOperand(MCOperand::CreateReg(X86::RDI));
468 Op.addMemOperands(Inst, 5);
469 EmitInstruction(Out, Inst);
472 Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
473 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
474 .addReg(X86::RAX).addImm(3));
477 Inst.setOpcode(X86::MOV8rm);
478 Inst.addOperand(MCOperand::CreateReg(X86::AL));
479 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
480 std::unique_ptr<X86Operand> Op(
481 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
482 Op->addMemOperands(Inst, 5);
483 EmitInstruction(Out, Inst);
487 MCInstBuilder(X86::TEST8rr).addReg(X86::AL).addReg(X86::AL));
488 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
489 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
490 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
493 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
494 EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::ECX)
495 .addReg(X86::ECX).addImm(7));
497 switch (AccessSize) {
502 Inst.setOpcode(X86::LEA32r);
503 Inst.addOperand(MCOperand::CreateReg(X86::ECX));
505 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
506 std::unique_ptr<X86Operand> Op(
507 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
508 Op->addMemOperands(Inst, 5);
509 EmitInstruction(Out, Inst);
513 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX)
514 .addReg(X86::ECX).addImm(3));
517 assert(false && "Incorrect access size");
522 Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::EAX).addReg(X86::AL));
524 Out, MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::EAX));
525 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
527 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
528 EmitLabel(Out, DoneSym);
530 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
531 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
532 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RCX));
533 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
534 EmitAdjustRSP(Ctx, Out, 128);
537 void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
538 X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
540 EmitAdjustRSP(Ctx, Out, -128);
541 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
542 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
546 Inst.setOpcode(X86::LEA64r);
547 Inst.addOperand(MCOperand::CreateReg(X86::RAX));
548 Op.addMemOperands(Inst, 5);
549 EmitInstruction(Out, Inst);
551 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
552 .addReg(X86::RAX).addImm(3));
555 switch (AccessSize) {
557 Inst.setOpcode(X86::CMP8mi);
560 Inst.setOpcode(X86::CMP16mi);
563 assert(false && "Incorrect access size");
566 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
567 std::unique_ptr<X86Operand> Op(
568 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
569 Op->addMemOperands(Inst, 5);
570 Inst.addOperand(MCOperand::CreateImm(0));
571 EmitInstruction(Out, Inst);
574 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
575 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
576 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
578 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
579 EmitLabel(Out, DoneSym);
581 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
582 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
583 EmitAdjustRSP(Ctx, Out, 128);
586 void X86AddressSanitizer64::InstrumentMOVSImpl(
587 unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) {
588 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
590 // No need to test when RCX is equals to zero.
591 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
592 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
594 Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
595 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
597 // Instrument first and last elements in src and dst range.
598 InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
599 X86::RCX /* CntReg */, AccessSize, Ctx, Out);
601 EmitLabel(Out, DoneSym);
602 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
605 } // End anonymous namespace
607 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
610 X86AsmInstrumentation::~X86AsmInstrumentation() {}
612 void X86AsmInstrumentation::InstrumentAndEmitInstruction(
613 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
614 const MCInstrInfo &MII, MCStreamer &Out) {
615 EmitInstruction(Out, Inst);
618 void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
619 const MCInst &Inst) {
620 Out.EmitInstruction(Inst, STI);
623 X86AsmInstrumentation *
624 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
625 const MCContext &Ctx, const MCSubtargetInfo &STI) {
626 Triple T(STI.getTargetTriple());
627 const bool hasCompilerRTSupport = T.isOSLinux();
628 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
629 MCOptions.SanitizeAddress) {
630 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
631 return new X86AddressSanitizer32(STI);
632 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
633 return new X86AddressSanitizer64(STI);
635 return new X86AsmInstrumentation(STI);
638 } // End llvm namespace