1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmInstrumentation.h"
12 #include "X86Operand.h"
13 #include "X86RegisterInfo.h"
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/ADT/Triple.h"
16 #include "llvm/CodeGen/MachineValueType.h"
17 #include "llvm/IR/Function.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/MC/MCTargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
32 static cl::opt<bool> ClAsanInstrumentAssembly(
33 "asan-instrument-assembly",
34 cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
37 bool IsStackReg(unsigned Reg) {
38 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
41 bool IsSmallMemAccess(unsigned AccessSize) { return AccessSize < 8; }
43 std::string FuncName(unsigned AccessSize, bool IsWrite) {
44 return std::string("__asan_report_") + (IsWrite ? "store" : "load") +
48 class X86AddressSanitizer : public X86AsmInstrumentation {
50 struct RegisterContext {
51 RegisterContext(unsigned AddressReg, unsigned ShadowReg,
53 : AddressReg(AddressReg), ShadowReg(ShadowReg), ScratchReg(ScratchReg) {
56 unsigned addressReg(MVT::SimpleValueType VT) const {
57 return getX86SubSuperRegister(AddressReg, VT);
60 unsigned shadowReg(MVT::SimpleValueType VT) const {
61 return getX86SubSuperRegister(ShadowReg, VT);
64 unsigned scratchReg(MVT::SimpleValueType VT) const {
65 return getX86SubSuperRegister(ScratchReg, VT);
68 const unsigned AddressReg;
69 const unsigned ShadowReg;
70 const unsigned ScratchReg;
73 X86AddressSanitizer(const MCSubtargetInfo &STI)
74 : X86AsmInstrumentation(STI), RepPrefix(false) {}
75 virtual ~X86AddressSanitizer() {}
77 // X86AsmInstrumentation implementation:
78 virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
79 OperandVector &Operands,
81 const MCInstrInfo &MII,
82 MCStreamer &Out) override {
83 InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
85 EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
87 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
89 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
91 EmitInstruction(Out, Inst);
94 // Should be implemented differently in x86_32 and x86_64 subclasses.
95 virtual void StoreFlags(MCStreamer &Out) = 0;
97 virtual void RestoreFlags(MCStreamer &Out) = 0;
99 // Adjusts up stack and saves all registers used in instrumentation.
100 virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
102 MCStreamer &Out) = 0;
104 // Restores all registers used in instrumentation and adjusts stack.
105 virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
107 MCStreamer &Out) = 0;
109 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
111 const RegisterContext &RegCtx,
112 MCContext &Ctx, MCStreamer &Out) = 0;
113 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
115 const RegisterContext &RegCtx,
116 MCContext &Ctx, MCStreamer &Out) = 0;
118 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
119 MCStreamer &Out) = 0;
121 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
122 const RegisterContext &RegCtx, MCContext &Ctx,
124 void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
125 unsigned AccessSize, MCContext &Ctx, MCStreamer &Out);
127 void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands,
128 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
129 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
130 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
133 void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
135 // True when previous instruction was actually REP prefix.
139 void X86AddressSanitizer::InstrumentMemOperand(
140 X86Operand &Op, unsigned AccessSize, bool IsWrite,
141 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
142 assert(Op.isMem() && "Op should be a memory operand.");
143 assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
144 "AccessSize should be a power of two, less or equal than 16.");
145 // FIXME: take into account load/store alignment.
146 if (IsSmallMemAccess(AccessSize))
147 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
149 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
152 void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
155 MCContext &Ctx, MCStreamer &Out) {
156 // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
157 // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
158 RegisterContext RegCtx(X86::RDX /* AddressReg */, X86::RAX /* ShadowReg */,
159 IsSmallMemAccess(AccessSize)
161 : X86::NoRegister /* ScratchReg */);
163 InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
167 const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
168 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
169 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
170 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
174 // Test -1(%SrcReg, %CntReg, AccessSize)
176 const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
177 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
178 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(), SMLoc()));
179 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
185 const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
186 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
187 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
188 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
191 // Test -1(%DstReg, %CntReg, AccessSize)
193 const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
194 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
195 0, Disp, DstReg, CntReg, AccessSize, SMLoc(), SMLoc()));
196 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
199 InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
202 void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
203 OperandVector &Operands,
204 MCContext &Ctx, const MCInstrInfo &MII,
206 // Access size in bytes.
207 unsigned AccessSize = 0;
209 switch (Inst.getOpcode()) {
226 InstrumentMOVSImpl(AccessSize, Ctx, Out);
229 void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
230 OperandVector &Operands, MCContext &Ctx,
231 const MCInstrInfo &MII,
233 // Access size in bytes.
234 unsigned AccessSize = 0;
236 switch (Inst.getOpcode()) {
267 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
268 RegisterContext RegCtx(X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
269 IsSmallMemAccess(AccessSize)
271 : X86::NoRegister /* ScratchReg */);
273 for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
274 assert(Operands[Ix]);
275 MCParsedAsmOperand &Op = *Operands[Ix];
277 X86Operand &MemOp = static_cast<X86Operand &>(Op);
278 // FIXME: get rid of this limitation.
279 if (IsStackReg(MemOp.getMemBaseReg()) ||
280 IsStackReg(MemOp.getMemIndexReg())) {
284 InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
285 InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out);
286 InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
291 class X86AddressSanitizer32 : public X86AddressSanitizer {
293 static const long kShadowOffset = 0x20000000;
295 X86AddressSanitizer32(const MCSubtargetInfo &STI)
296 : X86AddressSanitizer(STI) {}
298 virtual ~X86AddressSanitizer32() {}
300 virtual void StoreFlags(MCStreamer &Out) override {
301 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
304 virtual void RestoreFlags(MCStreamer &Out) override {
305 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
308 virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
310 MCStreamer &Out) override {
311 const MCRegisterInfo* MRI = Ctx.getRegisterInfo();
312 if (MRI && FrameReg != X86::NoRegister) {
314 Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EBP));
315 if (FrameReg == X86::ESP) {
316 Out.EmitCFIAdjustCfaOffset(4 /* byte size of the FrameReg */);
317 Out.EmitCFIRelOffset(
318 MRI->getDwarfRegNum(X86::EBP, true /* IsEH */), 0);
321 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EBP).addReg(FrameReg));
322 Out.EmitCFIRememberState();
323 Out.EmitCFIDefCfaRegister(
324 MRI->getDwarfRegNum(X86::EBP, true /* IsEH */));
328 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.addressReg(MVT::i32)));
330 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.shadowReg(MVT::i32)));
331 if (RegCtx.ScratchReg != X86::NoRegister) {
333 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.scratchReg(MVT::i32)));
338 virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
340 MCStreamer &Out) override {
342 if (RegCtx.ScratchReg != X86::NoRegister) {
344 Out, MCInstBuilder(X86::POP32r).addReg(RegCtx.scratchReg(MVT::i32)));
347 Out, MCInstBuilder(X86::POP32r).addReg(RegCtx.shadowReg(MVT::i32)));
349 Out, MCInstBuilder(X86::POP32r).addReg(RegCtx.addressReg(MVT::i32)));
351 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
353 Out, MCInstBuilder(X86::POP32r).addReg(X86::EBP));
354 Out.EmitCFIRestoreState();
355 if (FrameReg == X86::ESP)
356 Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the FrameReg */);
360 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
362 const RegisterContext &RegCtx,
364 MCStreamer &Out) override;
365 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
367 const RegisterContext &RegCtx,
369 MCStreamer &Out) override;
370 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
371 MCStreamer &Out) override;
374 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
375 MCStreamer &Out, const RegisterContext &RegCtx) {
376 EmitInstruction(Out, MCInstBuilder(X86::CLD));
377 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
379 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
384 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.addressReg(MVT::i32)));
386 const std::string &Fn = FuncName(AccessSize, IsWrite);
387 MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
388 const MCSymbolRefExpr *FnExpr =
389 MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
390 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
394 void X86AddressSanitizer32::InstrumentMemOperandSmall(
395 X86Operand &Op, unsigned AccessSize, bool IsWrite,
396 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
397 unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
398 unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
399 unsigned ShadowRegI8 = RegCtx.shadowReg(MVT::i8);
401 assert(RegCtx.ScratchReg != X86::NoRegister);
402 unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
406 Inst.setOpcode(X86::LEA32r);
407 Inst.addOperand(MCOperand::CreateReg(AddressRegI32));
408 Op.addMemOperands(Inst, 5);
409 EmitInstruction(Out, Inst);
412 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
414 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
415 .addReg(ShadowRegI32)
416 .addReg(ShadowRegI32)
421 Inst.setOpcode(X86::MOV8rm);
422 Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
423 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
424 std::unique_ptr<X86Operand> Op(
425 X86Operand::CreateMem(0, Disp, ShadowRegI32, 0, 1, SMLoc(), SMLoc()));
426 Op->addMemOperands(Inst, 5);
427 EmitInstruction(Out, Inst);
431 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
432 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
433 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
434 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
436 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
438 EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
439 .addReg(ScratchRegI32)
440 .addReg(ScratchRegI32)
443 switch (AccessSize) {
448 Inst.setOpcode(X86::LEA32r);
449 Inst.addOperand(MCOperand::CreateReg(ScratchRegI32));
451 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
452 std::unique_ptr<X86Operand> Op(
453 X86Operand::CreateMem(0, Disp, ScratchRegI32, 0, 1, SMLoc(), SMLoc()));
454 Op->addMemOperands(Inst, 5);
455 EmitInstruction(Out, Inst);
459 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
460 .addReg(ScratchRegI32)
461 .addReg(ScratchRegI32)
465 assert(false && "Incorrect access size");
471 MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
472 EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
474 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
476 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
477 EmitLabel(Out, DoneSym);
480 void X86AddressSanitizer32::InstrumentMemOperandLarge(
481 X86Operand &Op, unsigned AccessSize, bool IsWrite,
482 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
483 unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
484 unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
488 Inst.setOpcode(X86::LEA32r);
489 Inst.addOperand(MCOperand::CreateReg(AddressRegI32));
490 Op.addMemOperands(Inst, 5);
491 EmitInstruction(Out, Inst);
494 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
496 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
497 .addReg(ShadowRegI32)
498 .addReg(ShadowRegI32)
502 switch (AccessSize) {
504 Inst.setOpcode(X86::CMP8mi);
507 Inst.setOpcode(X86::CMP16mi);
510 assert(false && "Incorrect access size");
513 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
514 std::unique_ptr<X86Operand> Op(
515 X86Operand::CreateMem(0, Disp, ShadowRegI32, 0, 1, SMLoc(), SMLoc()));
516 Op->addMemOperands(Inst, 5);
517 Inst.addOperand(MCOperand::CreateImm(0));
518 EmitInstruction(Out, Inst);
520 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
521 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
522 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
524 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
525 EmitLabel(Out, DoneSym);
528 void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
533 // No need to test when ECX is equals to zero.
534 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
535 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
537 Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
538 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
540 // Instrument first and last elements in src and dst range.
541 InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
542 X86::ECX /* CntReg */, AccessSize, Ctx, Out);
544 EmitLabel(Out, DoneSym);
548 class X86AddressSanitizer64 : public X86AddressSanitizer {
550 static const long kShadowOffset = 0x7fff8000;
552 X86AddressSanitizer64(const MCSubtargetInfo &STI)
553 : X86AddressSanitizer(STI) {}
555 virtual ~X86AddressSanitizer64() {}
557 virtual void StoreFlags(MCStreamer &Out) override {
558 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
561 virtual void RestoreFlags(MCStreamer &Out) override {
562 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
565 virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
567 MCStreamer &Out) override {
568 const MCRegisterInfo *RegisterInfo = Ctx.getRegisterInfo();
569 if (RegisterInfo && FrameReg != X86::NoRegister) {
570 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RBP));
571 if (FrameReg == X86::RSP) {
572 Out.EmitCFIAdjustCfaOffset(8 /* byte size of the FrameReg */);
573 Out.EmitCFIRelOffset(
574 RegisterInfo->getDwarfRegNum(X86::RBP, true /* IsEH */), 0);
577 Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RBP).addReg(FrameReg));
578 Out.EmitCFIRememberState();
579 Out.EmitCFIDefCfaRegister(
580 RegisterInfo->getDwarfRegNum(X86::RBP, true /* IsEH */));
583 EmitAdjustRSP(Ctx, Out, -128);
585 Out, MCInstBuilder(X86::PUSH64r).addReg(RegCtx.shadowReg(MVT::i64)));
587 Out, MCInstBuilder(X86::PUSH64r).addReg(RegCtx.addressReg(MVT::i64)));
588 if (RegCtx.ScratchReg != X86::NoRegister) {
590 Out, MCInstBuilder(X86::PUSH64r).addReg(RegCtx.scratchReg(MVT::i64)));
595 virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
597 MCStreamer &Out) override {
599 if (RegCtx.ScratchReg != X86::NoRegister) {
601 Out, MCInstBuilder(X86::POP64r).addReg(RegCtx.scratchReg(MVT::i64)));
604 Out, MCInstBuilder(X86::POP64r).addReg(RegCtx.addressReg(MVT::i64)));
606 Out, MCInstBuilder(X86::POP64r).addReg(RegCtx.shadowReg(MVT::i64)));
607 EmitAdjustRSP(Ctx, Out, 128);
609 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
611 Out, MCInstBuilder(X86::POP64r).addReg(X86::RBP));
612 Out.EmitCFIRestoreState();
613 if (FrameReg == X86::RSP)
614 Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the FrameReg */);
618 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
620 const RegisterContext &RegCtx,
622 MCStreamer &Out) override;
623 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
625 const RegisterContext &RegCtx,
627 MCStreamer &Out) override;
628 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
629 MCStreamer &Out) override;
632 void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
634 Inst.setOpcode(X86::LEA64r);
635 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
637 const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
638 std::unique_ptr<X86Operand> Op(
639 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
640 Op->addMemOperands(Inst, 5);
641 EmitInstruction(Out, Inst);
644 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
645 MCStreamer &Out, const RegisterContext &RegCtx) {
646 EmitInstruction(Out, MCInstBuilder(X86::CLD));
647 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
649 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
654 if (RegCtx.AddressReg != X86::RDI) {
655 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
656 RegCtx.addressReg(MVT::i64)));
658 const std::string &Fn = FuncName(AccessSize, IsWrite);
659 MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
660 const MCSymbolRefExpr *FnExpr =
661 MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
662 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
666 void X86AddressSanitizer64::InstrumentMemOperandSmall(
667 X86Operand &Op, unsigned AccessSize, bool IsWrite,
668 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
669 unsigned AddressRegI64 = RegCtx.addressReg(MVT::i64);
670 unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
671 unsigned ShadowRegI64 = RegCtx.shadowReg(MVT::i64);
672 unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
673 unsigned ShadowRegI8 = RegCtx.shadowReg(MVT::i8);
675 assert(RegCtx.ScratchReg != X86::NoRegister);
676 unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
680 Inst.setOpcode(X86::LEA64r);
681 Inst.addOperand(MCOperand::CreateReg(AddressRegI64));
682 Op.addMemOperands(Inst, 5);
683 EmitInstruction(Out, Inst);
685 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
687 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
688 .addReg(ShadowRegI64)
689 .addReg(ShadowRegI64)
693 Inst.setOpcode(X86::MOV8rm);
694 Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
695 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
696 std::unique_ptr<X86Operand> Op(
697 X86Operand::CreateMem(0, Disp, ShadowRegI64, 0, 1, SMLoc(), SMLoc()));
698 Op->addMemOperands(Inst, 5);
699 EmitInstruction(Out, Inst);
703 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
704 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
705 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
706 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
708 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
710 EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
711 .addReg(ScratchRegI32)
712 .addReg(ScratchRegI32)
715 switch (AccessSize) {
720 Inst.setOpcode(X86::LEA32r);
721 Inst.addOperand(MCOperand::CreateReg(ScratchRegI32));
723 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
724 std::unique_ptr<X86Operand> Op(
725 X86Operand::CreateMem(0, Disp, ScratchRegI32, 0, 1, SMLoc(), SMLoc()));
726 Op->addMemOperands(Inst, 5);
727 EmitInstruction(Out, Inst);
731 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
732 .addReg(ScratchRegI32)
733 .addReg(ScratchRegI32)
737 assert(false && "Incorrect access size");
743 MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
744 EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
746 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
748 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
749 EmitLabel(Out, DoneSym);
752 void X86AddressSanitizer64::InstrumentMemOperandLarge(
753 X86Operand &Op, unsigned AccessSize, bool IsWrite,
754 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
755 unsigned AddressRegI64 = RegCtx.addressReg(MVT::i64);
756 unsigned ShadowRegI64 = RegCtx.shadowReg(MVT::i64);
760 Inst.setOpcode(X86::LEA64r);
761 Inst.addOperand(MCOperand::CreateReg(AddressRegI64));
762 Op.addMemOperands(Inst, 5);
763 EmitInstruction(Out, Inst);
765 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
767 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
768 .addReg(ShadowRegI64)
769 .addReg(ShadowRegI64)
773 switch (AccessSize) {
775 Inst.setOpcode(X86::CMP8mi);
778 Inst.setOpcode(X86::CMP16mi);
781 assert(false && "Incorrect access size");
784 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
785 std::unique_ptr<X86Operand> Op(
786 X86Operand::CreateMem(0, Disp, ShadowRegI64, 0, 1, SMLoc(), SMLoc()));
787 Op->addMemOperands(Inst, 5);
788 Inst.addOperand(MCOperand::CreateImm(0));
789 EmitInstruction(Out, Inst);
792 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
793 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
794 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
796 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
797 EmitLabel(Out, DoneSym);
800 void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
805 // No need to test when RCX is equals to zero.
806 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
807 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
809 Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
810 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
812 // Instrument first and last elements in src and dst range.
813 InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
814 X86::RCX /* CntReg */, AccessSize, Ctx, Out);
816 EmitLabel(Out, DoneSym);
820 } // End anonymous namespace
822 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
823 : STI(STI), FrameReg(X86::NoRegister) {}
825 X86AsmInstrumentation::~X86AsmInstrumentation() {}
827 void X86AsmInstrumentation::InstrumentAndEmitInstruction(
828 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
829 const MCInstrInfo &MII, MCStreamer &Out) {
830 EmitInstruction(Out, Inst);
833 void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
834 const MCInst &Inst) {
835 Out.EmitInstruction(Inst, STI);
838 X86AsmInstrumentation *
839 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
840 const MCContext &Ctx, const MCSubtargetInfo &STI) {
841 Triple T(STI.getTargetTriple());
842 const bool hasCompilerRTSupport = T.isOSLinux();
843 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
844 MCOptions.SanitizeAddress) {
845 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
846 return new X86AddressSanitizer32(STI);
847 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
848 return new X86AddressSanitizer64(STI);
850 return new X86AsmInstrumentation(STI);
853 } // End llvm namespace