1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmInstrumentation.h"
12 #include "X86Operand.h"
13 #include "llvm/ADT/StringExtras.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/IR/Function.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/MC/MCTargetOptions.h"
25 #include "llvm/Support/CommandLine.h"
30 static cl::opt<bool> ClAsanInstrumentAssembly(
31 "asan-instrument-assembly",
32 cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
35 bool IsStackReg(unsigned Reg) {
36 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
39 std::string FuncName(unsigned AccessSize, bool IsWrite) {
40 return std::string("__sanitizer_sanitize_") + (IsWrite ? "store" : "load") +
44 class X86AddressSanitizer : public X86AsmInstrumentation {
46 X86AddressSanitizer(const MCSubtargetInfo &STI) : STI(STI) {}
47 virtual ~X86AddressSanitizer() {}
49 // X86AsmInstrumentation implementation:
50 virtual void InstrumentInstruction(const MCInst &Inst,
51 OperandVector &Operands, MCContext &Ctx,
52 const MCInstrInfo &MII,
53 MCStreamer &Out) override {
54 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
57 // Should be implemented differently in x86_32 and x86_64 subclasses.
58 virtual void InstrumentMemOperandImpl(X86Operand &Op, unsigned AccessSize,
59 bool IsWrite, MCContext &Ctx,
62 void InstrumentMemOperand(MCParsedAsmOperand &Op, unsigned AccessSize,
63 bool IsWrite, MCContext &Ctx, MCStreamer &Out);
64 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
65 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
66 void EmitInstruction(MCStreamer &Out, const MCInst &Inst) {
67 Out.EmitInstruction(Inst, STI);
71 const MCSubtargetInfo &STI;
74 void X86AddressSanitizer::InstrumentMemOperand(MCParsedAsmOperand &Op,
76 bool IsWrite, MCContext &Ctx,
78 assert(Op.isMem() && "Op should be a memory operand.");
79 assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
80 "AccessSize should be a power of two, less or equal than 16.");
82 X86Operand &MemOp = static_cast<X86Operand &>(Op);
83 // FIXME: get rid of this limitation.
84 if (IsStackReg(MemOp.getMemBaseReg()) || IsStackReg(MemOp.getMemIndexReg()))
87 InstrumentMemOperandImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
90 void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
91 OperandVector &Operands, MCContext &Ctx,
92 const MCInstrInfo &MII,
94 // Access size in bytes.
95 unsigned AccessSize = 0;
97 switch (Inst.getOpcode()) {
128 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
129 for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
130 assert(Operands[Ix]);
131 MCParsedAsmOperand &Op = *Operands[Ix];
133 InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
137 class X86AddressSanitizer32 : public X86AddressSanitizer {
139 X86AddressSanitizer32(const MCSubtargetInfo &STI)
140 : X86AddressSanitizer(STI) {}
141 virtual ~X86AddressSanitizer32() {}
143 virtual void InstrumentMemOperandImpl(X86Operand &Op, unsigned AccessSize,
144 bool IsWrite, MCContext &Ctx,
145 MCStreamer &Out) override;
148 void X86AddressSanitizer32::InstrumentMemOperandImpl(X86Operand &Op,
153 // FIXME: emit .cfi directives for correct stack unwinding.
154 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
157 Inst.setOpcode(X86::LEA32r);
158 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
159 Op.addMemOperands(Inst, 5);
160 EmitInstruction(Out, Inst);
162 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
164 const std::string Func = FuncName(AccessSize, IsWrite);
165 const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
166 const MCSymbolRefExpr *FuncExpr =
167 MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
168 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FuncExpr));
170 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
171 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
174 class X86AddressSanitizer64 : public X86AddressSanitizer {
176 X86AddressSanitizer64(const MCSubtargetInfo &STI)
177 : X86AddressSanitizer(STI) {}
178 virtual ~X86AddressSanitizer64() {}
180 virtual void InstrumentMemOperandImpl(X86Operand &Op, unsigned AccessSize,
181 bool IsWrite, MCContext &Ctx,
182 MCStreamer &Out) override;
185 void X86AddressSanitizer64::InstrumentMemOperandImpl(X86Operand &Op,
190 // FIXME: emit .cfi directives for correct stack unwinding.
192 // Set %rsp below current red zone (128 bytes wide) using LEA instruction to
196 Inst.setOpcode(X86::LEA64r);
197 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
199 const MCExpr *Disp = MCConstantExpr::Create(-128, Ctx);
200 std::unique_ptr<X86Operand> Op(
201 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
202 Op->addMemOperands(Inst, 5);
203 EmitInstruction(Out, Inst);
205 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
208 Inst.setOpcode(X86::LEA64r);
209 Inst.addOperand(MCOperand::CreateReg(X86::RDI));
210 Op.addMemOperands(Inst, 5);
211 EmitInstruction(Out, Inst);
214 const std::string Func = FuncName(AccessSize, IsWrite);
215 const MCSymbol *FuncSym = Ctx.GetOrCreateSymbol(StringRef(Func));
216 const MCSymbolRefExpr *FuncExpr =
217 MCSymbolRefExpr::Create(FuncSym, MCSymbolRefExpr::VK_PLT, Ctx);
218 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FuncExpr));
220 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
222 // Restore old %rsp value.
225 Inst.setOpcode(X86::LEA64r);
226 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
228 const MCExpr *Disp = MCConstantExpr::Create(128, Ctx);
229 std::unique_ptr<X86Operand> Op(
230 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
231 Op->addMemOperands(Inst, 5);
232 EmitInstruction(Out, Inst);
236 } // End anonymous namespace
238 X86AsmInstrumentation::X86AsmInstrumentation() {}
239 X86AsmInstrumentation::~X86AsmInstrumentation() {}
241 void X86AsmInstrumentation::InstrumentInstruction(const MCInst &Inst,
242 OperandVector &Operands,
244 const MCInstrInfo &MII,
247 X86AsmInstrumentation *
248 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
249 const MCContext &Ctx, const MCSubtargetInfo &STI) {
250 Triple T(STI.getTargetTriple());
251 const bool hasCompilerRTSupport = T.isOSLinux();
252 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
253 MCOptions.SanitizeAddress) {
254 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
255 return new X86AddressSanitizer32(STI);
256 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
257 return new X86AddressSanitizer64(STI);
259 return new X86AsmInstrumentation();
262 } // End llvm namespace