1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 1, constraints>;
205 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 2, constraints>;
208 //===----------------------------------------------------------------------===//
209 // Selection DAG Node Properties.
211 // Note: These are hard coded into tblgen.
213 class SDNodeProperty;
214 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
215 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
216 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
217 def SDNPOutFlag : SDNodeProperty; // Write a flag result
218 def SDNPInFlag : SDNodeProperty; // Read a flag operand
219 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
220 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
221 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
222 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
223 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
225 //===----------------------------------------------------------------------===//
226 // Selection DAG Node definitions.
228 class SDNode<string opcode, SDTypeProfile typeprof,
229 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
230 string Opcode = opcode;
231 string SDClass = sdclass;
232 list<SDNodeProperty> Properties = props;
233 SDTypeProfile TypeProfile = typeprof;
242 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
243 def timm : SDNode<"ISD::TargetConstant", SDTIntLeaf , [], "ConstantSDNode">;
244 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
245 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
246 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
247 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
248 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
249 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
250 "GlobalAddressSDNode">;
251 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
252 "GlobalAddressSDNode">;
253 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
254 "GlobalAddressSDNode">;
255 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
256 "GlobalAddressSDNode">;
257 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
258 "ConstantPoolSDNode">;
259 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
260 "ConstantPoolSDNode">;
261 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
263 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
265 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
267 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
269 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
270 "ExternalSymbolSDNode">;
271 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
272 "ExternalSymbolSDNode">;
274 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
275 [SDNPCommutative, SDNPAssociative]>;
276 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
277 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
278 [SDNPCommutative, SDNPAssociative]>;
279 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
280 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
281 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
282 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
283 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
284 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
285 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
286 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
287 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
288 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
289 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
290 def and : SDNode<"ISD::AND" , SDTIntBinOp,
291 [SDNPCommutative, SDNPAssociative]>;
292 def or : SDNode<"ISD::OR" , SDTIntBinOp,
293 [SDNPCommutative, SDNPAssociative]>;
294 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
295 [SDNPCommutative, SDNPAssociative]>;
296 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
297 [SDNPCommutative, SDNPOutFlag]>;
298 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
299 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
300 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
302 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
303 [SDNPOutFlag, SDNPInFlag]>;
305 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
306 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
307 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
308 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
309 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
310 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
311 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
312 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
313 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
314 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
315 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
316 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
319 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
320 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
321 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
322 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
323 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
324 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
325 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
326 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
327 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
328 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
329 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
330 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
331 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
332 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
333 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
335 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
336 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
337 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
339 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
340 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
341 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
342 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
344 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
345 def select : SDNode<"ISD::SELECT" , SDTSelect>;
346 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
347 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
349 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
350 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
351 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
352 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
353 def trap : SDNode<"ISD::TRAP" , SDTNone,
354 [SDNPHasChain, SDNPSideEffect]>;
356 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
357 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
359 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
360 [SDNPHasChain, SDNPSideEffect]>;
362 def atomic_cmp_swap_8 : SDNode<"ISD::ATOMIC_CMP_SWAP_8" , STDAtomic3,
363 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
364 def atomic_load_add_8 : SDNode<"ISD::ATOMIC_LOAD_ADD_8" , STDAtomic2,
365 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
366 def atomic_swap_8 : SDNode<"ISD::ATOMIC_SWAP_8", STDAtomic2,
367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
368 def atomic_load_sub_8 : SDNode<"ISD::ATOMIC_LOAD_SUB_8" , STDAtomic2,
369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
370 def atomic_load_and_8 : SDNode<"ISD::ATOMIC_LOAD_AND_8" , STDAtomic2,
371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
372 def atomic_load_or_8 : SDNode<"ISD::ATOMIC_LOAD_OR_8" , STDAtomic2,
373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
374 def atomic_load_xor_8 : SDNode<"ISD::ATOMIC_LOAD_XOR_8" , STDAtomic2,
375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
376 def atomic_load_nand_8: SDNode<"ISD::ATOMIC_LOAD_NAND_8", STDAtomic2,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
378 def atomic_load_min_8 : SDNode<"ISD::ATOMIC_LOAD_MIN_8", STDAtomic2,
379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
380 def atomic_load_max_8 : SDNode<"ISD::ATOMIC_LOAD_MAX_8", STDAtomic2,
381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
382 def atomic_load_umin_8 : SDNode<"ISD::ATOMIC_LOAD_UMIN_8", STDAtomic2,
383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
384 def atomic_load_umax_8 : SDNode<"ISD::ATOMIC_LOAD_UMAX_8", STDAtomic2,
385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
386 def atomic_cmp_swap_16 : SDNode<"ISD::ATOMIC_CMP_SWAP_16" , STDAtomic3,
387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
388 def atomic_load_add_16 : SDNode<"ISD::ATOMIC_LOAD_ADD_16" , STDAtomic2,
389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
390 def atomic_swap_16 : SDNode<"ISD::ATOMIC_SWAP_16", STDAtomic2,
391 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
392 def atomic_load_sub_16 : SDNode<"ISD::ATOMIC_LOAD_SUB_16" , STDAtomic2,
393 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
394 def atomic_load_and_16 : SDNode<"ISD::ATOMIC_LOAD_AND_16" , STDAtomic2,
395 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
396 def atomic_load_or_16 : SDNode<"ISD::ATOMIC_LOAD_OR_16" , STDAtomic2,
397 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
398 def atomic_load_xor_16 : SDNode<"ISD::ATOMIC_LOAD_XOR_16" , STDAtomic2,
399 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
400 def atomic_load_nand_16: SDNode<"ISD::ATOMIC_LOAD_NAND_16", STDAtomic2,
401 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
402 def atomic_load_min_16 : SDNode<"ISD::ATOMIC_LOAD_MIN_16", STDAtomic2,
403 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
404 def atomic_load_max_16 : SDNode<"ISD::ATOMIC_LOAD_MAX_16", STDAtomic2,
405 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
406 def atomic_load_umin_16 : SDNode<"ISD::ATOMIC_LOAD_UMIN_16", STDAtomic2,
407 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
408 def atomic_load_umax_16 : SDNode<"ISD::ATOMIC_LOAD_UMAX_16", STDAtomic2,
409 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
410 def atomic_cmp_swap_32 : SDNode<"ISD::ATOMIC_CMP_SWAP_32" , STDAtomic3,
411 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
412 def atomic_load_add_32 : SDNode<"ISD::ATOMIC_LOAD_ADD_32" , STDAtomic2,
413 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
414 def atomic_swap_32 : SDNode<"ISD::ATOMIC_SWAP_32", STDAtomic2,
415 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
416 def atomic_load_sub_32 : SDNode<"ISD::ATOMIC_LOAD_SUB_32" , STDAtomic2,
417 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
418 def atomic_load_and_32 : SDNode<"ISD::ATOMIC_LOAD_AND_32" , STDAtomic2,
419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
420 def atomic_load_or_32 : SDNode<"ISD::ATOMIC_LOAD_OR_32" , STDAtomic2,
421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
422 def atomic_load_xor_32 : SDNode<"ISD::ATOMIC_LOAD_XOR_32" , STDAtomic2,
423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
424 def atomic_load_nand_32: SDNode<"ISD::ATOMIC_LOAD_NAND_32", STDAtomic2,
425 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
426 def atomic_load_min_32 : SDNode<"ISD::ATOMIC_LOAD_MIN_32", STDAtomic2,
427 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
428 def atomic_load_max_32 : SDNode<"ISD::ATOMIC_LOAD_MAX_32", STDAtomic2,
429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
430 def atomic_load_umin_32 : SDNode<"ISD::ATOMIC_LOAD_UMIN_32", STDAtomic2,
431 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
432 def atomic_load_umax_32 : SDNode<"ISD::ATOMIC_LOAD_UMAX_32", STDAtomic2,
433 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
434 def atomic_cmp_swap_64 : SDNode<"ISD::ATOMIC_CMP_SWAP_64" , STDAtomic3,
435 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
436 def atomic_load_add_64 : SDNode<"ISD::ATOMIC_LOAD_ADD_64" , STDAtomic2,
437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
438 def atomic_swap_64 : SDNode<"ISD::ATOMIC_SWAP_64", STDAtomic2,
439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
440 def atomic_load_sub_64 : SDNode<"ISD::ATOMIC_LOAD_SUB_64" , STDAtomic2,
441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
442 def atomic_load_and_64 : SDNode<"ISD::ATOMIC_LOAD_AND_64" , STDAtomic2,
443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
444 def atomic_load_or_64 : SDNode<"ISD::ATOMIC_LOAD_OR_64" , STDAtomic2,
445 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
446 def atomic_load_xor_64 : SDNode<"ISD::ATOMIC_LOAD_XOR_64" , STDAtomic2,
447 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
448 def atomic_load_nand_64: SDNode<"ISD::ATOMIC_LOAD_NAND_64", STDAtomic2,
449 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
450 def atomic_load_min_64 : SDNode<"ISD::ATOMIC_LOAD_MIN_64", STDAtomic2,
451 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
452 def atomic_load_max_64 : SDNode<"ISD::ATOMIC_LOAD_MAX_64", STDAtomic2,
453 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
454 def atomic_load_umin_64 : SDNode<"ISD::ATOMIC_LOAD_UMIN_64", STDAtomic2,
455 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
456 def atomic_load_umax_64 : SDNode<"ISD::ATOMIC_LOAD_UMAX_64", STDAtomic2,
457 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
459 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
460 // and truncst (see below).
461 def ld : SDNode<"ISD::LOAD" , SDTLoad,
462 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
463 def st : SDNode<"ISD::STORE" , SDTStore,
464 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
465 def ist : SDNode<"ISD::STORE" , SDTIStore,
466 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
468 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
469 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
470 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
472 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
473 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
474 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
475 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
477 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
478 SDTypeProfile<1, 2, []>>;
479 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
480 SDTypeProfile<1, 3, []>>;
482 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
483 // these internally. Don't reference these directly.
484 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
485 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
487 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
488 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
490 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
491 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
494 //===----------------------------------------------------------------------===//
495 // Selection DAG Condition Codes
497 class CondCode; // ISD::CondCode enums
498 def SETOEQ : CondCode; def SETOGT : CondCode;
499 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
500 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
501 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
502 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
504 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
505 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
508 //===----------------------------------------------------------------------===//
509 // Selection DAG Node Transformation Functions.
511 // This mechanism allows targets to manipulate nodes in the output DAG once a
512 // match has been formed. This is typically used to manipulate immediate
515 class SDNodeXForm<SDNode opc, code xformFunction> {
517 code XFormFunction = xformFunction;
520 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
523 //===----------------------------------------------------------------------===//
524 // Selection DAG Pattern Fragments.
526 // Pattern fragments are reusable chunks of dags that match specific things.
527 // They can take arguments and have C++ predicates that control whether they
528 // match. They are intended to make the patterns for common instructions more
529 // compact and readable.
532 /// PatFrag - Represents a pattern fragment. This can match something on the
533 /// DAG, frame a single node to multiply nested other fragments.
535 class PatFrag<dag ops, dag frag, code pred = [{}],
536 SDNodeXForm xform = NOOP_SDNodeXForm> {
539 code Predicate = pred;
540 SDNodeXForm OperandTransform = xform;
543 // PatLeaf's are pattern fragments that have no operands. This is just a helper
544 // to define immediates and other common things concisely.
545 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
546 : PatFrag<(ops), frag, pred, xform>;
550 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
551 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
553 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
554 def immAllOnesV: PatLeaf<(build_vector), [{
555 return ISD::isBuildVectorAllOnes(N);
557 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
558 return ISD::isBuildVectorAllOnes(N);
560 def immAllZerosV: PatLeaf<(build_vector), [{
561 return ISD::isBuildVectorAllZeros(N);
563 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
564 return ISD::isBuildVectorAllZeros(N);
569 // Other helper fragments.
570 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
571 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
572 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
573 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
576 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
577 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
579 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
580 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
583 // extending load fragments.
584 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
585 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
587 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
588 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
590 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
591 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
594 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
595 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
597 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
598 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
600 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
601 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
603 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
604 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
606 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
607 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
609 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
610 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
613 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
614 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
616 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
617 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
619 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
620 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
622 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
623 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
626 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
627 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
629 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
630 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
632 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
633 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
635 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
636 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
640 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
641 (st node:$val, node:$ptr), [{
642 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
644 def store : PatFrag<(ops node:$val, node:$ptr),
645 (unindexedstore node:$val, node:$ptr), [{
646 return !cast<StoreSDNode>(N)->isTruncatingStore();
649 // truncstore fragments.
650 def truncstore : PatFrag<(ops node:$val, node:$ptr),
651 (unindexedstore node:$val, node:$ptr), [{
652 return cast<StoreSDNode>(N)->isTruncatingStore();
654 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
655 (truncstore node:$val, node:$ptr), [{
656 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
658 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
659 (truncstore node:$val, node:$ptr), [{
660 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
662 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
663 (truncstore node:$val, node:$ptr), [{
664 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
666 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
667 (truncstore node:$val, node:$ptr), [{
668 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
670 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
671 (truncstore node:$val, node:$ptr), [{
672 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
675 // indexed store fragments.
676 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
677 (ist node:$val, node:$base, node:$offset), [{
678 return !cast<StoreSDNode>(N)->isTruncatingStore();
681 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
682 (istore node:$val, node:$base, node:$offset), [{
683 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
684 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
687 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
688 (ist node:$val, node:$base, node:$offset), [{
689 return cast<StoreSDNode>(N)->isTruncatingStore();
691 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
692 (itruncstore node:$val, node:$base, node:$offset), [{
693 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
694 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
696 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
697 (pre_truncst node:$val, node:$base, node:$offset), [{
698 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
700 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
701 (pre_truncst node:$val, node:$base, node:$offset), [{
702 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
704 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
705 (pre_truncst node:$val, node:$base, node:$offset), [{
706 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
708 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
709 (pre_truncst node:$val, node:$base, node:$offset), [{
710 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
712 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
713 (pre_truncst node:$val, node:$base, node:$offset), [{
714 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
717 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
718 (istore node:$val, node:$ptr, node:$offset), [{
719 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
720 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
723 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
724 (itruncstore node:$val, node:$base, node:$offset), [{
725 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
726 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
728 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
729 (post_truncst node:$val, node:$base, node:$offset), [{
730 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
732 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
733 (post_truncst node:$val, node:$base, node:$offset), [{
734 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
736 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
737 (post_truncst node:$val, node:$base, node:$offset), [{
738 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
740 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
741 (post_truncst node:$val, node:$base, node:$offset), [{
742 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
744 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
745 (post_truncst node:$val, node:$base, node:$offset), [{
746 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
749 // setcc convenience fragments.
750 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
751 (setcc node:$lhs, node:$rhs, SETOEQ)>;
752 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
753 (setcc node:$lhs, node:$rhs, SETOGT)>;
754 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
755 (setcc node:$lhs, node:$rhs, SETOGE)>;
756 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
757 (setcc node:$lhs, node:$rhs, SETOLT)>;
758 def setole : PatFrag<(ops node:$lhs, node:$rhs),
759 (setcc node:$lhs, node:$rhs, SETOLE)>;
760 def setone : PatFrag<(ops node:$lhs, node:$rhs),
761 (setcc node:$lhs, node:$rhs, SETONE)>;
762 def seto : PatFrag<(ops node:$lhs, node:$rhs),
763 (setcc node:$lhs, node:$rhs, SETO)>;
764 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
765 (setcc node:$lhs, node:$rhs, SETUO)>;
766 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
767 (setcc node:$lhs, node:$rhs, SETUEQ)>;
768 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
769 (setcc node:$lhs, node:$rhs, SETUGT)>;
770 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
771 (setcc node:$lhs, node:$rhs, SETUGE)>;
772 def setult : PatFrag<(ops node:$lhs, node:$rhs),
773 (setcc node:$lhs, node:$rhs, SETULT)>;
774 def setule : PatFrag<(ops node:$lhs, node:$rhs),
775 (setcc node:$lhs, node:$rhs, SETULE)>;
776 def setune : PatFrag<(ops node:$lhs, node:$rhs),
777 (setcc node:$lhs, node:$rhs, SETUNE)>;
778 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
779 (setcc node:$lhs, node:$rhs, SETEQ)>;
780 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
781 (setcc node:$lhs, node:$rhs, SETGT)>;
782 def setge : PatFrag<(ops node:$lhs, node:$rhs),
783 (setcc node:$lhs, node:$rhs, SETGE)>;
784 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
785 (setcc node:$lhs, node:$rhs, SETLT)>;
786 def setle : PatFrag<(ops node:$lhs, node:$rhs),
787 (setcc node:$lhs, node:$rhs, SETLE)>;
788 def setne : PatFrag<(ops node:$lhs, node:$rhs),
789 (setcc node:$lhs, node:$rhs, SETNE)>;
791 //===----------------------------------------------------------------------===//
792 // Selection DAG Pattern Support.
794 // Patterns are what are actually matched against the target-flavored
795 // instruction selection DAG. Instructions defined by the target implicitly
796 // define patterns in most cases, but patterns can also be explicitly added when
797 // an operation is defined by a sequence of instructions (e.g. loading a large
798 // immediate value on RISC targets that do not support immediates as large as
802 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
803 dag PatternToMatch = patternToMatch;
804 list<dag> ResultInstrs = resultInstrs;
805 list<Predicate> Predicates = []; // See class Instruction in Target.td.
806 int AddedComplexity = 0; // See class Instruction in Target.td.
809 // Pat - A simple (but common) form of a pattern, which produces a simple result
810 // not needing a full list.
811 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
813 //===----------------------------------------------------------------------===//
814 // Complex pattern definitions.
818 // Pass the parent Operand as root to CP function rather
819 // than the root of the sub-DAG
820 def CPAttrParentAsRoot : CPAttribute;
822 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
823 // in C++. NumOperands is the number of operands returned by the select function;
824 // SelectFunc is the name of the function used to pattern match the max. pattern;
825 // RootNodes are the list of possible root nodes of the sub-dags to match.
826 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
828 class ComplexPattern<ValueType ty, int numops, string fn,
829 list<SDNode> roots = [], list<SDNodeProperty> props = [],
830 list<CPAttribute> attrs = []> {
832 int NumOperands = numops;
833 string SelectFunc = fn;
834 list<SDNode> RootNodes = roots;
835 list<SDNodeProperty> Properties = props;
836 list<CPAttribute> Attributes = attrs;
839 //===----------------------------------------------------------------------===//
842 def SDT_dwarf_loc : SDTypeProfile<0, 3,
843 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
844 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;