1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Type.h"
20 #include "llvm/ADT/STLExtras.h"
24 SparcV8RegisterInfo::SparcV8RegisterInfo()
25 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26 V8::ADJCALLSTACKUP) {}
28 static const TargetRegisterClass *getClass(unsigned SrcReg) {
29 if (V8::IntRegsRegisterClass->contains(SrcReg))
30 return V8::IntRegsRegisterClass;
31 else if (V8::FPRegsRegisterClass->contains(SrcReg))
32 return V8::FPRegsRegisterClass;
33 else if (V8::DFPRegsRegisterClass->contains(SrcReg))
34 return V8::DFPRegsRegisterClass;
36 std::cerr << "Error: register of unknown class found: " << SrcReg << "\n";
41 void SparcV8RegisterInfo::
42 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
43 unsigned SrcReg, int FrameIdx,
44 const TargetRegisterClass *RC) const {
45 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
46 if (RC == V8::IntRegsRegisterClass)
47 BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0)
49 else if (RC == V8::FPRegsRegisterClass)
50 BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
52 else if (RC == V8::DFPRegsRegisterClass)
53 BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
56 assert (0 && "Can't store this register to stack slot");
59 void SparcV8RegisterInfo::
60 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
61 unsigned DestReg, int FrameIdx,
62 const TargetRegisterClass *RC) const {
63 if (RC == V8::IntRegsRegisterClass)
64 BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
65 else if (RC == V8::FPRegsRegisterClass)
66 BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
68 else if (RC == V8::DFPRegsRegisterClass)
69 BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
72 assert(0 && "Can't load this register from stack slot");
75 void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator I,
77 unsigned DestReg, unsigned SrcReg,
78 const TargetRegisterClass *RC) const {
79 if (RC == V8::IntRegsRegisterClass)
80 BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
81 else if (RC == V8::FPRegsRegisterClass)
82 BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
83 else if (RC == V8::DFPRegsRegisterClass)
84 BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
86 assert (0 && "Can't copy this register");
89 void SparcV8RegisterInfo::
90 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator I) const {
92 MachineInstr &MI = *I;
93 int size = MI.getOperand (0).getImmedValue ();
94 if (MI.getOpcode () == V8::ADJCALLSTACKDOWN)
96 BuildMI (MBB, I, V8::ADDri, 2, V8::SP).addReg (V8::SP).addSImm (size);
101 SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
103 MachineInstr &MI = *II;
104 while (!MI.getOperand(i).isFrameIndex()) {
106 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
109 int FrameIndex = MI.getOperand(i).getFrameIndex();
111 // Replace frame index with a frame pointer reference
112 MI.SetMachineOperandReg (i, V8::FP);
114 // Addressable stack objects are accessed using neg. offsets from %fp
115 MachineFunction &MF = *MI.getParent()->getParent();
116 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
117 MI.getOperand(i+1).getImmedValue();
119 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
122 void SparcV8RegisterInfo::
123 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
125 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
126 MachineBasicBlock &MBB = MF.front();
127 MachineFrameInfo *MFI = MF.getFrameInfo();
129 // Get the number of bytes to allocate from the FrameInfo
130 int NumBytes = (int) MFI->getStackSize();
132 // Emit the correct save instruction based on the number of bytes in
133 // the frame. Minimum stack frame size according to V8 ABI is:
134 // 16 words for register window spill
135 // 1 word for address of returned aggregate-value
136 // + 6 words for passing parameters on the stack
138 // 23 words * 4 bytes per word = 92 bytes
140 // Round up to next doubleword boundary -- a double-word boundary
141 // is required by the ABI.
142 NumBytes = (NumBytes + 7) & ~7;
143 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
144 V8::SP).addImm(-NumBytes).addReg(V8::SP);
147 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
148 MachineBasicBlock &MBB) const {
149 MachineBasicBlock::iterator MBBI = prior(MBB.end());
150 assert(MBBI->getOpcode() == V8::RETL &&
151 "Can only put epilog before 'retl' instruction!");
152 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
155 #include "SparcV8GenRegisterInfo.inc"
157 const TargetRegisterClass*
158 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
159 switch (Ty->getTypeID()) {
160 case Type::FloatTyID: return V8::FPRegsRegisterClass;
161 case Type::DoubleTyID: return V8::DFPRegsRegisterClass;
163 case Type::ULongTyID: assert(0 && "Long values do not fit in registers!");
164 default: assert(0 && "Invalid type to getClass!");
166 case Type::SByteTyID:
167 case Type::UByteTyID:
168 case Type::ShortTyID:
169 case Type::UShortTyID:
172 case Type::PointerTyID: return V8::IntRegsRegisterClass;