1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
13 //===----------------------------------------------------------------------===//
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "InstPrinter/AMDGPUInstPrinter.h"
19 #include "R600InstrInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/MC/MCCodeEmitter.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCObjectStreamer.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/Format.h"
34 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
38 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
39 OutMI.setOpcode(MI->getOpcode());
41 for (const MachineOperand &MO : MI->explicit_operands()) {
43 switch (MO.getType()) {
45 llvm_unreachable("unknown operand type");
46 case MachineOperand::MO_FPImmediate: {
47 const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
48 assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&
49 "Only floating point immediates are supported at the moment.");
50 MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
53 case MachineOperand::MO_Immediate:
54 MCOp = MCOperand::CreateImm(MO.getImm());
56 case MachineOperand::MO_Register:
57 MCOp = MCOperand::CreateReg(MO.getReg());
59 case MachineOperand::MO_MachineBasicBlock:
60 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
61 MO.getMBB()->getSymbol(), Ctx));
63 OutMI.addOperand(MCOp);
67 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
68 AMDGPUMCInstLower MCInstLowering(OutContext);
72 if (!TM.getInstrInfo()->verifyInstruction(MI, Err)) {
73 errs() << "Warning: Illegal instruction detected: " << Err << "\n";
78 const MachineBasicBlock *MBB = MI->getParent();
79 MachineBasicBlock::const_instr_iterator I = MI;
81 while (I != MBB->end() && I->isInsideBundle()) {
87 MCInstLowering.lower(MI, TmpInst);
88 EmitToStreamer(OutStreamer, TmpInst);
91 // Disassemble instruction/operands to text.
92 DisasmLines.resize(DisasmLines.size() + 1);
93 std::string &DisasmLine = DisasmLines.back();
94 raw_string_ostream DisasmStream(DisasmLine);
96 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(),
97 *TM.getRegisterInfo());
98 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef());
100 // Disassemble instruction/operands to hex representation.
101 SmallVector<MCFixup, 4> Fixups;
102 SmallVector<char, 16> CodeBytes;
103 raw_svector_ostream CodeStream(CodeBytes);
105 MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
106 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
107 InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
108 TM.getSubtarget<MCSubtargetInfo>());
111 HexLines.resize(HexLines.size() + 1);
112 std::string &HexLine = HexLines.back();
113 raw_string_ostream HexStream(HexLine);
115 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
116 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
117 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
120 DisasmStream.flush();
121 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());