MachineInstr: introduce explicit_operands and implicit_operands ranges

Makes iteration over implicit and explicit machine operands more
explicit (har har). Insipired by code review discussion for r205565.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205680 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 440d3a1302fa2494b4ab53498d5382f2d2c26d73..217d2b166683f979e7ce067a0722a4c4e8ede3c0 100644 (file)
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -293,6 +293,22 @@ public:
   iterator_range<const_mop_iterator> operands() const {
     return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
   }
+  iterator_range<mop_iterator> explicit_operands() {
+    return iterator_range<mop_iterator>(
+        operands_begin(), operands_begin() + getNumExplicitOperands());
+  }
+  iterator_range<const_mop_iterator> explicit_operands() const {
+    return iterator_range<const_mop_iterator>(
+        operands_begin(), operands_begin() + getNumExplicitOperands());
+  }
+  iterator_range<mop_iterator> implicit_operands() {
+    return iterator_range<mop_iterator>(explicit_operands().end(),
+                                        operands_end());
+  }
+  iterator_range<const_mop_iterator> implicit_operands() const {
+    return iterator_range<const_mop_iterator>(explicit_operands().end(),
+                                              operands_end());
+  }
 
   /// Access to memory operands of the instruction
   mmo_iterator memoperands_begin() const { return MemRefs; }

diff --git a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
index f85dbaa806ffa360ac0c1b450f4adaeb9a464971..f6034dcf4d04a9094f2113757db703bb18af11f3 100644 (file)
--- a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
+++ b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
@@ -50,13 +50,10 @@ char ARM64DeadRegisterDefinitions::ID = 0;
 bool ARM64DeadRegisterDefinitions::implicitlyDefinesSubReg(
                                                        unsigned Reg,
                                                        const MachineInstr *MI) {
-  for (unsigned i = MI->getNumExplicitOperands(), e = MI->getNumOperands();
-       i != e; ++i) {
-    const MachineOperand &MO = MI->getOperand(i);
+  for (const MachineOperand &MO : MI->implicit_operands())
     if (MO.isReg() && MO.isDef())
       if (TRI->isSubRegister(Reg, MO.getReg()))
         return true;
-  }
   return false;
 }
 

diff --git a/lib/Target/R600/AMDGPUMCInstLower.cpp b/lib/Target/R600/AMDGPUMCInstLower.cpp
index 2c9909ff9d94ce096ab0914c9c597c4fdd9fce96..d65b00f018c38313a18f126138d6890874013b76 100644 (file)
--- a/lib/Target/R600/AMDGPUMCInstLower.cpp
+++ b/lib/Target/R600/AMDGPUMCInstLower.cpp
@@ -38,9 +38,7 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(MI->getOpcode());
 
-  for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
-    const MachineOperand &MO = MI->getOperand(i);
-
+  for (const MachineOperand &MO : MI->explicit_operands()) {
     MCOperand MCOp;
     switch (MO.getType()) {
     default: