1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
21 #include "MipsSubtarget.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Jump and link (call)
32 // Get the Higher 16 bits from a 32-bit immediate
33 // No relation with Mips Hi register
36 // Get the Lower 16 bits from a 32-bit immediate
37 // No relation with Mips Lo register
40 // Handle gp_rel (small data/bss sections) relocation.
43 // General Dynamic TLS
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // Floating Point Rounding
86 //===--------------------------------------------------------------------===//
87 // TargetLowering Implementation
88 //===--------------------------------------------------------------------===//
90 class MipsTargetLowering : public TargetLowering {
92 explicit MipsTargetLowering(MipsTargetMachine &TM);
94 /// LowerOperation - Provide custom lowering hooks for some operations.
95 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
97 /// getTargetNodeName - This method returns the name of a target specific
99 virtual const char *getTargetNodeName(unsigned Opcode) const;
101 /// getSetCCResultType - get the ISD::SETCC result ValueType
102 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
104 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
107 const MipsSubtarget *Subtarget;
110 // Lower Operand helpers
111 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
112 CallingConv::ID CallConv, bool isVarArg,
113 const SmallVectorImpl<ISD::InputArg> &Ins,
114 DebugLoc dl, SelectionDAG &DAG,
115 SmallVectorImpl<SDValue> &InVals) const;
117 // Lower Operand specifics
118 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
130 LowerFormalArguments(SDValue Chain,
131 CallingConv::ID CallConv, bool isVarArg,
132 const SmallVectorImpl<ISD::InputArg> &Ins,
133 DebugLoc dl, SelectionDAG &DAG,
134 SmallVectorImpl<SDValue> &InVals) const;
137 LowerCall(SDValue Chain, SDValue Callee,
138 CallingConv::ID CallConv, bool isVarArg,
140 const SmallVectorImpl<ISD::OutputArg> &Outs,
141 const SmallVectorImpl<SDValue> &OutVals,
142 const SmallVectorImpl<ISD::InputArg> &Ins,
143 DebugLoc dl, SelectionDAG &DAG,
144 SmallVectorImpl<SDValue> &InVals) const;
147 LowerReturn(SDValue Chain,
148 CallingConv::ID CallConv, bool isVarArg,
149 const SmallVectorImpl<ISD::OutputArg> &Outs,
150 const SmallVectorImpl<SDValue> &OutVals,
151 DebugLoc dl, SelectionDAG &DAG) const;
153 virtual MachineBasicBlock *
154 EmitInstrWithCustomInserter(MachineInstr *MI,
155 MachineBasicBlock *MBB) const;
157 // Inline asm support
158 ConstraintType getConstraintType(const std::string &Constraint) const;
160 /// Examine constraint string and operand type and determine a weight value.
161 /// The operand object must already have been set up with the operand type.
162 ConstraintWeight getSingleConstraintMatchWeight(
163 AsmOperandInfo &info, const char *constraint) const;
165 std::pair<unsigned, const TargetRegisterClass*>
166 getRegForInlineAsmConstraint(const std::string &Constraint,
169 std::vector<unsigned>
170 getRegClassForInlineAsmConstraint(const std::string &Constraint,
173 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
175 /// isFPImmLegal - Returns true if the target can instruction select the
176 /// specified FP immediate natively. If false, the legalizer will
177 /// materialize the FP immediate as a load from a constant pool.
178 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
180 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
181 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
182 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
183 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
184 bool Nand = false) const;
185 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
186 MachineBasicBlock *BB, unsigned Size) const;
187 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
188 MachineBasicBlock *BB, unsigned Size) const;
192 #endif // MipsISELLOWERING_H