1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56 /// make the right decision when generating code for different targets.
57 const MipsSubtarget &Subtarget;
60 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
61 SelectionDAGISel(*tm.getTargetLowering()),
62 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
64 virtual void InstructionSelect();
67 virtual const char *getPassName() const {
68 return "MIPS DAG->DAG Pattern Instruction Selection";
73 // Include the pieces autogenerated from the target description.
74 #include "MipsGenDAGISel.inc"
76 SDValue getGlobalBaseReg();
77 SDNode *Select(SDValue N);
80 bool SelectAddr(SDValue Op, SDValue N,
81 SDValue &Base, SDValue &Offset);
84 // getI32Imm - Return a target constant with the specified
85 // value, of type i32.
86 inline SDValue getI32Imm(unsigned Imm) {
87 return CurDAG->getTargetConstant(Imm, MVT::i32);
98 /// InstructionSelect - This callback is invoked by
99 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
100 void MipsDAGToDAGISel::
104 // Codegen the basic block.
106 DOUT << "===== Instruction selection begins:\n";
110 // Select target instructions for the DAG.
114 DOUT << "===== Instruction selection ends:\n";
117 CurDAG->RemoveDeadNodes();
120 /// getGlobalBaseReg - Output the instructions required to put the
121 /// GOT address into a register.
122 SDValue MipsDAGToDAGISel::getGlobalBaseReg() {
123 MachineFunction* MF = BB->getParent();
125 for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
126 ee = MF->getRegInfo().livein_end(); ii != ee; ++ii)
127 if (ii->first == Mips::GP) {
131 assert(GP && "GOT PTR not in liveins");
132 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
136 /// ComplexPattern used on MipsInstrInfo
137 /// Used on Mips Load/Store instructions
138 bool MipsDAGToDAGISel::
139 SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
141 // if Address is FI, get the TargetFrameIndex.
142 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
143 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
144 Offset = CurDAG->getTargetConstant(0, MVT::i32);
148 // on PIC code Load GA
149 if (TM.getRelocationModel() == Reloc::PIC_) {
150 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
151 (Addr.getOpcode() == ISD::TargetJumpTable)){
152 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
157 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
158 Addr.getOpcode() == ISD::TargetGlobalAddress))
162 // Operand is a result from an ADD.
163 if (Addr.getOpcode() == ISD::ADD) {
164 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
165 if (Predicate_immSExt16(CN)) {
167 // If the first operand is a FI, get the TargetFI Node
168 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
169 (Addr.getOperand(0))) {
170 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
172 Base = Addr.getOperand(0);
175 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
182 Offset = CurDAG->getTargetConstant(0, MVT::i32);
186 /// Select instructions not customized! Used for
187 /// expanded, promoted and normal instructions
188 SDNode* MipsDAGToDAGISel::
191 SDNode *Node = N.getNode();
192 unsigned Opcode = Node->getOpcode();
194 // Dump information about the Node being selected
196 DOUT << std::string(Indent, ' ') << "Selecting: ";
197 DEBUG(Node->dump(CurDAG));
202 // If we have a custom node, we already have selected!
203 if (Node->isMachineOpcode()) {
205 DOUT << std::string(Indent-2, ' ') << "== ";
206 DEBUG(Node->dump(CurDAG));
214 // Instruction Selection not handled by the auto-generated
215 // tablegen selection should be handled here.
223 SDValue InFlag = Node->getOperand(2), CmpLHS;
224 unsigned Opc = InFlag.getOpcode(), MOp;
226 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
227 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
228 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
230 if (Opcode == ISD::ADDE) {
231 CmpLHS = InFlag.getValue(0);
234 CmpLHS = InFlag.getOperand(0);
238 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
240 SDValue LHS = Node->getOperand(0);
241 SDValue RHS = Node->getOperand(1);
245 MVT VT = LHS.getValueType();
246 SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
247 SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
248 SDValue(Carry,0), RHS);
250 return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
251 LHS, SDValue(AddCarry,0));
254 /// Mul/Div with two results
258 case ISD::UMUL_LOHI: {
259 SDValue Op1 = Node->getOperand(0);
260 SDValue Op2 = Node->getOperand(1);
265 if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
266 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
268 Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
270 SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
272 SDValue InFlag = SDValue(Node, 0);
273 SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32,
275 InFlag = SDValue(Lo,1);
276 SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
278 if (!N.getValue(0).use_empty())
279 ReplaceUses(N.getValue(0), SDValue(Lo,0));
281 if (!N.getValue(1).use_empty())
282 ReplaceUses(N.getValue(1), SDValue(Hi,0));
291 SDValue MulOp1 = Node->getOperand(0);
292 SDValue MulOp2 = Node->getOperand(1);
293 AddToISelQueue(MulOp1);
294 AddToISelQueue(MulOp2);
296 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
297 SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
299 SDValue InFlag = SDValue(MulNode, 0);
301 if (MulOp == ISD::MUL)
302 return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag);
304 return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
307 /// Div/Rem operations
312 SDValue Op1 = Node->getOperand(0);
313 SDValue Op2 = Node->getOperand(1);
318 if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
319 Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
322 Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
325 SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
327 SDValue InFlag = SDValue(Node, 0);
328 return CurDAG->getTargetNode(MOp, MVT::i32, InFlag);
331 // Get target GOT address.
332 case ISD::GLOBAL_OFFSET_TABLE: {
333 SDValue Result = getGlobalBaseReg();
334 ReplaceUses(N, Result);
338 /// Handle direct and indirect calls when using PIC. On PIC, when
339 /// GOT is smaller than about 64k (small code) the GA target is
340 /// loaded with only one instruction. Otherwise GA's target must
341 /// be loaded with 3 instructions.
342 case MipsISD::JmpLink: {
343 if (TM.getRelocationModel() == Reloc::PIC_) {
344 //bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
345 SDValue Chain = Node->getOperand(0);
346 SDValue Callee = Node->getOperand(1);
347 AddToISelQueue(Chain);
348 SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
349 SDValue InFlag(0, 0);
351 if ( (isa<GlobalAddressSDNode>(Callee)) ||
352 (isa<ExternalSymbolSDNode>(Callee)) )
354 /// Direct call for global addresses and external symbols
355 SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
357 // Use load to get GOT target
358 SDValue Ops[] = { Callee, GPReg, Chain };
359 SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, MVT::i32,
360 MVT::Other, Ops, 3), 0);
361 Chain = Load.getValue(1);
362 AddToISelQueue(Chain);
364 // Call target must be on T9
365 Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag);
368 Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag);
370 AddToISelQueue(Chain);
372 // Emit Jump and Link Register
373 SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
374 MVT::Flag, T9Reg, Chain);
375 Chain = SDValue(ResNode, 0);
376 InFlag = SDValue(ResNode, 1);
377 ReplaceUses(SDValue(Node, 0), Chain);
378 ReplaceUses(SDValue(Node, 1), InFlag);
384 // Select the default instruction
385 SDNode *ResNode = SelectCode(N);
388 DOUT << std::string(Indent-2, ' ') << "=> ";
389 if (ResNode == NULL || ResNode == N.getNode())
390 DEBUG(N.getNode()->dump(CurDAG));
392 DEBUG(ResNode->dump(CurDAG));
400 /// createMipsISelDag - This pass converts a legalized DAG into a
401 /// MIPS-specific DAG, ready for instruction scheduling.
402 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
403 return new MipsDAGToDAGISel(TM);